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PGA280

www.ti.com................................................................................................................................................ SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009

Zerø-Drift, High-Voltage,

Programmable Gain INSTRUMENTATION AMPLIFIER

Check for Samples: PGA280

1

FEATURES

DESCRIPTION

23

•

WIDE INPUT RANGE: ±15.5V at ±18V SUPPLY

The PGA280 is a high-precision instrumentation

amplifier with digitally-controllable gain and signal

integrity test capability. This device offers low offset

voltage, near-zero offset and gain drift, excellent

linearity, and nearly no 1/f noise with superior

common-mode and supply rejection to support

high-resolution precision measurement. The 36V

supply capability and wide, high-impedance input

range comply with requirements for universal signal

measurement.

•

BINARY GAIN STEPS: 128V/V to 1/8V/V

ADDITIONAL SCALING FACTOR: 1V/V and

1⅜V/V

•

LOW OFFSET VOLTAGE: 3μV at G = 128

NEAR-ZERO LONG-TERM DRIFT OF OFFSET

VOLTAGE

•

NEAR-ZERO GAIN DRIFT: 0.5ppm/°C

EXCELLENT LINEARITY: 1.5ppm

EXCELLENT CMRR: 140dB

Special circuitry prevents inrush currents from

multiplexer (MUX) switching. In addition, the input

switch matrix enables easy reconfiguration and

system-level diagnostics—overload conditions are

indicated.

HIGH INPUT IMPEDANCE

VERY LOW 1/f NOISE

DIFFERENTIAL SIGNAL OUTPUT

OVERLOAD DETECTION

The configurable general-purpose input/output

(GPIO) offers several control and communication

features. The SPI can be expanded to communicate

with more devices, supporting isolation with only four

INPUT CONFIGURATION SWITCH MATRIX

WIRE BREAK TEST CURRENT

EXPANDABLE SPI™ WITH CHECKSUM

GENERAL-PURPOSE I/O PORT

TSSOP-24 PACKAGE

ISO couplers. The PGA280 is available in

a

TSSOP-24 package and is specified from –40°C to

+105°C.

RELATED PRODUCTS

FEATURES

APPLICATIONS

PRODUCT

•

HIGH-PRECISION SIGNAL INSTRUMENTATION

MULTIPLEXED DATA ACQUISITION

HIGH-VOLTAGE ANALOG INPUT AMPLIFIER

UNIVERSAL INDUSTRIAL ANALOG INPUT

23-bit resolution, ΔΣ analog-to-digital converter

ADS1259

Chopper-stabilized instrumentation amplifier,

RR I/O, 5V single-supply

INA333

High-precision PGA, G = 1, 10, 100, 1000

PGA204

PGA206

High-precision PGA, JFET Input, G = 1, 2, 4, 8

+15V

-15V

+5V

PGA280

INP2

Switch

Matrix

and

INN2

ADC

(ADS1259)

Gain

Network

100mA

Source

Sink and

INP1

Buffer

MUX

INN1

Control Register

Address

7xGPIO

SPI Interface

SPI

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

SPI is a trademark of Motorola.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

PGA280

SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE INFORMATION⁽¹⁾

PACKAGE

DESIGNATOR

PACKAGE

MARKING

PRODUCT

PACKAGE-LEAD

PGA280

TSSOP-24

PW

PGA280A

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range, unless otherwise noted.

PGA280

UNIT

V

VSN to VSP

40

Supply Voltage

VSON to VSOP, and DGND to DVDD

6

VSN – 0.5 to VSP + 0.5

±10

V

Signal Input Terminals, Voltage⁽²⁾

Signal Input Terminals, Current⁽²⁾

Output Short-Circuit⁽³⁾

V

mA

Continuous

Operating Temperature

–55 to +140

–65 to +150

+150

°C

V

Storage Temperature

Junction Temperature

ESD Ratings

Human Body Model (HBM)

2000

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

(2) Terminals are diode-clamped to the power-supply (VON and VOP) rails. Signals that can swing more than 0.5V beyond the supply rails

must be current-limited.

(3) Short-circuit to VSON or VSOP, respectively, DGND or DVDD.

2

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www.ti.com................................................................................................................................................ SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009

ELECTRICAL CHARACTERISTICS

Boldface limits apply over the specified temperature range, T_A= –40°C to +105°C.

At T_A= +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, R_L= 2.5kΩ to VSOP/2 =

VOCM, G = 1V/V, using internal clock, BUF inactive, V_CM= 0V, and differential input and output, unless otherwise noted.

PGA280

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

INPUT

Offset Voltage, RTI⁽¹⁾

V_OS

Gain = 1V/V, 1.375V/V

Gain = 128V/V

±50

±3

±250

±15

μV

vs Temperature⁽²⁾

dV_OS/dT

Gain = 1V/V

±0.2

±0.03

±0.6

±0.17

μV/°C

Gain = 128V/V

VSP – VSN = 10 and 36V,

Gain = 1V/V, 128V/V

vs Power Supply, RTI

PSR

±0.3

±3

μV/V

vs External Clock, RTI⁽³⁾

dV_OS/df

0.8MHz to 1.2MHz, Gain = 1V/V

0.8MHz to 1.2MHz, Gain = 128V/V

Gain=128

±0.05

±0.001

3.5

μV/kHz

nV/month

GΩ

Long-Term Stability⁽⁴⁾

Input Impedance

Single-ended and Differential

Single-ended

>1

Input Capacitance, IN1 / IN2

Input Voltage Range

12 / 8

pF

Gain = 1V/V, Gain = 128V/V

Gain = 1V/V

(VSN) + 2.5

(VSP) – 2.5

±3

V

Common-Mode Rejection, RTI

CMR

±0.3

±0.08

±0.1

μV/V

Gain = 128V/V

±0.8

Over Temperature

Gain = 128V/V

±1.5

SINGLE-ENDED OUTPUT

CONNECTION

Offset Voltage, RTI, SE Out

V_OS

Gain = 1V/V, 1.375V/V, SE

Gain = 128V/V, SE

Gain = 1V/V, SE

±120

±3

μV

vs Temperature, SE Out

dV_OS/dT

0.6

μV/°C

Gain = 64V/V, SE

0.05

INPUT BIAS CURRENT⁽³⁾

Bias Current

I_B

Gain = 1V/V

±0.3

±0.8

±0.6

±0.1

±0.9

±1

±2

nA

Gain = 128V/V

Over Temperature

Offset Current

I_B

I_OS

Gain = 1V/V, Gain = 128V/V

±2

±0.5

±2

Over Temperature

NOISE

Voltage Noise, RTI; Target

f = 0.01Hz to 10Hz

f = 1kHz

e_NI

R_S= 0Ω, G = 128

R_S= 0Ω, G = 1

420

22

nV_PP

nV/√Hz

μV_PP

f = 0.01Hz to 10Hz

f = 1kHz

4.5

240

nV/√Hz

Current Noise, RTI

f = 0.01Hz to 10Hz

f = 1kHz

I_N

R_S= 10MΩ, G = 128

1.7

90

pA_PP

fA/√Hz

(1) RTI: Referred to input.

(2) Specified by design; not production tested.

(3) See Application Information section and typical characteristic graphs.

(4) 300-hour life test at +150°C demonstrated randomly distributed variation in the range of measurement limits.

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ELECTRICAL CHARACTERISTICS (continued)

Boldface limits apply over the specified temperature range, T_A= –40°C to +105°C.

At T_A= +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, R_L= 2.5kΩ to VSOP/2 =

VOCM, G = 1V/V, using internal clock, BUF inactive, V_CM= 0V, and differential input and output, unless otherwise noted.

PGA280

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

GAIN

Output Swing: ±4.5V⁽⁵⁾

Range of Input Gain

⅛ to 128

1 and 1⅜

±0.03

-0.5

V/V

Range of Output Gain: 1V/V and 1⅜

Gain Error, All Binary Steps

All Gains

No Load, All Gains Except G = 128V/V

No Load, G = 128V/V

±0.15

±2

%

vs Temperature⁽⁶⁾

ppm/°C

(7)

-1

±3

Gain Step Matching⁽⁸⁾(Gain to gain)

Nonlinearity

No Load, All Gains

No Load, All Gains⁽⁹⁾

See Typical Characteristics

1.5

10

ppm

Over Temperature⁽⁶⁾

No Load, All Gains

3

ppm

OUTPUT

Voltage Output Swing from Rail⁽⁸⁾

VSOP = 5V, Load Current 2mA

40

100

mV

pF

VSOP = 2.7V, Load Current 1.5mA

Capacitive Load Drive

Short-Circuit Current

Output Resistance

500

15

I_SC

To VSOP/2, Gain = 1.375V/V

Each output VOP and VON

7

25

mA

mΩ

200

(VSON) +

0.1

(VSOP) –

0.1

VOLTAGE RANGE FOR VOCM

VSP–2V > VOCM

V

Bias Current into VOCM

VOCM Input Resistance

INTERNAL OSCILLATOR

I_B

3

1

100

nA

GΩ

(8)

Frequency of Internal Clock⁽⁶⁾

0.8

1

1.2

MHz

Ext. Oscillator Frequency Range

FREQUENCY RESPONSE

Gain Bandwidth Product⁽⁸⁾

GBP

SR

G > 4

6

1

2

1

MHz

V/μs

Slew Rate⁽⁸⁾, 4V_PPOutput Step

G = 1, C_L= 100pF, BUF On

G = 8, C_L= 100pF

G = 128, C_L= 100pF

Settling Time⁽⁸⁾

t_S

0.01%

G = 8, V_O= 8V_PPStep

20

30

40

8

μs

0.001%

0.01%

G = 128, V_O= 8V_PPStep

0.5V Over Supply, G = ⅛ to 128

±5.5V_PInput, G = 1V/V

0.001%

Overload Recovery, Input⁽⁸⁾

Overload Recovery, Output⁽⁸⁾

INPUT MULTIPLEXER (Two-Channel)

Crosstalk, INP1 to INP2

Series-Resistance⁽⁸⁾—see Figure 44

Switch On-Resistance⁽⁸⁾

Current Source and Sink⁽⁸⁾

INPUT CURRENT BUFFER (BUF)

Offset Voltage⁽⁸⁾

6

At dc; Gain = 128V/V

< –130

600

dB

Ω

450

Ω

To GND

70

95

125

μA

V_OS

Buffer Active

15

mV

(5) Gains smaller than ½ are measured with smaller output swing.

(6) Specified by design; not production tested.

(7) See Figure 10 for typical gain error drift of various gain settings.

(8) See Application Information section and typical characteristic graphs.

(9) Only G = 1 is production tested.

4

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www.ti.com................................................................................................................................................ SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009

ELECTRICAL CHARACTERISTICS (continued)

Boldface limits apply over the specified temperature range, T_A= –40°C to +105°C.

At T_A= +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, R_L= 2.5kΩ to VSOP/2 =

VOCM, G = 1V/V, using internal clock, BUF inactive, V_CM= 0V, and differential input and output, unless otherwise noted.

PGA280

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL I/O

Supply: 2.7V to 5.5V

Input (Logic Low Threshold)

Input (Logic High Threshold)

Output (Logic Low)

0

(DVDD)x0.2

DVDD

V

0.8x(DVDD)

I_OUT= 4mA, Sink

0.7

V

Output (Logic High)

I_OUT= 2mA, Source

DVDD – 0.5

V

SCLK, Frequency

10

MHz

POWER SUPPLY: Input Stage (VSN – VSP)

Specified Voltage Range

10

36

V

Operating Voltage Range

10 to 38

2.4

V

Quiescent Current (VSP)

I_Q

3

mA

Quiescent Current (VSN)

2.1

POWER SUPPLY: Output Stage (VSOP – VSON)

Specified Voltage Range

VSP – 1.5V ≥ VSOP

2.7

5.5

V

Voltage Range for VSOP, Upper Limit

(VSP – 2V) > VOCM, (VSP – 5V) > VSON

(VSP)

V

(VSN) to

(VSP) – 5

Voltage Range for VSON

(VSP – 2V) > VOCM, VSP ≥ VSOP

V

Quiescent Current

I_Q

VSOP

0.75

1

mA

POWER SUPPLY: Digital (DVDD – DGND)

Specified Voltage Range

5.5

V

Voltage Range for DVDD, Upper Limit

Voltage Range for DGND, Lower Limit

(VSP) – 1

(VSN)

Static Condition, No External Load,

DVDD = 3V

Quiescent Current⁽¹⁰⁾

I_Q

0.07

0.13

mA

TEMPERATURE RANGE

Specified Range

Operating Range

Thermal Resistance

SSOP

–40

–55

+105

+140

°C

θ_JA

High-K Board, JESD51

80

°C/W

(10) See Application Information section and typical characteristic graphs.

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PIN CONFIGURATION

TSSOP-24

DW PACKAGE

(TOP VIEW)

VON

VOP

1

2

24 GPIO0

23 GPIO1

22 GPIO2

21 GPIO3

20 GPIO4

19 GPIO5

18 GPIO6

VOCM

VSOP

VSON

VSP

3

4

5

6

PGA280

INP2

7

INN2

INP1

8

17

CS

9

16 SCLK

15 SDI

INN1

10

VSN 11

14 SDO

13 DVDD

DGND 12

PIN DESCRIPTIONS

PIN NO.

NAME

VON

DESCRIPTION

Inverting signal output

Noninverting signal output

PIN NO.

NAME

DVDD

SDO

DESCRIPTION

Digital supply

1

2

13

VOP

14

SPI slave data output

3

VOCM

VSOP

VSON

VSP

Input, output common-mode voltage

Positive supply for output

Negative supply for output, AGND

Positive high-voltage supply

AUX input, noninverting

AUX input, inverting

15

16

17

18

19

20

21

22

23

24

SDI

SPI slave data input

4

SCLK

CS

SPI clock input

5

SPI chip select input; active low

GPIO 6, SYNC (in), OSC (out), ECS6

GPIO 5, BUFA (out), ECS5

GPIO 4, BUFT (in), ECS4

GPIO 3, EF (out), ECS3

GPIO 2, ECS2, MUX2

6

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

7

INP2

8

INN2

INP1

9

Signal input, noninverting

Signal input, inverting

10

11

12

INN1

VSN

Negative high-voltage supply

Digital ground

GPIO 1, ECS1, MUX1

DGND

GPIO 0, ECS0, MUX0

6

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TYPICAL CHARACTERISTICS

At T_A= +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, R_L= 2.5kΩ to VSOP/2 =

VOCM, G = 1V/V, using internal clock, BUF inactive, V_CM= 0V, and differential input and output, unless otherwise noted.

OFFSET VOLTAGE PRODUCTION DISTRIBUTION (G = 128)

OFFSET VOLTAGE PRODUCTION DISTRIBUTION (G = 1)

50

45

40

35

30

25

20

15

10

5

50

45

40

35

30

25

20

15

10

5

0

Offset Voltage (mV)

Figure 1.

Figure 2.

OFFSET VOLTAGE DRIFT DISTRIBUTION (G = 128)

OFFSET VOLTAGE DRIFT DISTRIBUTION (G = 1)

50

45

40

35

30

25

20

15

10

5

50

45

40

35

30

25

20

15

10

5

0

Offset Voltage Drift (mV/°C)

Figure 3.

Figure 4.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, R_L= 2.5kΩ to VSOP/2 =

VOCM, G = 1V/V, using internal clock, BUF inactive, V_CM= 0V, and differential input and output, unless otherwise noted.

COMMON-MODE REJECTION DISTRIBUTION (G = 128)

COMMON-MODE REJECTION DISTRIBUTION (G = 1)

80

120

70

60

50

40

30

20

10

0

100

80

60

40

20

0

Common-Mode Rejection Ratio (mV/V)

Figure 5.

Figure 6.

GAIN ERROR DISTRIBUTION (G = 128)

GAIN ERROR DISTRIBUTION (G = 1)

30

70

60

50

40

30

20

10

0

25

20

15

10

5

0

Gain Error (%)

Figure 7.

Figure 8.

8

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, R_L= 2.5kΩ to VSOP/2 =

VOCM, G = 1V/V, using internal clock, BUF inactive, V_CM= 0V, and differential input and output, unless otherwise noted.

GAIN ERROR DRIFT DISTRIBUTION vs

GAIN ERROR vs GAIN SETTING

GAIN SETTING (MEAN with ±3σ)

0.15

0.10

0.05

0

3

2

Selected samples with typical performance

1

0

-0.05

-0.10

-0.15

-1

-2

-3

1

1³

8

2

4

8

16 32 64 128

1/8 1/4 1/2

Gain Setting (V/V)

Figure 9.

Figure 10.

MAXIMUM GAIN ERROR DEVIATION BETWEEN

GAIN ERROR DISTRIBUTION vs

SEQUENTIAL GAIN SETTINGS (MEAN with ±3σ)

GAIN SETTING (MEAN with ±3σ)

0.20

0.15

0.10

0.05

0

0.20

0.15

0.10

0.05

0

-0.05

-0.10

-0.15

-0.20

-0.05

-0.10

-0.15

-0.20

Gain Setting (V/V)

Gain Setting Change

Figure 11.

Figure 12.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, R_L= 2.5kΩ to VSOP/2 =

VOCM, G = 1V/V, using internal clock, BUF inactive, V_CM= 0V, and differential input and output, unless otherwise noted.

POWER-SUPPLY REJECTION vs FREQUENCY

COMMON-MODE REJECTION vs FREQUENCY

140

120

100

80

140

120

100

80

VSN

VSP

60

40

20

0

10

100

1k

10k

100k

10

100

1k

10k

100k

Frequency (Hz)

Figure 13.

Figure 14.

INPUT-REFERRED NOISE SPECTRUM

SMALL-SIGNAL GAIN vs FREQUENCY

60

50

100

10

40

G = 1/8

30

20

1

G = 1

10

G = 4

0

0.1

0.01

G = 128

1

-10

-20

10

100

1k

10k

100k

1M

10M

0.1

10

100

1k

10k

100k

Frequency (Hz)

Figure 15.

Figure 16.

BIAS CURRENT vs GAIN SETTING

INPUT VOLTAGE RANGE LIMITS vs TEMPERATURE

2.0

3.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

2.5

2.0

IR+

1.5

1.0

IR-

0.5

0

1

2

4

8

16

32

64

128

-50

-25

0

25

50

75

100

125

150

Temperature (°C)

Gain Setting (V/V)

Figure 17.

Figure 18.

10

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, R_L= 2.5kΩ to VSOP/2 =

VOCM, G = 1V/V, using internal clock, BUF inactive, V_CM= 0V, and differential input and output, unless otherwise noted.

INPUT BIAS CURRENT DISTRIBUTION (G = 128)

INPUT BIAS CURRENT DISTRIBUTION (G = 1)

80

90

80

70

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

Bias Current (nA)

Figure 19.

Figure 20.

INPUT BIAS CURRENT AND INPUT OFFSET CURRENT

vs TEMPERATURE

INPUT OFFSET CURRENT DISTRIBUTION (G = 1, G = 128)

10

70

8

60

50

40

30

20

10

0

6

I_BIAS

4

2

0

-2

-4

-6

-8

-10

I_OFFSET

IN1_I_BIAS_1

IN1_I_BIAS_128

IN1_I_OFFSET_1

IN1_I_OFFSET_128

-50

-25

0

25

50

75

100

125

150

Temperature (°C)

Input Offset Current (nA)

Figure 21.

Figure 22.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, R_L= 2.5kΩ to VSOP/2 =

VOCM, G = 1V/V, using internal clock, BUF inactive, V_CM= 0V, and differential input and output, unless otherwise noted.

DIGITAL SUPPLY CURRENT

QUIESCENT CURRENT FROM SUPPLIES (VSP AND VSOP)

vs TEMPERATURE

WITH AND WITHOUT SPI COMMUNICATION

vs TEMPERATURE

3.0

90

85

80

75

70

65

60

1.0

0.9

0.8

0.7

0.6

0.5

0.4

I_DVDD(with SPI)

2.5

I_QVSP

2.0

I_DVDD(no SPI)

1.5

I_QVSOP

1.0

0.5

0

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

Temperature (°C)

Figure 23.

Figure 24.

GAIN NONLINEARITY WITH END-POINT CALIBRATION (G = 1)

GAIN NONLINEARITY vs TEMPERATURE

10

9

8

7

6

5

4

3

2

1

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

Selected samples with typical performance

-10

-50

-25

0

25

50

75

100

125

150

-4

-3

-2

-1

0

1

2

3

4

Temperature (°C)

Input/Output Voltage (V)

Figure 25.

Figure 26.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, R_L= 2.5kΩ to VSOP/2 =

VOCM, G = 1V/V, using internal clock, BUF inactive, V_CM= 0V, and differential input and output, unless otherwise noted.

POSITIVE OUTPUT CURRENT LIMIT DISTRIBUTION

NEGATIVE OUTPUT CURRENT LIMIT DISTRIBUTION

16

14

12

10

8

12

10

8

6

4

2

0

Positive Current Limit (mA)

Negative Current Limit (mA)

Figure 27.

Figure 28.

OUTPUT SWING TO RAIL vs TEMPERATURE

(VSOP – VSON = 5V)

OUTPUT CURRENT LIMIT vs TEMPERATURE

20

19

18

17

100

90

80

70

60

16

Negative

15

14

13

50

40

30

20

10

0

Positive Rail

Negative Rail

Positive

12

11

10

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

Temperature (°C)

Figure 29.

Figure 30.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, R_L= 2.5kΩ to VSOP/2 =

VOCM, G = 1V/V, using internal clock, BUF inactive, V_CM= 0V, and differential input and output, unless otherwise noted.

SWITCH-ON RESISTANCE AND SERIES INPUT RESISTANCE

vs COMMON-MODE VOLTAGE AT VARIOUS SUPPLY

VOLTAGES

SWITCH-ON RESISTANCE AND SERIES INPUT RESISTANCE

vs TEMPERATURE

800

1600

Series In R

Switch On

1400

700

600

at V_S= ±10V

at V_S= ±5V

1200

Switch On

at V_S= ±15V

Switch On

V_S= ±15V

Series Input

Resistance

500

1000

800

600

400

200

0

400

300

200

100

0

Switch On

at V_S= ±18V

-50

-25

0

25

50

75

100

125

150

-20

-15

-10

-5

0

5

10

15

20

Temperature (°C)

Common-Mode Voltage (V)

Figure 31.

Figure 32.

WIRE BREAK CURRENT DISTRIBUTION

WIRE BREAK CURRENT MAGNITUDE vs TEMPERATURE

100

45

40

35

30

25

20

15

10

5

Wire Break +

Wire Break -

98

96

Wire Break Positive

94

92

90

Wire Break Negative

88

86

84

82

80

0

-50

-25

0

25

50

75

100

125

150

Temperature (°C)

Wire Break Current (mA)

Figure 33.

Figure 34.

14

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, R_L= 2.5kΩ to VSOP/2 =

VOCM, G = 1V/V, using internal clock, BUF inactive, V_CM= 0V, and differential input and output, unless otherwise noted.

INFLUENCE OF EXTERNAL CLOCK FREQUENCY TO

VOS PERFORMANCE (G = 128)

INFLUENCE OF EXTERNAL CLOCK FREQUENCY TO

VOS PERFORMANCE (G = 1)

80

70

60

50

40

30

20

10

0

25

20

15

10

5

0

DV_OS(mV/kHz)

Figure 35.

Figure 36.

STEP RESPONSE (G = 128)

STEP RESPONSE (G = 8)

Diff Signal

Output

(Right Scale)

Diff Signal

Output

(Right Scale)

INN1

(Left Scale)

INN1 Single-Ended

(INP1 to GND)

(Left Scale)

Error Flag

10ms/div

Figure 37.

Figure 38.

STEP RESPONSE (G = 1)

OUTPUT OVERLOAD RECOVERY

G = 1, VSOP (5V)

Diff Signal Output

(Right Scale)

VON (1V/div)

INN1 (5V/div)

INN1

(INP1 to GND)

(Left Scale)

VOP (1V/div)

VSON (GND)

EF_OUT_ERR

Error Flag (Not Latched)

10ms/div

Figure 39.

Figure 40.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, R_L= 2.5kΩ to VSOP/2 =

VOCM, G = 1V/V, using internal clock, BUF inactive, V_CM= 0V, and differential input and output, unless otherwise noted.

OSCILLATOR FREQUENCY vs

TEMPERATURE

INPUT CURRENT BUFFER OFFSET VOLTAGE DISTRIBUTION

30

1.20

1.15

1.19

1.05

1.00

0.95

0.90

0.85

0.80

25

20

15

10

5

0

-50

-25

0

25

50

75

100

125

150

Temperature (°C)

Buffer Offset Voltage (mV)

Figure 41.

Figure 42.

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APPLICATION INFORMATION

DESCRIPTION

The PGA280 is a universal high-voltage instrumentation amplifier with digital gain control. It offers excellent dc

precision and long-term stability using modern chopper technology with internal filters that minimize

chopper-related noise. The input gain extends from ⅛V/V (attenuation) to 128V/V in binary steps. The output

stage offers a gain multiplying factor of 1V/V and 1⅜V/V for optimal gain adjustment. The output stage connects

to the low-voltage (5V or 3V) supply. Figure 43 shows a block diagram of the device.

VSP

VSOP

VSN

INP1

INN1

INP2

INN2

VOP

MUX

Switch Network,

Current Source

and Sink,

Gain

VOCM

VON

and Buffer

SPI

Digital I/O

Control Registers

7x GPIO

DGND

DVDD

VSON

Figure 43. PGA280 Block Diagram

A signal multiplexer provides two differential inputs. Several signal switches allow signal diagnosis of wire break,

input disconnect, single-ended (versus differential), and shorted inputs.

The supply voltage of up to ±18V offers a wide common-mode range with high input impedance; therefore, large

common-mode noise signals and offsets can be suppressed.

A pair of high-speed current buffers can be activated to avoid inrush currents during fast signal transients, such

as those generated from switching the signal multiplexers. This feature minimizes discharge errors in passive

signal input filters in front of the multiplexer.

The fully differential signal output matches the inputs of modern high-resolution and high-accuracy

analog-to-digital converters (ADCs), including Delta-Sigma (ΔΣ) as well as successive-approximation response

(SAR) converters. The supply voltage for the output stage is normally connected together with the converter

supply, thus preventing signal overloads from the high-voltage analog supply.

Internal error detection in the input and output stage provides individual information about the signal condition.

Integrating ADCs may hide momentary overloads. Together with the input switch matrix, extensive signal and

error diagnosis is made possible.

The serial peripheral interface (SPI) provides write and read access to internal registers. These registers control

gain, the current buffer, input switches, and the general-purpose input/output (GPIO) or special function pins, as

well as configuration and diagnostics.

The GPIO port controls the multiplexer (MUX) and switches and indicates internal conditions; it can also be

individually configured for output or input. A special CS mode for the GPIO extends the communication to other

external SPI devices, such as data converters or shift registers. This special function is intended for SPI

communication via a minimum number of isolation couplers. Additional proof for communication integrity is

provided by an optional checksum byte following each communication block.

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FUNCTIONAL BLOCKS

Both high-impedance input amplifiers are symmetrical, and have low noise and excellent dc precision. These

amplifiers are connected to a resistor network and provide a gain range from 128V/V down to an attenuation of

⅛. The PGA280 architecture rejects common-mode offsets and noise over a wide bandwidth.

The PGA280 features additional current buffers placed in front of the precision amplifier that can be activated on

demand. When activated, these additional current buffers avoid problems that result from input current during

dynamic overloads, such as the fast signal transient that follows the channel switching from a multiplexer.

Without the use of the additional current buffers, the fast signal transient would overload the precision amplifiers

and high bias currents could flow into the protection clamp until the amplifiers recover from the overload. This

momentary current can influence the signal source or passive filters in front of the multiplexer and generate long

settling tails. Activating this current buffer avoids such an overload current pulse. The buffer disconnects

automatically after an adjustable time. For continuous signal measurement, the additional current buffers are not

used.

The switches in the input provide signal diagnostic capability and offer an auxiliary input channel (INP2 and

INN2; see Figure 44). Both channels can be switched to diagnose or test conditions, such as a ground-referred,

single-ended voltage measurement for either input. In this mode, each of the signal inputs can be observed to

analyze common-mode offsets and noise.

The primary input channel [INP1 and INN1] provides switches and current sources for a wire break test. A switch

can short both inputs. It can also discharge a filter capacitor after a wire break test, for example.

The signal inputs are diode-clamped to the supply rails. External resistors can be placed in series to the inputs to

provide overvoltage protection. Current into the input pins should be limited to ≤ 10mA.

The output stage offers a fully-differential signal around the output reference pin, VOCM. The VOCM pin is a

high-impedance input and expects an external voltage, typically close to midsupply. The 3V or 5V supply of the

converter or amplifier, following the PGA280 outputs, is normally connected to VSOP and VSON; this

configuration shares a common supply voltage and protects the circuit from overloads. The fully-differential signal

avoids coupling of noise and errors from the supply and ground, and allows large signal swing without the risk of

nonlinearities that arise when driving near the supply rails.

The PGA280 signal path has several test points for critical overload conditions. The input amplifiers detect signal

overvoltage and overload as a result of high gain. The output stage also detects clipping. These events are

filtered with adjustable suppression delays and then stored for readout. A GPIO pin can be dedicated for external

indication either as an interrupt or in a monitor mode.

A serial peripheral interface (SPI) controls the gain setting and switches, as well as the operation modes and the

GPIO port pins. The SPI allows read and write access to the internal registers. These registers contain

conditions, flags, and settings, as described in the SPI and Register Description section. They represent the gain

setting for the input stage from 128V/V to the attenuation of ⅛V/V in binary steps and the output stage gain of

1V/V and 1.375V/V (1⅜). The input MUX and switches and the input buffers are also controlled by registers.

Internal error conditions are stored and may be masked to activate an external pin in the GPIO port.

This GPIO port can be configured individually for either input or output or for a special function. In special

function mode, the port indicates an error condition, generates CS signal, controls an external MUX, and

connects to the buffer control and oscillator.

The port pin can act as a CS for an external SPI device. This mode connects other SPI devices [such as an

analog-to-digital (A/D) converter] to the primary four-wire SPI. This feature is especially desirable when using

galvanically-isolated SPI communication. An optional checksum byte further improves communications integrity.

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Input Switch Network

Figure 44 shows the arrangement of the input switches. They are controlled individually via the digital SPI. The

switches B1b, B2b, A1b, and A2b are controlled automatically with the buffer (BUF) operation.

VSP

100mA

VSON

G1

Source

F1

VSON

C1

B1

B1b

A1b

A1

600W

INP2

INP1

BUF

D12

B2

B2b

A2b

A2

Gain

Network

600W

INN2

INN1

BUF

C2

F2

G2

VSON

100mA

Sink

VSON

Serial Peripheral Interface

and Controls

VSN

DVDD

DGND

Figure 44. Input Switch Diagram

Switches A and B select the signal input. Input 1 (INP1 and INN1) provides two current sources and two switches

that connect to VSON (which is typically the analog ground). This configuration is intended for wire break

diagnosis. D12 can discharge an external capacitor or generate a starting condition.

Switches C1 and C2 are used to measure the input voltage referred to GND (VSON); for example, with A1 and

C2 closed. This scheme measures the voltage signal connected to the input pin (INP1) referred to a common

ground. The BUF output is protected against a short to VSON. See the SPI and Register Description section for

more information about switch control.

Input Amplifier, Gain Network and Buffer

The high-precision input amplifiers present very low dc error and drift as a result of a modern chopper technology

with an embedded synchronous filter that removes virtually all chopping noise. This topology reduces flicker

noise to a minimum and therefore enables the precise measurement of small dc-signals with high resolution,

accuracy, and repeatability. The chopper frequency of 250kHz is derived from an internal 1MHz clock. An

external clock can also be connected, if desired.

The gain network for the binary gain steps connects to the input amplifiers, thus providing the best possible

signal-to-noise ratio (SNR) and dc accuracy up to the highest gains. Gain is controlled by Register 0. This

register can control the gain and address for an external MUX in one byte. Selectable gains (in V/V) are : 128,

64, 32, 16, 8, 4, 2, 1, ½, ¼, and ⅛. The gain is set to 1/8V/V after device reset or power-on.

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Programmable gain amplifiers such as the PGA280 use internal resistors to set the gain. Consequently,

quiescent current is increased by the current that passes through these resistors. The largest amplitude could

increase the supply current by ±0.4mA. In maximum overload, gain of 128V/V and each or the inputs connected

to the opposite supply voltage, a current of approximately 27mA was measured. External resistors in series with

the input pins that are normally present avoid this extreme condition. This current is only limited by the internal

600Ω and the switch-on resistance (see Figure 44).

Current Buffer

Designed for highest accuracy and low noise, both amplifier inputs are protected from dynamic overvoltages

through clamps. The amplifier fast input slew rate (approximately 1V/µs) normally prevents these clamps from

turning on, provided adequate signal filtering is placed before the input. However, the fast channel

switching-transient of a multiplexer or switch is much steeper, and cannot be filtered; this type of transient

generates a dynamic overload. The current buffers (BUF) prevent this dynamic overload condition of the input.

With the buffers not activated, Figure 45 indicates the clamp current flowing as a result of a fast signal change.

The ramp in the signal, measured at the input pins (INP1), is the resulting voltage drop across the 1.5kΩ resistor.

In the example measurement, this resistor is placed between the signal generator and the input pin of the

PGA280.

Signal Input

to INP1

Ch 4, 2V/div

1.5kW Connecting to INP1

Ch 2, 2V/div

Diff Signal Output

Ch 1, 1V/div

1ms/div

Figure 45. Buffer OFF: Input Clamp Current Flowing

Figure 46 shows a typical block diagram for multiplexed data acquisition. The transient from channel 1 to channel

2 , shown as a voltage step, dynamically overloads the amplifier. A current pulse results from the input protection

clamp. Without the activation of the buffers (see BUF, Figure 44), the clamp current charges the filter and the

signal source. Input low-pass filters are often set to settling times in the millisecond range; therefore, discharge

currents from dynamic overload would produce long settling delays.

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Low-Pass

Filters

Ch 1

S1

Ch 2

S2

Ch 3

S3

Instrumentation

Amplifier

Mux

Ch x

Sx

Ideal

Ch 2

Actual

Change of Mux

Output Voltage

Ch 1

Current into

Protection Clamp

Long Settling of

Voltage on Ch 2

Note: Current from the protection clamp into the signal source and filter produces a long settling delay.

Figure 46. Typical Block Diagram for Multiplexed Data Acquisition

Together with the switching command of the multiplexer or internal switching, the current buffers (BUF) can be

activated to prevent such clamp currents. The buffers do not have clamps as long as the signal remains within

the supply boundaries. Figure 47 shows an example of the input signal settling for both conditions: without and

with the buffer activated.

Without the buffer, there is an obvious long settling, depending on signal and filter impedance. With the buffer

activated, only the amplifier has to settle and no distorting current is reflected into the signal source and filter; no

glitch is visible in this plot. The plot shows the resulting settling of the input signal for a positive and a negative

signal step as indicated in Figure 46; also shown are the SPI signal and the BUFA signal.

Inputs to PGA

with Buffer OFF

Inputs to PGA

with Buffer ON

Mux Switching

Buffer Activated

100ms/div

t₁

t₂

Figure 47. Example for Amplifier Settling Without (t₁) and With (t₂) Buffer (BUF) Activated

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The buffers turn off automatically after a preset time (see Register 3, BUFTIM). They are activated from bit 5 ('T')

within the command byte. They can also be triggered by an external pin (BUFTin on GPIO4). The BUFA bit is

active in conjunction with the buffer, indicating that the buffer is busy (see Figure 55).

Error detection circuits observe the signal path for signal overvoltage (IOVerr), amplifier output clipping (IARerr),

and gain overload (GAINerr). The Input Clamp Activation indicator ICAerr indicates that current was conducted

into the dynamic clamp circuit. These indicators help prevent misinterpretation of the analog signal and diagnose

critical input signal conditions, such as those that occur with integrating analog-to-digital converters that may hide

momentary overloads and present inaccurate results.

The buffers (BUF) prevent current flowing from the signal source with a compromise of offset voltage. As soon as

the buffers are turned off, the amplifiers settle back to high precision. For signal measurement without

(multiplexer) switching transients, the buffer is not used.

Input Protection

The input terminals are protected with internal diodes connected to VSP and VSN. If the input signal voltage

exceeds the power-supply voltage (VSP and VSN), the current should be limited to less than 10mA to protect the

internal clamp diodes. This current-limiting can generally be accomplished with a series input resistor.

EMI Susceptibility

Amplifiers vary in susceptibility to electromagnetic interference (EMI), but good layout practices play a critical

role. EMI can generally be identified as a variation in offset voltage shifts. The PGA280 has been specifically

designed to minimize susceptibility to EMI by incorporating an internal low-pass filter. Additional EMI filters may

be required next to the signal inputs of the system, as well as known good practices such as using short traces,

low-pass filters, and damping resistors combined with parallel and shielded signal routing, depending on the end

system requirements.

Output Stage

The output stage power is connected to the low-voltage supply (normally 3V or 5V) that is used by the

subsequent signal path of the system. This design prevents overloading of the low-voltage signal path.

The output signal is fully differential around a common-mode voltage (VOCM). The VOCM input pin is typically

connected to midsupply voltage to offer the widest signal amplitude range. VOCM is a high-impedance input that

requires an external connection to a voltage within the supply boundaries. The usable voltage range for the

VOCM input is specified in the Electrical Characteristics and must be observed.

The output stage can be set to a gain of 1V/V and 1⅜V/V. It is set to 1V/V after device reset or power-on, and is

controlled by the gain multiplication factor.

Both signal outputs, VOP and VON, swing symmetrically around VOCM. The signal is represented as the voltage

between the two outputs and does not require an accurate VOCM. Therefore, the signal output does not include

ground noise or grounding errors. Noise or drift on VOCM is normally rejected by the common-mode rejection

capability of the subsequent signal stage.

The signal that passes through the output stage is internally monitored for two error conditions: clipping of the

signal to the supply rail and overcurrent. In fault conditions, an error flag bit is set (OUTerr).

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Output Filter

The PGA280 uses chopper technology for excellent dc stability over temperature and life of operation. It also

avoids 1/f frequency (flicker) noise, and therefore enables both high resolution and high repeatability for dc

measurements. While the chopper noise components are internally filtered, a minimal residual amount of

high-frequency switching noise appears at the signal outputs. An external, passive, low-pass filter after the output

stage is recommended to remove this switching noise; Figure 48 shows two examples. This filter can also be

used to isolate or decouple the charge switching pulses of an A/D converter input.

R₁

R₃

50W

100W

VOP

VON

VOP

VON

C₁

R₂

R₄

10nF

50W

100W

C₂

10nF

C₃

10nF

Figure 48. Typical Examples of Recommended Output Filters

Single-Ended Output

The output stage of PGA280 is designed for highest precision. The fully-differential output avoids grounding

errors and noise, and delivers twice the signal amplitude compared to single-ended signals. However, if desired,

the output can be taken single-ended from one of the output pins referred to the voltage at the VOCM pin. The

output stage errors now relate to half the signal amplitude and half the signal gain. The unused output is

unconnected, but not disconnected from error detection. The usable voltage range for the VOCM input is

specified in the Electrical Characteristics and must be observed: the output swing (of both outputs) should not

saturate to the supply. Separate specifications for offset voltage and drift indicate higher offset voltage at lower

gains, because some error sources are not cancelled in the output stage connected in single-ended mode. Note

that the gain is one-half of the gain set in reference to the gain table (see Table 2).

Error Detection

The PGA280 is designed for high dc precision and universal use, but it also allows monitoring of signal integrity.

The device contains an input switch network for signal tests and sense points that can indicate critical conditions.

These added features support fully automated system setup and diagnostic capability. Out-of linear range

conditions are detected and stored in the Error Status Register (Register 4) until reset. The input switches shown

in Figure 44 can be used to short the input to GND, disconnect the signal, insert a 100µA test current, discharge

external capacitance, and switch to a ground (VSON)-referenced signal measurement to observe the signal at

the pin (versus the differential measurement). Figure 49 illustrates the diagnostic points available for error

detection in the device architecture.

All switches are controlled through the SPI. The error signals can be combined using a logic OR function to an

output pin and eventually be used as an error interrupt signal. Errors are normally latched, unless the LTD bit

(latch disable) is set.

The error sensors are filtered with a suppression delay (Register 11). These error signals are normally

suppressed during the buffer (BUFA) active time.

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VSOP

VSP

VSN

VSP

VSN

VSOP

VSON

Error:

Input over-voltage

Error:

Input amp saturation

Error:

Output amplifier

Error:

Clamp condition

Clamp

A1

MUX

Switch Network,

Current Source

and Sink,

Gain

A3

and Buffer

Clamp

A2

Error:

Gain network

overload

Digital I/O

VSN

VSON

Note: The signal path is observed for possible limitations; flags are stored and indicated in Register 4.

Figure 49. Diagnostic Points for Error Detection

ERROR INDICATORS

Input Clamp Conduction (ICAerr)

The input clamp protects the precision input amplifier from large voltages between the inputs that occur from a

fast signal slew rate in the input. This clamp circuit pulls current from the input pins while active. Current flowing

through the clamp can influence the signal source and cause long settling delays on passive signal filters. The

current is limited by internal resistors of approximately 2.4kΩ. Dynamic overload can result from the difference

signal as well as the common-mode signal.

The input clamp turns on when the input signal slew rate is faster than the amplifier slew rate (see the Electrical

Characteristics specification) and larger than ±1V. Appropriate input filtering avoids the activation. However,

transients from MUX switching, internal switches, and gain switching action cannot be filtered; therefore, to avoid

these transients, it is recommended that the current buffer (BUF) be activated. The buffer isolates the signal input

from the clamp, and therefore avoids the current pulse (see Figure 44).

Input Overvoltage (IOVerr)

The input amplifier can only operate at high performance within a certain input voltage range to the supply rail.

The IOVerr flag indicates a loss of performance because of the input voltage or the amplifier output approaching

the rail.

Gain Network Overload (GAINerr)

The gain setting network is protected against overcurrent conditions that arise because of an improper gain

setting. The current into the resistors is proportional to the voltage between both inputs and the internal resistor;

a low resistor value results in high gains. This error flag indicates such an overload condition that is the result of

an improper gain setting.

Output Amplifier (OUTerr)

The output stage is monitored for signal clipping to the supply rail and for overcurrent conditions.

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CheckSum Error (CRCerr)

SPI communication can include a checksum byte for increased data integrity, when enabled. It is especially

useful for an isolated SPI. This error detection is only active with the checksum activated. See the Checksum

section for details.

POWER SUPPLY

The PGA280 can connect to three supply voltages: the high-voltage analog supply, the low-voltage output

amplifier supply, and the digital I/O supply. This architecture allows an optimal interface (level-shift) to the

different supply domains.

The high-voltage analog supply, VSP and VSN, powers the high-voltage input section. The substrate of the IC is

connected to VSN; therefore, it must be connected to the most negative potential.

The low-voltage analog output supply, VSOP and VSON, can operate within the high-voltage supply boundaries

with two minimal limitations:

1. The usable range for VSON is from a minimum 5V below VSP to as low as VSN. This 5V provides the

headroom for the output supply voltage of +2.7V to +5V. Even with less than 5V supply, this voltage

difference is required for proper operation.

2. The common-mode control input, VOCM, requires a voltage at least 2V from VSP, in order to support

internal rail-to-rail performance.

These limits may only come into consideration when using a minimum supply or an extremely asymmetrical

high-voltage supply. In most practical cases, VSON is connected to the ground of the system 3V or 5V supply.

VSOP can be turned on first or can be higher than VSP without harm, but operation fails if VSP and VSN are not

present.

Observe the maximum voltage applied between VSOP and VSON, because there is no internal protection. This

consideration is the same as with other standard operational amplifier devices.

The digital supply, DGND and DVDD, can also be set within the boundaries of VSP and VSN. Only the positive

supply, DVDD, cannot be closer than 1V below VSP. It can be turned on without the analog supply being present

and is operational, but limited to digital functions in this case. The maximum supply voltage must be observed

because there is no internal protection. VSOP and VSON can be connected with DVDD and DGND, if desired.

Current consumption of the digital supply is very low under static conditions, but increases with communications

activity. Assuming no external load except the 20pF load to SDO, with an SCLK = 10MHz and a 3V supply, the

current momentarily increases by approximately 0.6mA when reading a register (for example, reading Register

14). With a 5V digital supply, the increase is in the range of 0.8mA. This additional current is only required during

communication; a larger bypass capacitor can supply this current. Driving current into SDO would further

increase the current demand.

VSN is connected to the substrate; therefore, the voltage at VSON or DGND must not turn on the substrate

diode to VSN. Use external Schottky diodes from VSON to VSN and from DGND to VSN (refer to Figure 50) to

prevent such a condition.

The PGA280 uses an internal chopper technology and therefore works best with good supply decoupling. Series

resistors in the supply are recommended to build an RC low-pass filter. With the small supply current, these

series resistors can be in the range of 15Ω to 22Ω. The RC filter also prevents a very fast rise time of the supply

voltage, thus avoiding parasitic currents in the IC. Connecting supply wires into an already-turned on supply (very

fast rise time) without such a filter can damage the IC as a result of voltage overshoot and parasitic charge

currents. Figure 50 shows an example of a supply connection using RC bypass filters. DVDD may not need

decoupling, but if the digital supply is noisy, a filter is recommended at C₄and R₄.

NOTE

Rise and fall times for the high-voltage supplies must be slower than 1V/μs.

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+15V

-15V

+5V

+3V

R₁

22W

R₂

R₃

R₄

22W

10W

C₁

C₂

C₃

C₄

SD1

470nF

100nF

SD2

VSP

VSN

VSON

VSOP

DGND

DVDD

PGA280

Supply Connections

Note: In this example, the Schottky diodes prevent substrate reversing. The supply voltages shown are only example

values.

Figure 50. Supply Connection Example Using RC Bypass Filters for Good Decoupling

External Clock Synchronization

The PGA280 uses an internal oscillator of 1MHz, nominally. This clock can be brought out to pin GPIO6 if

configured by the internal register setting to allow synchronization of external systems to this clock. If the

PGA280 must be controlled by an external clock, GPIO06 can be configured as an oscillator input, thus

overriding the internal oscillator. The frequency range must be within the specified range shown in the Electrical

Characteristics in order to maintain stable device performance. The clock pulse width is not critical, because it is

internally divided down; however, less than 30% deviation is recommended. The GPIO6 input assumes a

standard logic signal. Prevent overshoot at this pin, and provide approximately equal rise and fall time for the

lowest influence on offset voltage as a result of coupled noise.

Expect a small amount of additional noise during the transition from internal to external clock, or vice-versa, for

approximately eight clock periods because of phase mismatch.

Quiescent Current

The PGA280 uses internal resistor networks and switches to set the signal gain. Consequently, the current

through the resistor network may vary with the gain and signal amplitude. Under normal operation, the

gain-related current is low (less than 400μA). However, in signal overload conditions while a high gain is

selected, this amount of current can increase.

Settling Time

The PGA280 provides very low drift and low noise, and therefore allows repeatable settling to a precise value

with a negligible tail. Signal-related load and power dissipation variables have minimal effect on the device

accuracy.

Overload Recovery

Overload conditions can vary widely, and there are multiple points in an instrumentation amplifier that can be

overloaded. During input overload, the PGA280 folds the output signal partially back as a result of the differential

signal structure and summing, but the error flags indicate such fault conditions. The amplifier recovers safely

after removing the overload condition, as long as it is within the specified operating range as shown in Figure 51.

Avoid dynamic overload by using adequate signal filtering that reduces the input slew rate to the slew rate of the

amplifier. Fast signal jumps produced from multiplexed signal sources or gain changes cannot normally be

filtered, but the current buffer (BUF) stage can be activated to prevent current flowing through the input into the

protection clamp in such situations.

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Overload Error Flag

(IOVerr), Ch 4

2V/div

Output Signal

Ch 3, 2V/div

VSN

Ch 2, 5V/div

INN1 Clipped to

VSN, Ch 1, 5V/div

25ms/div

Figure 51. Input Clipping: Negative Side

SPI and Register Description

The serial peripheral interface uses four wires: CS (input), clock (SCLK, input), data in (SDI, or slave data input),

and data out (SDO, or slave data output) and operates as a slave.

CS is active low; data are sampled with the negative clock edge. It is insensitive to the starting condition of SCLK

polarity (SPOL = 1 or 0). See Figure 52 and Figure 53.

The SPI communicates to the internal registers, starting with a byte for command and address. It is followed by a

single data byte (exception: 11tx 0ccc requires no data byte). The communication can include a checksum byte.

When enabled, this byte follows the last valid byte. Either power on reset or software reset (SftwrRst) disables

the checksum mode. Writing to Register 11 enables or disables checksum mode.

On a read command, the device responds with the data byte and the checksum byte. If the checksum is not

desired, setting CS to high terminates the transmission.

Multiple commands can be chained by holding CS low and sending the additional commands after the checksum

byte (if checksum is disabled, send a dummy byte). In this mode, read and write instructions can be mixed.

This interface allows clock rates up to 10MHz. Such high clock rates require careful board layout, short wire

lengths, and low parasitic capacitance and inductance. Observe delays and distortion generated from isolation

couplers. External drivers may be required to drive long and terminated cables.

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COMMAND STRUCTURE AND REGISTER OVERVIEW

Bit 7 is the most significant bit (MSB); bit 0 is the least significant bit (LSB). Binary numbers are denoted with 'b'.

'aaaa' is used to denote the encoded register pointer, 0000b to 1111b. 'T' denotes the buffer trigger bit. Writing to

unassigned bits is ignored, but it is recommend to write a '0' for all unassigned bits. PGA280 registers,

addresses, and functional information are summarized in the Register Map (Table 1).

Command Byte

01T0 aaaa dddd dddd: Write

Write 'dddd dddd' to internal PGA280 register at address aaaa

1000 aaaa 0000 0000: Read

Read from specified internal PGA280 register at address aaaa [no BUFT on read]. The number of trailing

zeros provides the clock for reading data. 16 SCLK pulses are required when reading the data byte plus

checksum.

00T0 aaaa:

Factory-reserved commands.

11T0 0ccc: Direct CS Command

Controls CS to pin (all pins are CS-capable, but not simultaneously; only one at a time) for ccc = 0 to 6,

corresponding to GPIO0 to GPIO6, if CS mode is activated.

Within the command byte, T = 1 triggers the current buffer (BUF). Each command is terminated with setting CS

to high; commands can be chained within a period of CS active low, but require a checksum byte, or a dummy

byte when checksum mode is disabled.

NOTE

BUF cannot be triggered during a read command.

Here are several examples (discrete commands):

Read Register 3:

Send 0x8300; response: 0xzz19 (this value is the initial setting of BUFTIM).

The first byte zz contains the line state (3-state) of SDO. The second byte is data.

NOTE

The PGA280 sends the CHKsum, if clocks are available while CS: Send 0x830000.

Response: 0xzz1937

Write Register 0:

Send 0x4018; set gain to 1V/V.

Write Register 4:

Send 0x44FF; reset all error flags.

Read Register 4:

Send 0x8400; response: 0xzz00 (no error flags set).

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Extended CS

The PGA280 can generate an extended chip select (ECS) for other devices that are connected to the same SPI

wires: SDO, SDI, and SCLK. This ECS signal redirects the SPI communication to the connected device, while

the PGA280 ignores data and SCLK. The CS signal to the PGA280 must stay low during such communication;

as soon as CS returns high, SPI communication is terminated. See the GPIO Operation Mode section for details.

Table 1. REGISTER MAP⁽¹⁾

REGISTER

(Decimal,

[Hex])

aaaa

(Binary)

RESET

VALUES

(2)

(3)

R/W

B7

B6

B5

B4

B3

B2

B1

B0

DESCRIPTION

0

1

2

3

4

5

0000

0001

0010

0011

0100

0101

W/R

G4

G3

G2

G1

G0

MUX2

MUX1

MUX0

Gain and optional MUX register

0000 0000b

0001 1001b

0000 0000b

SftwrRst

Note2x

W

Write-only register, soft reset, write 1

SPI-MODE selection to GPIO-pin

Set BUF time-out

W/R

CP6

CP5

BUFTIM5

BUFA

CP4

CP3

BUFTIM3

EF

CP2

CP1

CP0

BUFTIM

4

BUFTIM

2

BUFTIM

0

BUFTIM1

GAINerr

GPIO1

CHKerr

IARerr

GPIO6

SW-A1

ICAerr

GPIO4

SW-B1

OUTerr

GPIO2

IOVerr

GPIO0

Error Register; reset error bit: write 1

GPIO Register Data force out or

sense

GPIO5

SW-A2

GPIO3

6

7

8

9

0110

0111

1000

1001

W/R

SW-B2

SW-F1

DIR3

SW-C1

SW-F2

DIR2

SW-C2

SW-G1

DIR1

SW-D12

SW-G2

DIR0

Input switch control

0110 0000b

0000 0000b

DIR6

DIR5

DIR4

Configure pin to out = 1 or in = 0

Extended CS mode (1 = enable)

ECS6

ECS5

ECS4

ECS3

ECS2

ECS1

ECS0

MUX-D

dis

IARerr

dis

BUFAPol

at pin

ICAerr

dis

ED BUFA

suppress

OUTerr

dis

GAINerr

dis

IOVerr

dis

10 [A]

1010

1011

W/R

Various configuration settings

0000 0000b

FLGTIM

2

FLGTIM

0

CHKsu

mE

11 [B]

12 [C]

W/R

LTD

FLGTIM3

FLGTIM1

Reserved

0001 0000b

0000 0000b

1100

OSCout SYNCin

GPIO6

BUFAout

GPIO5

BUFTin

GPIO4

EFout

MUX2

MUX1

MUX0

Special function register

GPIO3

GPIO2

GPIO1

GPIO0

Register bit reference to GPIO pin⁽⁴⁾

(1) Blank register bits are ignored and undefined.

(2) Registers 13 to 15 are for test purposes; read-only.

(3) Power-on reset values are SftwrRst values.

(4) Details for GPIO pin assignments are shown in Figure 54 .

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SPI Timing Diagrams (Read and Write)

(SCLK—Data—CS)

SDO

Z

SDI

C7

C6

C5

C4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SCLK

CS

GPX

Sampled Here

Figure 52. Write (to Device) Timing (GPX: Command Decoding); No Checksum Enabled.

With Checksum, Command Decoding Occurs After 24th Falling Edge of SCLK

SDO

SDI

Z

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

Z

CB7

B6

B5

B4

A3

A2

A1

A0

X

SCLK

CS

GPX

Sampled Here

Figure 53. Read (From Register) Timing (GPX: Command Decoding); No Checksum Enabled.

Falling Edge of SCLK Controls Logic

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GPIO Pin Reference

As shown in Figure 54, the PGA280 has seven multi-function pins labeled GPIO0 through GPIO6. These pins

can function as general purpose input-output (GPIO) pins either to read a digital input or to output a digital signal

as an interrupt or control. GPIO functions are controlled through Register 5 and Register 8.

These pins can also be programmed to have additional special functions for the PGA280. Each of these seven

pins can be used as an output for the extended chip select function (ECS), using the PGA280 to redirect the SPI

communications to other connected devices. CS Configuration Mode is enabled through Register 9. Additionally,

Register 2 controls the clock polarity (CP) of each ECS. For each bit set to '1', a positive edge of SCLK follows

CS (CP = 0); for each bit set to '0', a negative edge of SCLK follows CS (CP = 1).

Together with the GPIO and ECS functions, the seven pins can perform more specialized input and output tasks

as controlled by Register 12, the Special Functions Register.

GPIO0, GPIO1, and GPIO2 can be used to control an external multiplexer. If the MUX function is enabled in the

first three bits of Register 12, the output value on the MUX pins is controlled through Register 0. This

configuration allows for simultaneous control of the PGA280 gain and external multiplexer settings by writing to a

single register.

GPIO3 can be used to output an error flag. As with bit 3 of Register 4, this option would be the logical OR of the

error bits in Register 10 (IARerr, ICAerr, OUTerr, GAINerr, and IOVerr).

GPIO4 can be used as an input to trigger the current buffer. The low-to-high edge of a pulse starts the buffer with

a delay of three to four clock cycles. If held high, the buffer [BUFA] remains active. It is extended by a minimum

of three to four clock cycles in addition to the time set with FLAGTIM.

GPIO5 can be configured as an output to indicate a buffer active condition. The polarity is controlled by BUFApol

of bit 5 in Register 10.

GPIO6 can be configured as either an output or an input with the Special Functions Register. With Bit 7,

OSCOUT connects the internal oscillator to GPIO6. With Bit 6, SYNCIN allows an external oscillator to provide

the master clock to the PGA280.

To use any of these functions, Register 8 must first be set to '0' for input or to '1' for an output (for GPIO, ECS, or

special function).

Once set, any 1s in Register 9 supersede the GPIO function for the related pin, allowing for CS configuration.

Likewise, any 1s in Register 12 supersede the GPIO function and CS configuration, allowing for any of the

pin-specific special functions to operate.

GPO/ECS6/OSCout

GPIO6

GPI/SYNCin

GPO/ECS5/BUFout

GPIO5

GPI

GPO/ECS4

GPIO4

GPI/BUFTin

GPO/ECS3/EFout

GPIO3

GPI

GPO/ECS2/MUX2

GPIO2

GPI

GPO/ECS1/MUX1

GPIO1

GPI

GPO/ECS0/MUX0

GPIO0

GPI

Figure 54. Special Function to Pin Assignment Reference

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REGISTER INFORMATION

REGISTER DETAILS

Register 0: Gain and External MUX Address (Read = 0x8000; Write with BUF Off = 0x40, Write with BUF

On = 0x60)

Bit #

D7

G4

0

D6

G3

0

D5

G2

0

D4

G1

0

D3

G0

0

D2

MUX2

0

D1

MUX1

0

D0

MUX0

0

Bit Name

POR Value

Bit Descriptions:

G4: Output stage gain setting. This setting is independent of the gain selected in the input stage and acts as

a multiplication factor to the input gain.

0 = 1V/V output gain (power-on default)

1 = 1.375V/V output gain (= 1⅜V/V)

G[3:0]: Input stage gain setting. Refer to Table 2.

MUX[2:0]: These ports can be used to control an external multiplexer.

Table 2. INPUT STAGE GAIN SETTINGS

G3

0

1

G2

0

1

0

1

G1

0

1

0

1

0

1

0

1

G0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Gain

1/8

1/4

½

1

2

4

8

16

32

64

128

Reserved

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Register 1: Software Reset Register (Write = 0x4101; Write with Checksum = 0x4101DD)

Bit #

D7

—

0

D6

—

0

D5

—

0

D4

—

0

D3

—

0

D2

—

0

D1

—

0

D0

SftwrRst

0

Bit Name

POR Value

Bit Descriptions:

SftwrRst: Software Reset.

Setting this bit to '1' generates a system reset that has the same effect as a power-on reset. All registers are

reset to the respective default values; this bit self-clears.

Register 2: SPI: MODE Selection to GPIO-Pin (Read = 0x8200, Write = 0x012)

Bit #

D7

—

0

D6

CP6

0

D5

CP5

0

D4

CP4

0

D3

CP3

0

D2

CP2

0

D1

CP1

0

D0

CP0

0

Bit Name

POR Value

Bit Descriptions:

CP[6:0] SPI mode1 or mode2 can be configured for each individual ECS (extended CS) output if activated in

Register 9. See CS Mode in GPIO Operation Mode for details. CP6 controls ECS6, for example. For SPI

mode1, set the respective bit to '1': a positive edge of SCLK follows CS (Clock Polarity, CP = 0). For SPI

mode2, set the respective bit to '0': a negative edge of SCLK follows CS (CP = 1). See also Figure 56.

Register 3: BUF Timeout Register (Read = 0x8300, Write = 0x43)

Bit #

D7

—

0

D6

—

0

D5

BUFTIM5

0

D4

BUFTIM4

1

D3

BUFTIM3

1

D2

BUFTIM2

0

D1

BUFTIM1

0

D0

BUFTIM0

1

Bit Name

POR Value

Bit Descriptions:

BUFTIM[5:0] Defines BUF timeout length. The LSB equivalent is 4*t CLK (nominal value is 4μs with a 1MHz

clock). Setting this register to 0x00 disables the BUF. The minimum timeout length that can be set is

approximately 6μs. The default/POR setting sets BUFA time on to 100μs. The BUFA bit of the Error Register

[D5] indicates the buffer active status. See Figure 55.

Register 4: Error Register (Read = 0x8400, Write = 0x44)

Bit #

D7

CHKerr

0

D6

IARerr

0

D5

BUFA

0

D4

ICAerr

0

D3

EF

0

D2

OUTerr

0

D1

GAINerr

0

D0

IOVerr

0

Bit Name

POR Value

The Error Register flags activate whenever an error condition is detected. These flags are cleared when a '1' is

written to the error bit.

Bit Descriptions:

CHKerr: Checksum error in SPI. This bit is only active if checksum is enabled. This bit is set to '1' when the

checksum byte is incorrect.

IARerr: Input Amplifier Saturation

BUFA: Buffer Active

ICAerr: Input Clamp Active

EF: Error Flag. Logic OR combination of error bits of Register 10. This bit can be connected to GPIO3 pin if it

is configured for output (Register 8) and as a special function (Register 12).

OUTerr: Output Stage Error (allow approximately 6µs activation delay).

GAINerr: Gain Network Overload

IOerr: Input Overvoltage

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Register 5: GPIO Register (Read = 0x8500, Write = 0x45)

Bit #

D7

—

0

D6

GPIO6

0

D5

GPIO5

0

D4

GPIO4

0

D3

GPIO3

0

D2

GPIO2

0

D1

GPIO1

0

D0

GPIO0

0

Bit Name

POR Value

Bit Descriptions:

GPIO[6:0]: The GPIO bits correspond to GPIO6 through GPIO0, respectively. The function of each bit

depends on whether the GPIO pin is configured as an input pin or an output pin, which is determined by the

setting in Register 8. When the GPIO pin is configured as an input, reading this register samples the GPIO

pin. When the GPIO pin is configured as an output, reading from this register reads back the forced data.

Register 6: Input Switch Control Register 1 (Read = 0x8600, Write = 0x46)

Bit #

D7

—

0

D6

SW-A1

1

D5

SW-A2

1

D4

SW-B1

0

D3

SW-B2

0

D2

SW-C1

0

D1

SW-C2

0

D0

SW-D12

0

Bit Name

POR Value

Bit Descriptions:

Switch control; see Figure 44 for switch designation (switch closed = 1).

Example: Select INP2 and INN2: 0x18 // opens A1 and A2, and closes B1 and B2.

Register 7: Input Switch Control Register 2 (Read = 0x8700, Write = 0x47)

Bit #

D7

—

0

D6

—

0

D5

—

0

D4

—

0

D3

SW-F1

0

D2

SW-F2

0

D1

SW-G1

0

D0

SW-G2

0

Bit Name

POR Value

Bit Descriptions:

Switch control; see Figure 44 for switch designation.

Register 8: GPIO Configuration Register (Read = 0x8800, Write = 0x48)

Bit #

D7

—

0

D6

DIR6

0

D5

DIR5

0

D4

DIR4

0

D3

DIR3

0

D2

DIR2

0

D1

DIR1

0

D0

DIR0

0

Bit Name

POR Value

Bit Descriptions:

DIR[6:0]: GPIO configuration for input or output; 0 for input; 1 for output. Power-on default is all inputs

(requires external termination or set to output ).

Register 9: CS Configuration Mode Register (Read = 0x8900, Write = 0x49)

Bit #

D7

—

0

D6

ECS6

0

D5

ECS5

0

D4

ECS4

0

D3

ECS3

0

D2

ECS2

0

D1

ECS1

0

D0

ECS0

0

Bit Name

POR Value

Bit Descriptions:

ECS[6:0]: Configure CS function to respective pins. See CS Mode, in the GPIO Operation Mode section (a

single byte command applies).

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Register 10: Configuration Register 1 (Read = 0x8A00, Write = 0x4A)

Bit #

D7

MUX-D

0

D6

IARerr

0

D5

BUFA Pol

0

D4

ICAerr

0

D3

ED BUFA

0

D2

OUTerr

0

D1

GAINerr

0

D0

IOVerr

0

Bit Name

POR Value

Bit Descriptions:

MUX-D: Set this bit to '1' to disable MUX control from Register 0; set to '0' after reset.

BUFA Pol: Controls BUF active indication polarity. Set to '0' for high = active; set to '1' for low = active.

ED BUFA Suppress: Error detection is normally disabled during BUFA active. Errors are not suppressed if

ED BUFA = 1.

Error flags are logic OR-combined and connected to the ‘EFout’ in Register 12 as well as connected to the

GPIO3 output pin if configured. The EFout signal is active high. Assigned errors can be disabled individually

using this OR function, with the exception of ‘CHKerr’, by writing a '1' to the error bit position. [IARerr; ICAerr;

OUTerr; GAINerr; IOVerr]

Register 11: Configuration Register 2 (Read = 0x8B00, Write = 0x4B)

Bit #

D7

LTD

0

D6

—

0

D5

FLGTIM3

0

D4

FLGTIM2

1

D3

FLGTIM1

0

D2

FLGTIM0

0

D1

Reserved

0

D0

CHKsumE

0

Bit Name

POR Value

Bit Descriptions:

LTD: Individual error signals are not latched if this bit is set to '1'. With EFout activated on GPIO3, the error

condition can be observed in real time, but error suppression time is applied. Clear errors in Register 4 after

writing '1' to this bit.

FLAGTIM0 to 3: Choose the number of clock cycles (nominally 1MHz) according to Table 3 for suppression

of the error flags in Register 4. The timeout starts after the end of BUFA. Alternatively, it can start with the

event if the buffer is not active or Register 10, bit 3 is set high. Allow delayed activation for the individual

error sources in the microsecond range.

Table 3. Error Flag Suppression Time

(1)

FLGTIM [3:0]

0000

CLOCK CYCLES

0

1

0001

0010

2

0011

3

0100

4

0101

5

0110

6

0111

7

1000

8

1001

12

16

24

32

48

64

127

1010

1011

1100

1101

1110

1111

(1) Clock cycles refer to internal clock or SYNCin; nominally 1MHz.

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35

Product Folder Link(s): PGA280

PGA280

SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com

CHKsum is enabled by writing a '1' to this bit. A correct checksum is always required for enabling. Once set, all

communication to the device requires a valid checksum, until '0' is written to this bit. Alternatively, a software

reset [0x4101DD] or power-on reset can be performed to reset this function.

Register 12: Special Functions Register (Read = 0x8C00, Write = 0x4C)

Bit #

D7

OSCout

0

D6

SYNCin

0

D5

BUFAout

0

D4

BUFTin

0

D3

EFout

0

D2

MUX2

0

D1

MUX1

0

D0

MUX0

0

Bit Name

POR Value

Bit Descriptions:

Special function pin designation: Set to '1' for activation.

OSCout: Internal oscillator connected to pin GPIO6 for output (GPIO6 configured as an output).

SYNCin: External connection for external oscillator input to pin GPIO6 (GPIO6 configured as an input).

BUFAout: Pin GPIO5 indicates a buffer active condition (if configured as an output). The BUFA output signal

is active high by default, but can be inverted to active low by BUFA Pol.

BUFTin: The current buffer can be triggered externally by pin GPIO4, if configured as an input. The

low-to-high edge of a pulse starts the buffer with a delay of three to four clock cycles. If held high, the buffer

[BUFA] remains active. It is extended by a minimum of three to four clock cycles plus the time set with

FLAGTIM.

EFout: A logic OR combination of error bits; see Register 10. This flag can control GPIO3 if this pin is

configured as an output and EFout = 1.

MUX2 to MUX0: If the GPIO pins are configured as outputs and these bits are set to '1', the GPIO pins are

controlled from Register 0 (if MUX-D = 0).

GPIO Configuration

Register priority: If GPIO pins are used, follow this procedure:

First, configure individual I/O bits as either inputs or outputs (Register 8); '0' = input, '1' = output. Bits B0 to

B6 are connected to GPIO0 to GPIO6, respectively.

Then, configure individual bits to the desired function. When configuring for output, set the Data Register

(Register 5) first to avoid glitches.

To configure the GPIO pins for the CS function (see Register 9):

•

Configure ECS ('0' = disable, '1' = enable). If set to '1' and the I/O configuration is set to output as well, this

pin becomes ECS. Details of this configuration are described in GPIO Operation Mode, CS Mode.

Configure for clock polarity (CP), relative to ECS in Register 2; see Register 9. Set this bit to '0': a negative

edge of SCLK follows ECS (CP = 1). Set this bit to '1': a positive edge of SCLK follows ECS (CP = 0).

Configure for special function (Register 12): Special function signals can be assigned to the GPIO pins in this

manner: 0 = disable, 1 = enable. Pins xxout must be configured as outputs, and xxin must be configured as

inputs in Register 8.

•

GPIO data to force (Register 5) GPIO data (1 = low, 0 = high). Forcing a bit, which is assigned to a special

function, may be stored until GPIO is enabled.

NOTE

Data may be stored in internal registers and therefore may show on a given GPIO pin

after the configuration is changed.

36

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Product Folder Link(s): PGA280

PGA280

www.ti.com................................................................................................................................................ SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009

Buffer Timing

The buffer is used to isolate fast transients from the overload protection of the high-precision amplifier. It avoids

current into the overload clamp. Fast transients result from the switching transient of a signal multiplexer or a

gain change; these transients cannot be filtered in the signal path.

The buffer can be turned on by software using the 'T' bit in the SPI command or by activating a GPIO pin. The

on-time of the buffer is set in Register 3 (BUFTIM).

If controlled by software command, the buffer turns active (indicated by BUFA shown in Figure 55) with the last

falling edge of SCLK.

Controlling an external MUX through Register 0 activates the GPIO pins after the rising edge of CS, providing an

extra delay.

Alternatively, the buffer can be controlled by GPIO4, after configuration (Register 8, bit 4 = 0, and 0x4C10). A

rising edge triggers the buffer with a delay of three to four clock cycles. If held high, the buffer [BUFA] remains

active. It is extended by a minimum of three to four clock cycles plus FLAGTIM.

The buffer active condition can be observed at GPIO5, after configuration for output and special function

(0x4820, 0x4C20). The time reference is the end of CS. The buffer is turned on with the 16th falling edge of the

SCLK and writing to Register 0 (0x6018). BUFA stays high for 6μs (BUFTIM0) after CS.

SDI

BUFA

SCLK

CS

2.5ms/div

Figure 55. BUFA Timing

GPIO Operation Mode

The six GPIO port pins can be configured individually in several modes: as inputs or outputs; a special CS mode;

and a connection to the PGA280 internal special function register that contains control signals or indications. See

Table 1 for details. The GPIO can be accessed through SPI as soon as supply voltage is connected to DVDD

and DGND.

Input: Standard CMOS high-impedance input, no internal termination. Terminate externally if not used or set to

output. Note: The GPIOs are all set as inputs after a device reset.

Output: Push-pull output. Output current is derived from DVDD and from DGND. Avoid I/O activity and high

current during high-precision measurements to avoid coupled noise.

Special Function I/O: The configuration allows connecting a designated pin to the special function register

(Register 12): OSCout, SYNCin, BUFAout, BUFTin, EFout, MUX2, MUX1, and MUX0. The pin must be

configured as an input or output according to the pin function.

Example (CHKsum not enabled):

0x480B GPIO0, GPIO1. and GPIO3 set to output

0x4C0B GPIO0 and GPIO1 connected to MUX0 and MUX1, EFout connected to GPIO3. MUX0 and MUX1

are controlled from Register 0.

Submit Documentation Feedback

37

Product Folder Link(s): PGA280

PGA280

SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com

CS Mode

A special CS mode for the GPIO extends the device communications to other external SPI devices, such as data

converters or shift registers. This CS function is intended for SPI communication using four isolation couplers. To

use this mode, follow this procedure:

Configure the desired GPIO pins as outputs in Register 8, then configure the respective ECS (extended CS)

bits in Register 9.

Register 2 allows control of the clock mode by CPn (n for the individual ECS pins). CP = 1 asserts ECS after the

last negative SCLK edge of the command; CP = 0 asserts ECS after the positive SCLK, as Figure 56 shows.

Use the CS command 1100 0cccb [ccc = CS coded for 0 to 7] to activate ECS on a single GPIO pin.

Example for ECS on pin GPIO1 (CHKsum disabled):

0x4802 GPIO1 configured output (Note: GPIO may output a previously stored state; default is all zeroes)

0x4902 Assign CS (ECS) mode to GPIO1

0xC1 Single byte command to activate CS on GPIO1

CS

CS to PGA280

SCLK

CPOL = 1

SDI

SDO

0xC1

Data to external device

PGA280 3-State

GPIO

(1)

ECS

(1) CPn = 0; the red edge applies if CPn = 1.

Figure 56. Timing for GPIO Pin Acting as CS (ECS) to External Device

This CS pin (ECS) stays low as long as CS to the PGA280 is held low. The PGA280 SDO is turned to a

high-impedance output (and requires external termination). The PGA280 ignores both clock and data signals

during this time. Therefore, data can be read and written to another device selected by the ECS port.

Communication is terminated by setting CS (to the PGA280) to high; this toggle also sets the port ECS to high

and terminates the I/O transfer with the other device.

Figure 56 shows the timing for the GPIO-generated ECS pulse in clock mode SPOL = 1 (SCLK is high after CS

asserts low). Register 2 allows activating SPOL = 0 by writing a '1' to the CP bit, according to SPI mode1. The

initial setting is SPOL = 1.

Mode1; set bit to '1': a positive edge of SCLK follows after ECS asserts low (CP = 0). See the red edge of the

GPIO trace in Figure 56.

Mode2; set bit to '0': a negative edge of SCLK follows after ECS asserts high (CP = 1). See the black edge of the

GPIO trace in Figure 56.

The negative edge of SCLK senses data. The positive edge of SCLK sets data on the data out line (if

applicable).

For SPI modes 0 or 3, SCLK must be inverted to indirectly sense data with the positive edge of SCLK. Figure 57

shows an example of connecting additional SPI devices, addressed by the ECS. The OR connection for SDO

can be a wired-OR if all devices provide a 3-state output option with the respective device CS (ECS) set high.

The SPI interface allows clock rates higher than 10MHz. Clock rates less than10MHz are recommended when

using the ECS mode for less critical printed circuit board (PCB) layout and timing. Observe delays and distortion

generated from isolation couplers. External drivers may be required to drive long and terminated cables.

38

Submit Documentation Feedback

Product Folder Link(s): PGA280

PGA280

www.ti.com................................................................................................................................................ SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009

With only four isolation couplers (digital galvanic isolation) connected in the SPI wires, the SPI can provide

galvanic isolation for input and output channels. Figure 57 shows a block diagram of how to connect SPI devices

selected by the ECS (extended CS) signal.

Isolation couples or long SPI cables in harsh industrial environment are sensitive to impairments. For improved

communication integrity, the communication can be extended with a checksum byte.

Figure 57 shows an example of the GPIO pins used for both the extended chip select and special functions.

The chip select (CS) is connected to the PGA280 alone. The serial data input (SDI) and the serial clock (SCLK)

are shared connections, and are connected to all devices [PGA280, A/D converter, and the shift register or

digital-to-analog converter (DAC)]. The serial data output comes from each of the devices and are OR-connected

or sent to an OR gate, to be received by the master. An OR gate is only required if the connected devices do not

support 3-state operation. The PGA280 provides a 3-state output if not active. Pullup resistors may be required.

As mentioned previously, the GPIO pins are used to control an external multiplexer. In Figure 57, the three pins

from GPIO0, GPIO1, and GPIO2 are used as a MUX address. Two other GPIO pins are used as ECS to enable

communications with other slave devices.

CS

SCLK

MOSI

MISO

CS

Addressing

MUX0

SCLK

SDI

SPI

Master

External

MUX

PGA280

MUX1

GPIO

SDO

MUX2

Extended Chip-Select

CS

External MUX Control

SCLK

SDI

A/D

Converter

OR

SDO

CS

SCLK

SDI

Shift Register

or DAC

SDO

Figure 57. Example for Connecting Two Additional SPI Devices Selected by ECS

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39

Product Folder Link(s): PGA280

PGA280

SBOS487A –JUNE 2009–REVISED SEPTEMBER 2009................................................................................................................................................ www.ti.com

Checksum

SPI communication can be secured by adding a checksum byte to the write and read data. If this mode is

activated by setting CHKsumE (bit 0 in Register 11), the PGA280 expects a valid checksum; otherwise, the

device ignores the received data and sets CHKerr in Register 4. This event may require a Register 4 read after

each write completes. The PGA280 always responds to a read with checksum if sufficient SCLK pulses (16) are

provided after the command byte.

A straight checksum (ignore carry) with a starting value of 0x9B, an 8-bit byte, is used. Polynomial value: 1001

1010b = 0x9B (b denotes binary, 0x denotes hex coding)

Write to device: Command byte + Data byte + CHKsum byte

CHKsum = Polynomial value + Command byte + Data byte*;

space

Read command to device = Command byte + CHKsum byte

Response: Data byte + CHKsum byte

CHKsum = Polynomial value + Command byte + Data byte

*The command for activating the CS on a GPIO pin (after configuration) is only a command byte: ‘11Tx 0ccc’.

Example: 0xC15C. This instruction activates CS on GPIO1. The 5C is the checksum [(0x9B + 0xC1) mod

0x100 = 0x5C]

The checksum is calculated only for the communication to or from the PGA280. In extended SPI mode, if

connecting the CS (ECS) for other SPI devices to the PGA280 port, the external device has to provide its own

checksum character, if available.

Examples:

0x4101DD Send Reset [CHKsum calculation: (0x9B + 0x41 + 0x01) mod 0x100 = 0xDD]

0x4B11F7 Activate CHKsum bit 0 of Register 11. Note that activation of the CHK bit requires proper

Checksum.

0x8B260000 Read Configuration Register 11 (contains 0x11) [0x9B + 0x8B = 0x26]

0x1137 Response includes the CHKsum [0x9B + 0x8B + 0x11 = 0x37]

0x44FFDF Reset all error flags in Register 4 [0x9B + 0x44 + 0xFF = 0xDF]

0x841F0000 Read Register 4 [0x9B + 0x84 = 0x1F]

0x001F No errors indicated if 00 [0x9B + 0x84 + 0x00 = 0x1F]

Commands can be chained while CS is active low; all bytes are added for checksum:

Examples:

0x4C 07 EE; Activate MUX0, MUX1, and MUX2 to GPIO0, GPIO1, and GPIO2, respectively

0x64 FF FE 40 1B 59 80 D9 00 00; Write to Register 4 with BUF trigger and reset all error flags

: Write to Register 0 and set gain 1V/V; MUX0 and MUX1 set high

: Read Register 0, provide 16 SCLKs

40

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Product Folder Link(s): PGA280

PACKAGE OPTION ADDENDUM

www.ti.com

14-Sep-2009

PACKAGING INFORMATION

Orderable Device

PGA280AIPW

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TSSOP

PW

24

60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

PGA280AIPWR

TSSOP

PW

24

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Sep-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

PGA280AIPWR

TSSOP

PW

24

2000

330.0

16.4

6.95

8.3

1.6

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Sep-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP PW 24

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 33.0

PGA280AIPWR

2000

Pack Materials-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

型号:	PGA280AIPWR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	TSSOP
包装说明：	TSSOP-24
针数：	24
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.33.00.01
风险等级：	1.32
放大器类型：	INSTRUMENTATION AMPLIFIER
最大平均偏置电流 (IIB)：	0.002 µA
最大输入失调电流 (IIO)：	0.002 µA
最大输入失调电压：	15 µV
JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e4
长度：	7.8 mm
湿度敏感等级：	2
负供电电压上限：	-20 V
标称负供电电压 (Vsup)：	-15 V
最大非线性：	0.001%
功能数量：	4
端子数量：	24
最高工作温度：	125 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP24,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：	TR
峰值回流温度（摄氏度）：	260
电源：	3,+-15 V
认证状态：	Not Qualified
座面最大高度：	1.2 mm
标称压摆率：	1 V/us
子类别：	Instrumentation Amplifier
供电电压上限：	20 V
标称供电电压 (Vsup)：	15 V
表面贴装：	YES
温度等级：	AUTOMOTIVE
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm
Base Number Matches：	1

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