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Philips Semiconductors

Objective specification

PowerMOS transistor

Isolated version of PHP10N40E

PHX5N40E

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel enhancement mode

field-effect power transistor in a full

pack, plastic envelope featuring high

avalanche energy capability, stable

blocking voltage, fast switching and

high thermal cycling performance

withlowthermalresistance. Intended

for use in Switched Mode Power

Supplies (SMPS), motor control

circuits and general purpose

switching applications.

SYMBOL

PARAMETER

MAX.

UNIT

V_DS

I_D

Drain-source voltage

Drain current (DC)

Total power dissipation

Drain-source on-state resistance

400

4.9

V

A

W

Ω

P_tot

30

R_DS(ON)

0.55

PINNING - SOT186A

PIN CONFIGURATION

SYMBOL

1

DESCRIPTION

d

case

gate

2

drain

g

3

source

case isolated

1

2 3

s

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DS

V_DGR

±V_GS

I_D

Drain-source voltage

-

400

30

V

A

Drain-gate voltage

Gate-source voltage

Drain current (DC)

R_GS= 20 kΩ

T_hs= 25 ˚C

T_hs= 100 ˚C

T_hs= 25 ˚C

4.9

3.0

19.6

I_DM

Drain current (pulse peak

value)

Source-drain diode current

(DC)

Source-drain diode current

(pulse peak value)

Total power dissipation

Storage temperature

Junction temperature

I_DR

T_hs= 25 ˚C

-

4.9

A

I_DRM

19.6

P_tot

T_stg

T_j

-

-55

-

30

150

W

˚C

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

W_DSS

Drain-source non-repetitive I_D= 10 A; V_DD≤ 50 V; V_GS= 10 V;

unclamped inductive turn-off R_GS= 50 Ω

energy

T_j= 25˚C prior to surge

T_j= 100˚C prior to surge

-

520

83

13

mJ

1

W_DSR

Drain-source repetitive

I_D= 10 A; V_DD≤ 50 V; V_GS= 10 V;

unclamped inductive turn-off R_GS= 50 Ω; T_j≤ 150 ˚C

energy

1. Pulse width and frequency limited by T_j(max)

November 1996

1

Rev 1.000

Philips Semiconductors

Objective specification

PowerMOS transistor

PHX5N40E

ISOLATION LIMITING VALUE & CHARACTERISTIC

T_hs= 25 ˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

V_isol

C_isol

R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal

-

2500

V

three terminals to external

heatsink

waveform;

R.H. ≤ 65% ; clean and dustfree

Capacitance from T2 to external f = 1 MHz

heatsink

-

10

-

pF

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

R_{th j-hs}

R_{th j-a}

Thermal resistance junction to with heatsink compound

-

4.1

-

K/W

heatsink

Thermal resistance junction to

ambient

55

STATIC CHARACTERISTICS

T_j= 25 ˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

V_(BR)DSS

Drain-source breakdown

voltage

V_GS= 0 V; I_D= 0.25 mA

400

-

V

V_GS(TO)

I_DSS

Gate threshold voltage

Drain-source leakage current

V_DS= V_GS; I_D= 0.25 mA

V_DS= 400 V; V_GS= 0 V; T_j= 25 ˚C

2.0

3.0

10

4.0

100

1.0

100

0.55

V

µA

mA

nA

Ω

-

V

_DS= 320 V; V_GS= 0 V; T_j= 125 ˚C

0.1

10

I_GSS

R_DS(ON)

Gate-source leakage current

Drain-source on-state

resistance

Source-drain diode forward

voltage

V_GS= ±30 V; V_DS= 0 V

V_GS= 10 V; I_D= 5 A

0.4

V_SD

I_F= 10 A ;V_GS= 0 V

-

1.4

2.0

V

November 1996

2

Rev 1.000

Philips Semiconductors

Objective specification

PowerMOS transistor

PHX5N40E

DYNAMIC CHARACTERISTICS

T_j= 25 ˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

g_fs

Forward transconductance

V_DS= 15 V; I_D= 5 A

4

6

-

S

C_iss

C_oss

C_rss

Input capacitance

Output capacitance

Feedback capacitance

V_GS= 0 V; V_DS= 25 V; f = 1 MHz

-

1500 1800

pF

170

70

270

120

Q_g(tot)

Q_gs

Q_gd

Total gate charge

Gate to source charge

Gate to drain (Miller) charge

V_GS= 10 V; I_D= 10 A; V_DS= 320 V

-

65

8

37

-

nC

t_{d on}

t_r

t_{d off}

t_f

Turn-on delay time

Turn-on rise time

Turn-off delay time

Turn-off fall time

V_DD= 30 V; I_D= 2.8 A;

V_GS= 10 V; R_GS= 50 Ω;

R_GEN= 50 Ω

-

20

60

200

75

40

90

250

90

ns

t_rr

Source-drain diode reverse

recovery time

Source-drain diode reverse

recovery charge

I_F= 10 A; -dI_F/dt = 100 A/µs;

-

500

6.0

-

ns

Q_rr

V_GS= 0 V; V_R= 100 V

µC

L_d

L_s

Internal drain inductance

Internal source inductance

Measured from drain lead 6 mm

from package to centre of die

Measured from source lead 6 mm

from package to source bond pad

-

4.5

7.5

-

nH

November 1996

3

Rev 1.000

Philips Semiconductors

Objective specification

PowerMOS transistor

PHX5N40E

MECHANICAL DATA

Dimensions in mm

Net Mass: 2 g

10.3

max

4.6

max

3.2

3.0

2.9 max

2.8

Recesses (2x)

6.4

2.5

0.8 max. depth

15.8

max

seating

plane

15.8

max.

19

max.

3 max.

not tinned

3

2.5

13.5

min.

1

2

3

M

0.4

1.0 (2x)

0.6

2.5

0.9

0.7

2.54

0.5

5.08

1.3

Fig.1. SOT186A; The seating plane is electrically isolated from all terminals.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent

damage to MOS gate oxide.

2. Refer to mounting instructions for F-pack envelopes.

3. Epoxy meets UL94 V0 at 1/8".

November 1996

4

Rev 1.000

Philips Semiconductors

Objective specification

PowerMOS transistor

PHX5N40E

DEFINITIONS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Electronics N.V. 1996

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the

copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury. Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

November 1996

5

Rev 1.000

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