PI3VDP101LSZDE全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

PI3HDX412BD

HDMI 1.4b 1:2 Splitter/Demux for 3.4Gbps Data Rate

with Equalization & Pre-emphasis

Features

General Description

Pericom Semiconductor’s PI3HDX412BD, active-drive

ꢀySupport up to 3.4Gbps TMDS Serial Link Compliant

switch solution is targeted for high-resolution video net-

with HDMI 1.4b requirement

TM

works that are based on HDMI /DVI standards, and

ꢀyHDMI 1-to-2 Splitter or 1-to-2 DeMux with

Equalization & Pre-emphasis up to 340 MHz Clock

TMDS signal processing.

The PI3HDX412BD is an active single TMDS channel to two

TMDS channel Splitter and DeMux with Hi-Z outputs. The

device drives differential signals to multiple video display

units.

ꢀyAC or DC Coupled Diﬀerential Signaling Input

ꢀyConﬁgurableTMDSOutputSignalwithPortSelection,

Pre-emphasis, Voltage Swing, Slew Rate Control

ꢀySupport Squelch Mode with Built-in Clock detector

It provides controllable output swing levels that can be con-

trolled through pin control or I2C control, depending on

the mode select pin. This solution also provides a unique

advanced pre-emphasis technique to increase rise and fall

times.

2

ꢀyControl Status Register controlled by Pin strap or I C

mode programming

ꢀyESD Protection on I/O pins to connector: 8KV Contact

per IEC6100-4-2 and 2KV HBM

TM

The maximum HDMI /DVI data rate of 3.4Gbps provides

ꢀySupply Voltage: 3.3V

ꢀyIndustrial Temperature Range: -40 C to 85 C

a 1920x1080 @60Hz resolution or 4K @30Hz required for

4K HDTV and PC graphics products. Due to its active uni-

directional feature, this switch is designed for usage only

for the video driver’s side. For PC graphics application, the

device sits at the driver’s side to switch between multiple dis-

play units, such as PC LCD monitor, projector, TV, etc.

o

ꢀyPackaging (Pb-free & Green): 56-contact TQFN

(ZB56)

PI3HDX412BD ensures transmitting high bandwidth video

streams from PC graphics source to end display units. It will

also provide enhanced robust ESD/EOS protection, which is

required by many consumer video networks today.

56 55 54 53 52 51 50 49 48 47 46 45 44 43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

VDD

MS

VDD

GND

D2P

1

2

3

4

D0P1

D0N1

GND

5

6

7

D2N

VDD

D1P

CLKP1

CLKN1

VDD

PI3HDX412BD

Port_A

TQFN- 56

8

9

D1N

D0P

D2P2

D2N2

GND

D1P2

D1N2

VDD

10

11

12

13

14

D0N

VDD

CLKP

CLKN

GND

HDMI Input

HDMI Outputs

D0P2

Port_B

15 16 17 18 19 20 21 22 23 24 25 26 27 28

PI3HDX412BD Package & Pinout

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Application Block Diagram

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

TMDS In/Out Pin Assignment

Pin # Pin Name

Type

Description

4

D2P

D2N

I

5

I

7

D1P

I

Input Port. TMDS Clock and Data Input pins. When Input Termination

Resistor (Rt = 50 Ohm) tied to VDD or GND, Rpd=200 kOhm shall be

"OFF" state.

8

D1N

I

9

D0P

I

I2C registers can control Rt and Rpd ON/OFF state.

10

12

13

25

26

28

29

31

32

34

35

37

38

40

41

43

44

46

47

D0N

I

CLKP

CLKN

CLKN2

CLKP2

D0N2

D0P2

D1N2

D1P2

D2N2

D2P2

CLKN1

CLKP1

D0N1

D0P1

D1N1

D1P1

D2N1

D2P1

I

O

Output Port 1. TMDS Clock and Data Output pins. ROUT_SEL pin en-

ables Output Termination Resistor (Rout=50 Ohm).

Output Port 2. TMDS Clock and Data Output pins. ROUT_SEL pin en-

ables Output Termination Resistor (Rout=50 Ohm).

Note: In TMDS Data and Clock Diﬀerential Pair, the polarity +/- (or P/N) of each pair can use interchangeably. When input TMDS Input Clock polarity +/-

pin swaps, output TMDS Clock of port 1 and port 2 shall swapped accordingly.

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03/24/14

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

Control Pins

Pin # Pin Name

Type Description

Mode Selection Pin. Internal pull-up at 100K Ohm.

2

1

MS

I

"High" :

I C Control Mode Selection

"Low" : Pin Control Mode Selection

2

Shared Pin. EQ2 pin or I C Clock pin. I C pin is compatible with standard I C-

Bus speciﬁcation, up to 400 Kbps.

Pin#1 MS sets "High" : Pin#19 assigns to SCL_CTL pin

Pin#1 MS sets "Low" : Pin#19 assigns to EQ2 pin

Internally Pull-Up at 100 Kohm and Pull-Down at 100 Kohm.

Pin Control EQ setting table is shown below. "M" is Tri-state.

EQ2

EQ1

Equalization Setting

(dB)

19

20

EQ2/SCL_CTL

EQ1/SDA_CTL

(Pin# 19)

(Pin# 20)

IO

0

M

0

2.5

5

M

0

7.5

10

1

Pin#1 MS =

"Low"

M

1

M

0

12.5

15

1

M

1

17.5

20

1

Shared Pin. SW or EMP or I2C_ADR pins.

When Pin#1 MS="High" : These Shared Pins assign to I2C_ADR[3:0]

When Pin#1 MS="Low" : These Shared Pins assign to SW1/2 and EMP1/2

49

50

51

52

SW1/I2C_ADR0

SW2/I2C_ADR1

EMP1/I2C_ADR2

EMP2/I2C_ADR3

ese SW2 and SW1 pins control output voltage swing adjustment as following

table. ese SW pins have internal Pull-Up 100K Ohm.

I

SW2 (Pin#50) SW1 (Pin#49)

Output Voltage Swing

0

1

0

1

0

1

500 mV

-10 %

+10 %

+20 %

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

Pin # Pin Name

Type Description

EMP2 and EMP1 pins control output voltage pre-emphasis. ese pins have

internally Pull-Up 100 Kohm.

49

EMP2 (Pin#52) EMP1 (Pin#51) Pre-emphasis Setting (dB)

50

0

1

0

1

0

1

0

(Continued)

51

I

1.5

2.5

3.5

52

Output Enable Control pin. Internally pull-up at 100 Kohm.

"High" :

Output Port Enable

56

OE

I

"Low" : Turn oﬀ Rout and Rt(termination resistor). TMDS Receiver and TMDS

Output Drivers are "OFF" state.

Direction Control pin

54

55

16

DR

I

"High" : All ports are Active at same time

"Low" : Output Ports are controlled by SEL1 (Pin#55) control

Port 1 or Port 2 Output Enable Selection pin. Internal pull-up at 100 Kohm.

SEL1

"High" : Enable Output Port 2

"Low" : Enable Output Port 1

2

SEL_OUT pin. I C Register Oﬀset 0x00 Bit[5] can control this pin status.

SEL_OUT

O

Oﬀset 0x00 Bit[5] ="1" :

Oﬀset 0x00 Bit[5] ="0" :

Enable Output Port 1 Output

Disable Output Port 1 Output

Source termination selection pin. Internal pull-up at 100K Ohm.

ROUT_SEL

"High" :

Source Termination Output (Rout) Resistor is "ON", connect to VDD in

Output Driver

"Low" :

17

I

Source Termination Output (Rout) Resistor is "OFF". Open-Drain Output

Driver is open drain

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

Power/Ground Pins

Pin #

Pin Name Type

Description

LDO Output Pin for internal core supplier. Add external 4.7 uF ca-

pacitor to GND

18

VDD18

GND

Power

Ground Ground Pins

3,14,21,23,27,33,39,45,53

2,6,11,15,24,30,36,42,48 VDD

Power 3.3V Power Supply

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

Block Diagram

VDD18

VDD

Rout

LDO

VDD or GND

CLKP/N

D[0:2]P/N

Rt

VDD

DeMux

Rout

Rpd

GND

Control & Status Register

I2C Controller

SCL_CTL

SDA_CTL

EQ#,MS,DR, SEl#

SW.EMP# Control Pins

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

Functional Description

Squelch Mode:

Output Disable (Squelch) Mode uses TMDS Clock channel signal detection. When low voltage levels on the TMDS input clock

signals are detected, Squelch state enables and TMDS output port signals shall disable; when the TMDS clock input signal levels

are above a pre-determined threshold voltage, output ports shall return to the normal voltage swing levels.

When enable Squelch mode, input termination resistor will be enabled together. When Squelch is disabled through I2C register

programming RX_SET[1]="1" and no TMDS input signal condition, TMDS D[0:2]P/N will be undetermined status. In Squelch

state, TMDS output is high impedance state or TMDS output port shall 50 Ohm pull-up at source termination output.

Function Control Table

OE

MS

DR

SEL1 HDMI Outputs

0

x

All Port Disable

Pin Cotrol Mode

1

0

1

0

x

0

1

All Ports Enable

Enable Port 1

Enable Port 2

I2C Control Mode

1

x

I2C Programming Mode

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

I²C Register Control Programming

2

I C Register Control

Pin Name

I/O

Description

SCL_CTL

SDA_CTL

I

I2C Clock, compatible with I2C-bus specification, up to 400 kb/s

I2C Data, compatible with I2C-bus specification, up to 400 kb/s

IO

I2C_ADR[3:0]

I

I2C Control Address Setting

I2C Control registers output

Byte output : 0x00 - 0x07

O

2

I C Address Byte

b[7]

b[6]

b[5]

b[4]

b[3]

b[2]

b[1]

b[0]

MSB

(R/W)

Address Byte

1

0

1

A3

A2

A1

A0

1/0*

Note: Read "1", Write "0"

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

Power Up

Condition

Oﬀset

Name

Description

Type

[7] Enable TMDS Standby mode.

In standby mode, TMDS equalizer and output driver

shall power down.

"0": Standby mode

"1": Normal mode

[6] Reserved

[5] Output TMDS Port 1 Select

"0": Disable

0x00

CONFIG[7:0]

0xFF

R/W

"1": Enable

[4] Output TMDS Port 2 Selected

"0": Disable

"1": Enable

[3] Reserved

[2:0] Reserved

TMDS Receiver Equalization Setting Registers

[7] Disable Input Port input termination resistors

"0" : Enable Rpd connection

"1" : Disable Rpd connection

[6] TMDS Input termination V-bias selection

"0": Connect to GND

"1": Connect to VDD

[5] V-bias register selection enable

"0": bit[6] control disable

"1": bit[6] control enable

[4:2] EQ programmable setting

b[4:2]

000

001

010

011

100

101

110

111

EQ Setting (dB)

2.5

5

0x01

RX_SET[7:0]

0x00

R/W

7.5

10

12.5

15

17.5

20

[1] Squelch Control Bit

"0": Squelch enable

"1": Squelch disable

[0] Reserved

0x02

Reserved

[7:0] Reserved

0x00

R/W

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

Power Up

Condition

Oﬀset

Name

Description

Type

TMDS Port 1 Output setting

[7] TMDS output control

"0": Open drain

"1": Double termination

[6:4] TMDS output Pre-emphasis control

"000": 0 dB

"001": 1.5 dB

"010": 2.5 dB

"011": 3.5 dB

"1xx": 6 dB (750 mVpp swing)

TX_SET[7:0] for

port1

0x03

0x00

R/W

[3:2] TMDS output swing setting

"00": 500 mV as default

"01": -10%

"10": +10%

"11": +20%

[1:0] TMDS output slew rate setting

"00": as default

"01" / "10": + 5%

"11": +10%

TMDS Port 2 Output setting

[7] TMDS output control

"0": Open drain

"1": Double termination

[6:4] TMDS output Pre-emphasis control

"000" : 0 dB

"001" : 1.5 dB

"010" : 2.5 dB

"011" : 3.5 dB

"1xx" : 6 dB ( 750 mVpp swing)

TX_SET[7:0] for

port2

0x04

0x00

R/W

[3:2] TMDS output swing setting

"00" : 500 mV as default setting

"01" : -10%

"10" : +10%

"11" : +20%

[1:0] TMDS output slew rate setting

"00" : Default setting

"01" / "10" : + 5%

"11" : +10%

0x05

0x06

0x07

Reserved

[7:0] Reserved

0x00

0x0F

0x00

R/W

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

I²C Data Transfer

1. Read Sequence

ACK

NO ACK

DEV SEL

DATA OUT 1

DATA OUT N

R / W

2. Write Sequence

ACK

DEV SEL

DATA IN 1

DATA IN N

R / W

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

Absolute Maximum Ratings

Note:

Supply Voltage to Ground Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V

Stresses greater than those listed under MAXIMUM RAT-

INGS may cause permanent damage to the device. is is a

stress rating only and functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this speciﬁcation is not implied. Ex-

posure to absolute maximum rating conditions for extended

periods may aﬀect reliability.

DC SIG Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to V +0.5V

DD

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +85°C

Thermal Characteristics

Symbol

Parameter

Ratings

Units

125

5

T

R

Junction Temperature

ermal Resistance, Junction to Case

ermal Resistance, Junction to Ambient

°C

°C/W

Jmax

θJC

24

θJA

Electrical Characteristics _{T =25 °C unless otherwise noted}

J

DC Specifications _{VDD=3.3V +/- 10%}

Symbol

Parameter

Test

Conditions

Min.

Typ.

Max.

Units

V

Operation Voltage

3.0

3.3

3.6

V

DD

I

VDD Supply Current

250

290

mA

DD

OE = 1, No

input signal

VDD Quiescent Current

Standby mode

50

1

80

5

mA

DDQ

STB

OE = 0

TMDS Diﬀerential Pins

VDD = 3.3 V,

Rout=50 Ω

V

Single-ended high level output voltage

VDD-10

VDD+10 mV

VDD–400 mV

OH

VOL

Single-ended low level output voltage

Single-ended output swing voltage

Overshoot of output diﬀerential voltage

VDD-600

400

Vswing

VOD(O)

600

180

mV

Undershoot of output diﬀerential volt-

age

VOD(U)

200

mV

Change in steady-state common- mode

output voltage between logic states

VOC(SS)

IOS

5

mV

mA

Short Circuit output current

-12

-24

12

24

Short Circuit output current at double

termination mode

IOS

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

Symbol

Parameter

Test

Conditions

Min.

Typ.

Max.

Units

Single-ended input voltage under high

impedance input or open input

VI(open)

RT

IL = 10 uA

VDD-10

45

VDD+10 mV

Input termination resistance

VIN = 2.9 V

50

30

55

Ohm

VDD = 3.6 V,

OE = 0

IOZ

Leakage current with Hi-Z I/O

100

μA

Control pins (OE, SEL1, EMP2, EMP1, SW2, SW1, MS)

I

High level digital input current

Low level digital input current

High level digital input voltage

Low level digital input voltage

V

=V

DD

-10

-50

2.4

0

10

μA

V

IH

IL

IH

IL

= GND

V

IH

IL

0.8

V

AC Specifications

Symbol

Parameter

Test

Conditions

Min.

Typ.

Max.

Units

tpd

Propagation delay

2000

ps

Diﬀerential output signal rise time (20% VDD=3.3V,

- 80%), 0 dB / Open drain

t

117

r

f

ROUT=50 ohm

Diﬀerential output signal fall time (20%

- 80%), 0 dB / Open drain

ps

t

Pulse skew

15

25

50

ps

ns

us

ns

sk(p)

sk(D)

sk(O)

sx

Intra-pair diﬀerential skew

Inter-pair diﬀerential skew

Select to switch output

Enable time

100

550

10

1

en

Disable time

50

dis

Peak-to-peak output jitter CLK residual

jitter

tjit_clk(pp)

Data: 3.4 Gbps

data pattern

10

28

ps

Peak-to-peak output jitter Date residual

jitter

tjit_data(pp)

Clock: 340 MHz

Note:

1. Overshoot of output diﬀerential voltage V

= (V

OD(O)

*2) * 15%

SWING(MIN)

OD(O)

SWING(MAX)

= (V

2. Undershoot of output diﬀerential voltage V

*2) * 25%

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

Inter-pair Skew Definition

Intra-pair Skew Definition

Test Setup of DC-coupled TMDS Input Measurement

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

Rise/Fall Time and Single-ended Swing Voltage

Typical Splitter Application

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

Power Supply Decoupling Circuit

It is recommended to put 0.1 µF decoupling capacitors on each VDD pins of our part, there are four 0.1 µF decoupling

capacitors are put in Figure 1 with an assumption of only four VDD pins on our part, if there is more or less VDD pins

on our Pericom parts, the number of 0.1 µF decoupling capacitors should be adjusted according to the actual number

of VDD pins. On top of 0.1 µF decoupling capacitors on each VDD pins, it is recommended to put a 10 µF decoupling

capacitor near our part’s VDD, it is for stabilizing the power supply for our part. Ferrite bead is also recommended for

isolating the power supply for our part and other power supplies in other parts of the circuit. But, it is optional and de-

pends on the power supply conditions of other circuits.

Recommended Power Supply Decoupling Capacitor Diagram

Requirements on the De-coupling Capacitors

ere is no special requirement on the material of the capacitors. Ceramic capacitors are generally being used with typi-

cally materials of X5R or X7R.

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

Layout and Decoupling Capacitor Placement Consideration

ꢀyEach 0.1 µF decoupling capacitor should be placed as close as possible to each VDD pin.

ꢀyVDD and GND planes should be used to provide a low impedance path for power and ground.

ꢀyVia holes should be placed to connect to VDD and GND planes directly.

ꢀyTrace should be as wide as possible

ꢀyTrace should be as short as possible.

ꢀye placement of decoupling capacitor and the way of routing trace should consider the power ﬂowing criteria.

ꢀy10 µF Capacitor should also be placed closed to our part and should be placed in the middle location of 0.1 µF

capacitors.

ꢀyAvoid the large current circuit placed close to our part; especially when it is shared the same VDD and GND planes.

Since large current ﬂowing on our VDD or GND planes will generate a potential variation on the VDD or GND of our

part.

Decoupling Capacitor Placement Diagram

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

Package Mechanical: 56-pin TQFN (ZB56)

DATE: 03/18/09

DESCRIPTION: 56-contact, Thin Fine Pitch Quad Flat No-lead (TQFN)

PACKAGE CODE: ZB (ZB56)

REVISION: E

DOCUMENT CONTROL #: PD-2008

Note:

For latest package info, please check: http://www.pericom.com/products/packaging

Ordering Information

Ordering Code

Package Code

Package Description

PI3HDX412BDZBE

ZB

56-pin, Pb-free & Green TQFN, Source Termination Type

Notes:

ermal characteristics can be found on the company web site at www.pericom.com/packaging/

PI3HDX412B : Root Part Number

-D/E : D= Source Termination TMDS Top Mount Type, E = Source Termination TMDS Bottom Mount Type

-ZB = 56-pin TQFN Package Type

-E = Pb-free and Green

Adding an -X Suﬃx = Tape/Reel Type

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PI3HDX412BD

3.4Gbps HDMI 1.4b 1:2 Splitter/Demux with Equalization & Pre-emphasis

型号:	PI3VDP1430ZBE
是否Rohs认证：	符合
生命周期：	Obsolete
IHS 制造商：	DIODES INC
包装说明：	HVQCCN,
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.63
商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-XQCC-N48
长度：	7 mm
功能数量：	1
端子数量：	48
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN
封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED
座面最大高度：	1 mm
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7 mm
Base Number Matches：	1

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