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深圳市中利达电子科技有限公司
PT7V4050TDCGA32.768/2.048
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首天国际（深圳）科技有限公司
PT7V4050TDCGA32.768/2.048
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北京元坤伟业科技有限公司
PT7V4050TDCGA32.768/2.048
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柒号芯城电子商务（深圳）有限公司
PT7V4050TDCGA32.768/2.048
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18922803401

深圳市毅创腾电子科技有限公司
PT7V4050TDCGA32.768/2.048

数量1047
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深圳市诚达吉电子有限公司
PT7V4050TDCGA32.768/2.048

数量6925
厂家PT
封装DIP
批号2024+
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产品型号PT7V4050TDTHA22.1184的Datasheet PDF文件预览

Data Sheet

PT7V4050

PLL with quartz stabilized VCXO

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Features

General Description

• PLL with quartz stabilized VCXO

• Loss of signals alarm

The device is composed of a phase-lock loop with an

integrated VCXO for use in clock recovery, data re-

timing, frequency translation and clock smoothing

applications in telecom and datacom systems.

• Return to nominal clock upon LOS

• Input data rates from 8 kb/s to 65 Mb/s

• Tri-state output

Crystal Frequencies Supported:

12.000~65.536 MHz

• User defined PLL loop response

• NRZ data compatible

• 3.3V and 5.0V power supply

Block Diagram

RCLK

CLKIN

DATAIN

Phase Detector &

Loss Of Signal

Circuit

RDATA

LOS

HIZ

PHO

CLK1

LOSIN

VCXO

Divider

CLK2

OPN

OPP

Amp

OPOUT

Ordering Information

Frequencies using at CLK1 (MHz)

PT7V4050

51.840 / 25.920

CLK2 Frequency

12.000

16.128

18.432

22.579

28.000

34.368

44.736

51.840

54.000

12.288

13.384

18.936

24.586

30.720

38.880

47.457

65.536

60.000

12.624

16.777

20.000

24.704

32.000

40.000

49.152

19.440

61.440

13.00

16.000

17.920

22.1184

27.000

33.330

41.943

50.000

40.960

62.500

Device Type

CLK1 Frequency

16.896

20.480

25.000

32.768

41.2416

49.408

35.328

62.208

16-pin clock recovery module

Power Supply

A: 5.0V

B: 3.3V

PackageLeads

T: Thru-Hole

G: Surface Mount

M: Metal Can

C: 20ppm

F: 2ppm

CLK2 Divider

G: 50ppm

A: Divide by 2 E: Divide by 32

B: Divide by 4 F: Divide by 64

C: Divide by 8 G: Divide by 128

D: Divide by 16 H: Divide by 256

K: Disable

H: 100ppm

Temperature Range

C: 0 C to 70 C

T: -40 C to 85 C

PT0125(07/04)

Ver:1

Data Sheet

PT7V4050

PLL with quartz stabilized VCXO

Pin Configuration

PT7V4050

V_CC

CLK1

OPN

OPOUT

OPP

CLK2

RDATA

RCLK

LOS

LOSIN

PHO

DATAIN

GND

CLKIN

Pin Description

Pin No

Pin Name

Type

Description

Control voltage input to internal voltage controlled crystal oscillator (VCXO).

Negative input terminal to internal operational amplifier.

Output terminal of internal operational amplifier.

OPN

OPOUT

OPP

Positive input terminal to internal operational amplifier.

TTL input. When LOSIN is set to HIGH, VC disabled, and when set to LOW, VC to

VCXO are enabled. (Internal pull-down resistor)

LOSIN

PHO

DATAIN

GND

Output signal of phase detector.

TTL input. Input data stream to phase detector.

Ground.

CLKIN

LOS

TTL input. Input clock to phase detector.

Signal loss indication for DATAIN, high active.

Output recovered clock.

RCLK

RDATA

CLK2

Output recovered data stream.

Output clock with divided function.

TTL input. When HIZ is set to LOW, the device is in standby state and the outputs are

set to high impedance. (Internal pull-up resistor)

HIZ

CLK1

V_CC

Output clock of internal VCXO frequency.

power supply

Notes:

1. LOSIN input sets to HIGH, VC is disabled and the VCXO returns to it’s nominal center frequency. When sets to LOW, VC to

VCXO is enabled.

2. LOS output sets to HIGH, if no transitions are detected at DATAIN after 256 clock cycles. LOS output sets to LOW as soon

as a transition occurs at DATAIN.

3. HIZ input sets LOW, output pins CLK1, CLK2, RCLK, and RDATAbuffers are set to high-impedance state. When set to logic

high or no connection, the device functions and output pins CLK1, CLK2, RCLK, and RDATA etc. are active.

PT0125(07/04)

Ver:1

Data Sheet

PT7V4050

PLL with quartz stabilized VCXO

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested)

Note:

Storage Temperature ........................................... -55^oCto+125^oC

Stresses greater than those listed under MAXIMUM RAT-

Power Supply Voltage .................................................-0.5to+7V

INGS may cause permanent damage to the device. This is a

Input High Voltage ....................................................... +7VMax.

stress rating only and functional operation of the device at

Input Low Voltage ....................................................... -0.5VMin.

these or any other conditions above those indicated in the

Input ESD Protection .................................................2000VMin.

operational sections of this specification is not implied. Ex-

posure to absolute maximum rating conditions for extended

periods may affect reliability.

DC Electrical Characteristics

(V_CC=4.5 to 5.5V)

Symbol

Parameters

Conditions

Min

Max

Units

V_CC

I_LEAK

V_TIH

Supply Voltage

4.5

-10

5.5

µA

Input Leakage Current

TTL Input High Voltage

0~V_CC

V_TIL

TTL Input Low Voltage

0.8

0.4

V_OH1

Output High Voltage for CLK1

& 2, RCLK&RDATA

Output Low Voltage for CLK1

& 2, RCLK&RDATA

Ioh = -8mA

Iol = 8mA

2.4

V_OL1

V_OH2

V_OL2

Output High Voltage for LOS

Ioh = -3mA

Iol = 3mA

2.4

Output Low Voltage for LOS

Input Pull up Current for HIZ

0.4

I_PULLUP

I_PULLDOWN

-160

µA

Input Pull down Current for

LOSIN

I_CC

T_A

Maximum Supply Current

Full Active

^oC

Ambient Temperature

-40

(V_CC=3.0 to 3.6V)

Symbol

Parameters

Conditions

Min

Max

Units

V_CC

I_LEAK

V_TIH

Supply Voltage

4.5

3.0

5.5

3.6

µA

Input Leakage Current

TTL Input High Voltage

0~V_CC

-10

-5

2.0

V_TIL

TTL Input Low Voltage

0.8

V_OH1

V_OL1

Output High Voltage for CLK1

& 2, RCLK&RDATA

Output Low Voltage for CLK1

& 2, RCLK&RDATA

Ioh = -8mA

Iol = 8mA

2.4

2.0

0.4

0.5

V_OH2

V_OL2

Output High Voltage for LOS

Ioh = -3mA

Iol = 3mA

2.4

2.0

Output Low Voltage for LOS

Input Pull up Current for HIZ

0.4

0.5

I_PULLUP

I_PULLDOWN

-160

µA

Input Pull down Current for

LOSIN

I_CC

T_A

Maximum Supply Current

Full Active

5650

^oC

Ambient Temperature

-40

PT0125(07/04)

Ver:1

Data Sheet

PT7V4050

PLL with quartz stabilized VCXO

AC Electrical Characteristics

(V_CC=4.5 to 5.5V)

Parameter

Symbol

Min

Typical

Max

Unit

Input NRZ Data Rates

DATAIN

0.008

65.536

32.768

M b/s

Input RZ Data and Clock Rates

Nominal Output Frequency

Clock Output 1

CLK1

CLK2

12.00

CLK1 /256

65.536

CLK1 /2

MHz

Clock Output 2

Transition Times:

Rise Time (0.5V to 2.5V)

Fall Time (2.5V to 0.5V)

t_R

t_F

0.5

Symmetry or Duty cycle (VS = 1.4V)

CLK1

CLK2

RCLK

SYM 1

SYM 2

RCLK

Control Voltage Bandwidth (-3 dB,VC =

0.5V_CC)

kHz

Sensitivity @ VC = V_CC/2

100

ppm/V

∆F/∆VC

Nominal Output Frequency on Loss of Signal:

Clock Output 1 & 2

CLK1

CLK2

-75

ppm from fo 1

ppm from fo 2

Phase Detector Gain

K D

0.53

V/rad

x Data

Density

(V_CC=3.0 to 3.6V)

Parameter

Symbol

Min

Typical

Max

Unit

Input NRZ Data Rates

DATAIN

0.008

65.536

32.768

M b/s

Input RZ Data and Clock Rates

Nominal Output Frequency

Clock Output 1

CLK1

CLK2

12.00

CLK1 /256

65.536

CLK1 /2

MHz

Clock Output 2

Transition Times:

Rise Time (0.4V to 2.0V)

Fall Time (2.0V to 0.4V)

t_R

t_F

0.5

Symmetry or Duty cycle (VS = 11..14V)

CLK1

CLK2

RCLK

SYM 1

SYM 2

RCLK

Control Voltage Bandwidth (-3 dB,VC =

0.5V_CC)

kHz

Sensitivity @ VC = V_CC/2

200

ppm/V

∆F/∆VC

Nominal Output Frequency on Loss of Signal:

Clock Output 1 & 2

CLK1

CLK2

-75

-100

-75

-100

100

ppm from fo 1

ppm from fo 2

Phase Detector Gain

K D

0.53

V/rad

x Data

Density

PT0125(07/04)

Ver:1

Data Sheet

PT7V4050

PLL with quartz stabilized VCXO

Packaging Information

16-pin SMD (G)

20.32

10.16

2.54

1.2

20.32

PT0125(07/04)

Ver:1

Data Sheet

PT7V4050

PLL with quartz stabilized VCXO

16-pin DIP (T)

16-pin Metal Can (M)

19.66mm

21.65mm

R0.2

7.62

16－ 0.45

2.54

PT0125(07/04)

Ver:1

Data Sheet

PT7V4050

PLL with quartz stabilized VCXO

Notes

PericomTechnologyInc.

Email: support@pti.com.cn

Web Site: www.pti.com.cn, www.pti-ic.com

China:

No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China

Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181

Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong

Tel: (852)-2243 3660 Fax: (852)- 2243 3667

U.S.A.:

3545 North First Street, San Jose, California 95134, USA

Tel: (1)-408-435 0800 Fax: (1)-408-435 1100

Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to

improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any

circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry

described herein is free from patent infringement or other rights, of Pericom Technology Incorporation.

PT0125(07/04)

Ver:1

PT7V4050TDCGA32.768/2.048相关文章

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深圳市中利达电子科技有限公司服务专线: 0755-83200645/13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

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深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

柒号芯城电子商务（深圳）有限公司服务专线: 18922803401 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

PT7V4050TDCGA49.408/12.352产品参数

型号:	PT7V4050TDCGA49.408/12.352
生命周期：	Active
IHS 制造商：	DIODES INC
Reach Compliance Code：	unknown
风险等级：	5.72
模拟集成电路 - 其他类型：	PHASE DETECTOR

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