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PTN3300A

DVI/HDMI level shifter with inverting 1.1 V HPD

Rev. 01 — 30 June 2008

Product data sheet

1. General description

The PTN3300A is a high-speed level shifter device which converts four lanes of low-swing

AC-coupled differential input signals to DVI and HDMI compliant open-drain

current-steering differential output signals, up to 2.25 Gbit/s per lane. Each of these lanes

provides a level-shifting differential buffer to translate from low-swing AC-coupled

differential signaling on the source side, to TMDS-type DC-coupled differential

current-mode signaling terminated into 50 Ω to 3.3 V on the sink side. Additionally, the

PTN3300A provides a single-ended active inverting buffer for voltage translation of the

HPD signal from 5 V on the sink side to 1.1 V on the source side and provides a channel

for level shifting of the DDC channel (consisting of a clock and a data line) between 3.3 V

source-side and 5 V sink-side. The DDC channel is implemented using pass gate

technology allowing level shifting as well as disablement (isolation between source and

sink) of the clock and data lines.

The low-swing AC-coupled differential input signals to the PTN3300A typically come from

a display source with multi-mode I/O, which supports multiple display standards, e.g.,

DisplayPort, HDMI and DVI. While the input differential signals are conﬁgured to carry DVI

or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0

speciﬁcation or HDMI v1.3a speciﬁcation. By using PTN3300A, chip set vendors are able

to implement such reconﬁgurable I/Os on multi-mode display source devices, allowing the

support of multiple display standards while keeping the number of chip set I/O pins low.

See Figure 1.

The PTN3300A main high-speed differential lanes feature low-swing self-biasing

differential inputs which are compliant to the electrical speciﬁcations of DisplayPort

Standard v1.1 and/or PCI Express Standard v1.1, and open-drain current-steering

differential outputs compliant to DVI v1.0 and HDMI V1.3a electrical speciﬁcations. The

PTN3300A also supports power-saving modes in order to minimize current consumption

when no display is active or connected.

The PTN3300A supports level translation functions and features supporting DVI and

HDMI. It is identical to the PTN3300B except that the HPD_SOURCE_N output is the

logic inverse function of input HPD_SINK, level shifted to 1.1 V. For a fully-featured

HDMI/DVI level shifter function that supports active buffering of the DDC lines and HDMI

dongle detect, the PTN3301 should be used.

PTN3300A is powered from a single 3.3 V power supply consuming a small amount of

power (120 mW typ.) and is offered in two different 48-terminal HWQFN packages, one

laminate based (no terminals visible from edge of the package), and one leadframe-based

(terminals visible from edge of the package).

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

MULTI-MODE DISPLAY SOURCE

OE_N

PTN3300A

reconfigurable I/Os

PCIe PHY ELECTRICAL

AC-coupled

differential pair

TMDS data

OUT_D4+

PCIe

output buffer

TMDS

coded

data

OUT_D4−

TX

FF

IN_D4+

DATA LANE

IN_D4−

TX

AC-coupled

differential pair

TMDS data

OUT_D3+

PCIe

output buffer

TMDS

coded

data

OUT_D3−

TX

FF

IN_D3+

DATA LANE

IN_D3−

TX

AC-coupled

differential pair

TMDS data

OUT_D2+

PCIe

output buffer

TMDS

coded

data

OUT_D2−

TX

FF

IN_D2+

DATA LANE

IN_D2−

TX

OUT_D1+

AC-coupled

differential pair

clock

PCIe

output buffer

TMDS

clock

pattern

OUT_D1−

TX

FF

IN_D1+

CLOCK LANE

IN_D1−

TX

0 V to 5 V

0 V to 1.1 V

3.3 V

HPD_SOURCE_N HPD_SINK

DDC_EN

(0 V to 3.3 V)

3.3 V

5 V

SCL_SOURCE

SDA_SOURCE

SCL_SINK

SDA_SINK

3.3 V

DDC I/O

2

(I C-bus)

CONFIGURATION

002aad645

Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1].

Fig 1. Typical application system diagram

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

2 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

2. Features

2.1 High-speed TMDS level shifting

I Converts four lanes of low-swing AC-coupled differential input signals to DVI and HDMI

compliant open-drain current-steering differential output signals

I TMDS level shifting operation up to 2.25 Gbit/s per lane (225 MHz character clock)

I Integrated 50 Ω termination resistors for self-biasing differential inputs

I Back-current safe outputs to disallow current when device power is off and monitor is

on

I Disable feature to turn off TMDS inputs and outputs and to enter low-power state

2.2 DDC level shifting

I Integrated DDC level shifting (3.3 V source to 5 V sink side)

I 0 Hz to 400 kHz clock frequency

I Back-power safe to disallow backdrive current when power is off or when DDC is not

enabled

2.3 HPD level shifting

I HPD inverting level shift from 0 V on the sink side to 1.1 V on the source side, or from

5 V on the sink side to 0 V on the source side

I Integrated 200 kΩ pull-down resistor on HPD sink input guarantees ‘input LOW’ when

no display is plugged in

2.4 General

I Power supply 3.3 V ± 10 %

I ESD resilience to 3.5 kV HBM, 1 kV CDM

I Power-saving modes by source-side disablement (using output enable) as well as

sink-side detection (using HPD)

I Back-current-safe design on all sink-side terminals

I Transparent operation: no re-timing or software conﬁguration required

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

PTN3300AHF

PTN3300AHF2

HWQFN48R

plastic thermal enhanced very very thin quad ﬂat package; no leads;

48 terminals; resin based; body 7 × 7 × 0.7 mm

SOT1031-2

HWQFN48

plastic thermal enhanced very very thin quad ﬂat package; no leads;

SOT1074-1

48 terminals; body 7 × 7 × 0.65 mm

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

3 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

4. Functional diagram

OE_N

PTN3300A

input bias

enable

OUT_D4+

OUT_D4−

50 Ω

IN_D4+

IN_D4−

enable

input bias

enable

OUT_D3+

OUT_D3−

50 Ω

IN_D3+

IN_D3−

input bias

OUT_D2+

OUT_D2−

50 Ω

IN_D2+

IN_D2−

input bias

OUT_D1+

OUT_D1−

50 Ω

IN_D1+

IN_D1−

HPD level shifter

DDC level shifter

HPD_SOURCE_N

(0 V to 1.1 V)

HPD_SINK

(0 V to 5 V)

200 kΩ

DDC_EN (0 V to 3.3 V)

SCL_SOURCE

SCL_SINK

SDA_SINK

SDA_SOURCE

002aad646

Fig 2. Functional diagram of PTN3300A

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

4 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

5. Pinning information

5.1 Pinning

terminal 1

index area

1

2

36

35

34

33

32

31

30

29

28

27

26

25

GND

n.c.

V

DD

3

n.c.

4

V

DD

5

GND

DDC_EN

GND

6

REXT

PTN3300AHF

7

HPD_SOURCE_N

SDA_SOURCE

SCL_SOURCE

n.c.

HPD_SINK

SDA_SINK

SCL_SINK

GND

8

9

10

11

12

V

DD

GND

OE_N

002aad647

Transparent top view

HWQFN48R package supply ground is connected to both GND pins and exposed center pad.

GND pins must be connected to supply ground for proper device operation. For enhanced thermal,

electrical, and board level performance, the exposed pad needs to be soldered to the board using

a corresponding thermal pad on the board and for proper heat conduction through the board,

thermal vias need to be incorporated in the PCB in the thermal pad region.

Fig 3. Pin conﬁguration for HWQFN48R

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

5 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

terminal 1

index area

GND

1

2

3

4

5

6

7

8

9

36 GND

35 n.c.

34 n.c.

V

DD

n.c.

33

V

DD

GND

32 DDC_EN

31 GND

REXT

PTN3300AHF2

HPD_SOURCE_N

SDA_SOURCE

SCL_SOURCE

30 HPD_SINK

29 SDA_SINK

28 SCL_SINK

27 GND

n.c. 10

11

V

26 V

DD

GND 12

25 OE_N

002aad648

Transparent top view

HWQFN48 package supply ground is connected to both GND pins and exposed center pad. GND

pins must be connected to supply ground for proper device operation. For enhanced thermal,

electrical, and board level performance, the exposed pad needs to be soldered to the board using

a corresponding thermal pad on the board and for proper heat conduction through the board,

thermal vias need to be incorporated in the PCB in the thermal pad region.

Fig 4. Pin conﬁguration for HWQFN48

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

6 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

5.2 Pin description

Table 2.

Symbol

Pin description

Type

Description

OE_N, IN_Dx and OUT_Dx signals

OE_N

25

3.3 V low-voltage

CMOS

Output Enable and power saving function for high-speed differential

level shifter path.

single-ended input

When OE_N = HIGH:

IN_Dx termination = high-impedance

OUT_Dx outputs = high-impedance; zero output current

When OE_N = LOW:

IN_Dx termination = 50 Ω

OUT_Dx outputs = active

IN_D4+

IN_D4−

IN_D3+

IN_D3−

IN_D2+

IN_D2−

IN_D1+

IN_D1−

48

47

45

44

42

41

39

38

Self-biasing

differential input

Low-swing differential input from display source with PCI Express

electrical signalling. IN_D4+ makes a differential pair with IN_D4−.

The input to this pin must be AC coupled externally.

Self-biasing

differential input

Low-swing differential input from display source with PCI Express

electrical signalling. IN_D4− makes a differential pair with IN_D4+.

The input to this pin must be AC coupled externally.

Self-biasing

differential input

Low-swing differential input from display source with PCI Express

electrical signalling. IN_D3+ makes a differential pair with IN_D3−.

The input to this pin must be AC coupled externally.

Self-biasing

differential input

Low-swing differential input from display source with PCI Express

electrical signalling. IN_D3− makes a differential pair with IN_D3+.

The input to this pin must be AC coupled externally.

Self-biasing

differential input

Low-swing differential input from display source with PCI Express

electrical signalling. IN_D2+ makes a differential pair with IN_D2−.

The input to this pin must be AC coupled externally.

Self-biasing

differential input

Low-swing differential input from display source with PCI Express

electrical signalling. IN_D2− makes a differential pair with IN_D2+.

The input to this pin must be AC coupled externally.

Self-biasing

differential input

Low-swing differential input from display source with PCI Express

electrical signalling. IN_D1+ makes a differential pair with IN_D1−.

The input to this pin must be AC coupled externally.

Self-biasing

differential input

Low-swing differential input from display source with PCI Express

electrical signalling. IN_D1− makes a differential pair with IN_D1+.

The input to this pin must be AC coupled externally.

OUT_D4+

OUT_D4−

OUT_D3+

OUT_D3−

OUT_D2+

OUT_D2−

13

14

16

17

19

20

TMDS differential

output

DVI and HDMI compliant TMDS output. OUT_D4+ makes a

differential pair with OUT_D4−. OUT_D4+ is in phase with IN_D4+.

TMDS differential

output

DVI and HDMI compliant TMDS output. OUT_D4− makes a

differential pair with OUT_D4+. OUT_D4− is in phase with IN_D4−.

TMDS differential

output

DVI and HDMI compliant TMDS output. OUT_D3+ makes a

differential pair with OUT_D3−. OUT_D3+ is in phase with IN_D3+.

TMDS differential

output

DVI and HDMI compliant TMDS output. OUT_D3− makes a

differential pair with OUT_D3+. OUT_D3− is in phase with IN_D3−.

TMDS differential

output

DVI and HDMI compliant TMDS output. OUT_D2+ makes a

differential pair with OUT_D2−. OUT_D2+ is in phase with IN_D2+.

TMDS differential

output

DVI and HDMI compliant TMDS output. OUT_D2− makes a

differential pair with OUT_D2+. OUT_D2− is in phase with IN_D2−.

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

7 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

Table 2.

Symbol

OUT_D1+

Pin description …continued

Type

Description

22

TMDS differential

output

DVI and HDMI compliant TMDS output. OUT_D1+ makes a

differential pair with OUT_D1−. OUT_D1+ is in phase with IN_D1+.

OUT_D1−

23

TMDS differential

output

DVI and HDMI compliant TMDS output. OUT_D1− makes a

differential pair with OUT_D1+. OUT_D1− is in phase with IN_D1−.

HPD and DDC signals

HPD_SINK

30

5 V CMOS

0 V to 5 V (nominal) input signal. This signal comes from the DVI or

single-ended input HDMI sink. A HIGH value indicates that the DVI or HDMI sink is

connected; a LOW value indicates that the sink is disconnected.

HPD_SINK is pulled down by an integrated 200 kΩ pull-down resistor.

A LOW input level on this pin will automatically put the PTN3300A in

Standby mode for lowest power consumption.

HPD_SOURCE_

N

7

1.1 V CMOS

single-ended

output

0 V to 1.1 V (nominal) output signal. This is the level-shifted

logic-inverted version of the HPD_SINK signal.

SCL_SOURCE

SDA_SOURCE

SCL_SINK

9

single-ended 3.3 V 3.3 V source-side DDC clock I/O. Pulled up by external termination to

DDC I/O pass gate 3.3 V.

8

single-ended 3.3 V 3.3 V source-side DDC data I/O. Pulled up by external termination to

DDC I/O pass gate 3.3 V.

28

29

32

single-ended 5 V

5 V sink-side DDC clock I/O. Pulled up by external termination to 5 V.

DDC I/O pass gate

SDA_SINK

single-ended 5 V

5 V sink-side DDC data I/O. Pulled up by external termination to 5 V.

DDC I/O pass gate

DDC_EN

3.3 V CMOS input Enables the DDC level shifter path.

When DDC_EN = LOW, DDC level shifter is disabled.

When DDC_EN = HIGH, DDC level shifter are enabled.

Note that HPD_SINK needs to be HIGH for the DDC channel to be

enabled.

Supply and ground

V_DD

2, 11, 15, 3.3 V DC supply

21, 26, 33,

Supply voltage; 3.3 V ± 10 %.

40, 46

GND^[1]

1, 5, 12,

ground

Supply ground. All ground pins must be connected to ground for

proper operation.

18, 24, 27,

31, 36, 37,

43

Feature control signals

REXT

6

analog I/O

Current sense port used to provide an accurate current reference for

the differential outputs OUT_Dx. For best output voltage swing

accuracy, use of a 10 kΩ resistor (1 % tolerance) from this terminal to

GND is recommended. May also be left open-circuit or tied to either

V_DDor GND.

Miscellaneous

n.c.

3, 4, 10,

34, 35

no connection to

the die

Not connected. May be left open-circuit or tied to GND or V_DDeither

directly or via a resistor.

[1] HWQFN48R and HWQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins must be

connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed

pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the

board, thermal vias need to be incorporated in the PCB in the thermal pad region.

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

8 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

6. Functional description

Refer to Figure 2 “Functional diagram of PTN3300A”.

The PTN3300A level shifts four lanes of low-swing AC-coupled differential input signals to

DVI or HDMI compliant open-drain current-steering differential output signals, up to

2.25 Gbit/s per lane. It has integrated 50 Ω termination resistors for AC-coupled

differential input signals. An enable signal OE_N can be used to turn off the TMDS inputs

and outputs, thereby minimizing power consumption. The TMDS outputs are back-power

safe to disallow current ﬂow from a powered sink while the PTN3300A is unpowered.

The PTN3300A's DDC level-shifter allows 3.3 V source-side termination and 5 V sink-side

termination. The PTN3300A offers the back-power safe feature to disallow backdrive

current from the DDC clock and data lines when power is off or when DDC is not enabled.

An enable signal DCC_EN enables the level shifter block.

The PTN3300A also provides voltage translation for the Hot Plug Detect (HPD) signal

from 0 V/5 V on the sink side, inverting and level-shifting to 1.1 V/0 V on the source side.

PTN3300A also automatically goes into low power mode when the sink is not connected

(HPD_SINK is LOW).

The PTN3300A does not re-time any data. It contains no state machines. No inputs or

outputs of the device are latched or clocked. Because the PTN3300A acts as a

transparent level shifter, no reset is required.

6.1 Flexible and power-efﬁcient enable and disable features

PTN3300A offers different ways to enable or disable functionality, using the Output Enable

(OE_N), Hot Plug Detect (HPD_SINK) and DDC Enable (DDC_EN) inputs. Whenever the

PTN3300A is disabled using HPD_SINK or OE_N, the device will be in Standby mode and

power consumption will be minimal; otherwise the PTN3300A will be in Active mode and

power consumption will be nominal. These three inputs each affect the operation of

PTN3300A differently: OE_N affects only the TMDS channels, DDC_EN affects only the

DDC channel, and HPD_SINK affects both TMDS and DDC channels. The following

sections and truth table describe their detailed operation.

6.1.1 Hot plug detect with power-saving feature

The HPD channel of PTN3300A in fact has a dual function: as a level-shifting inverting

buffer to pass the HPD logic signal from the display sink device (via input HPD_SINK) on

to the display source device (via output HPD_SOURCE_N), as well as a detection input

for determining when the PTN3300A will go into Standby mode to save power

consumption.

The PTN3300A will automatically disable both the TMDS and DDC channels when the

HPD input indicates that no display is connected (indicated by HPD_SINK = LOW), upon

which power consumption is minimized. The power-down behavior in HPD power-saving

mode is identical to the active disablement using both the OE_N input and the DDC_EN

input.

The logic state of the HPD_SOURCE_N output always follows the inverse logic state of

the HPD_SINK input, regardless of whether the device is in Active or Standby mode.

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

9 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

6.1.2 Output Enable function (OE_N)

When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully

functional provided that HPD_SINK input is HIGH. Input termination resistors are enabled

and the internal bias circuits are turned on.

When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a

high-impedance state and drive zero output current. The IN_Dx input buffers are disabled

and IN_Dx termination is disabled. Internal bias circuits for the differential inputs and

outputs are turned off. Power consumption is minimized.

Remark: Note that OE_N has no inﬂuence on the HPD_SINK input, HPD_SOURCE_N

output, or the SCL and SDA level shifters. OE_N only affects the high-speed TMDS

channel.

6.1.3 DDC channel enable function (DDC_EN)

The DDC_EN pin is active HIGH and can be used to isolate a badly behaved slave. When

DDC_EN is LOW, the DDC channel is turned off. The DDC_EN input should never change

state during an I²C-bus operation. Note that disabling DDC_EN during a bus operation will

hang the bus, while enabling DDC_EN during bus trafﬁc would corrupt the I²C-bus

operation. Hence, DDC_EN should only be toggled while the bus is idle. (See I²C-bus

speciﬁcation).

6.1.4 Enable/disable truth table

Table 3.

HPD_SINK, OE_N and DDC_EN enabling and power saving functions truth table

Inputs

Channels

Mode

HPD_SINK OE_N

DDC_EN IN_Dx

[3]

OUT_Dx^[4]

DDC^[5]

HPD_SOURCE_N

[6]

[1]

[2]

LOW

X

high-impedance

high-impedance; high-impedance HIGH

Standby

zero output

current

HIGH

LOW

HIGH

LOW

HIGH

LOW

50 Ω termination enabled

to V_RX(bias)

high-impedance LOW

enabled LOW

Active

50 Ω termination enabled

to V_RX(bias)

Active

high-impedance

high-impedance; high-impedance LOW

Standby

zero output

current

HIGH

high-impedance

high-impedance; enabled

zero output

current

LOW

Standby

with DDC

channel

enabled

[1] A LOW level on input HPD_SINK disables both the TMDS and DDC channels.

[2] A HIGH level on input OE_N disables only the TMDS channels.

[3] A LOW level on input DDC_EN disables only the DDC channel.

[4] OUT_Dx channels ‘enabled’ means outputs OUT_Dx toggling in accordance with IN_Dx differential input voltage switching.

[5] DDC channel ‘enabled’ means SDA_SINK is connected to SDA_SOURCE and SCL_SINK is connected to SCL_SOURCE.

[6] The HPD_SOURCE_N output logic state follows the inverse of the HPD_SINK input logic state regardless of Active or Standby mode.

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

10 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

6.2 Analog current reference

The REXT pin (pin 6) is an analog current sense port used to provide an accurate current

reference for the differential outputs OUT_Dx. For best output voltage swing accuracy, use

of a 10 kΩ resistor (1 % tolerance) connected between this terminal and GND is

recommended.

If an external 10 kΩ ± 1 % resistor is not used, this pin can be left open-circuit, or

connected to GND or V_DD, either directly (0 Ω) or using pull-up or pull-down resistors of

value less than 10 kΩ. In any of these cases, the output will function normally but at

reduced accuracy over voltage and temperature of the following parameters: output levels

(V_OL), differential output voltage swing, and rise and fall time accuracy.

6.3 Backdrive current protection

The PTN3300A is designed for backdrive prevention on all sink-side terminals. This

supports user scenarios where the display is connected and powered, but the PTN3300A

is unpowered. In these cases, the PTN3300A will sink no more than a negligible amount

of leakage current, and will block the display (sink) termination network from driving the

power supply of the PTN3300A or that of the inactive DVI or HDMI source.

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

11 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

Parameter

Conditions

Min

−0.3

−65

-

Max

Unit

V

supply voltage

input voltage

+4.6

V_I

3.3 V CMOS inputs

5.0 V CMOS inputs

V_DD+ 0.5

6.0

V

T_stg

storage temperature

+150

3500

1000

°C

V

[1]

[2]

V_esd

electrostatic discharge

voltage

HBM

CDM

-

V

[1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -

Component level; Electrostatic Discharge Association, Rome, NY, USA.

[2] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device

Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.

8. Recommended operating conditions

Table 5.

Recommended operating conditions

Symbol Parameter

Conditions

Min

3.0

0

Typ

Max

3.6

5.5

-

Unit

V

V_DD

V_I

supply voltage

input voltage

3.3

3.3 V CMOS inputs

5.0 V CMOS inputs

-

V

0

-

V

[1]

V_I(AV)

average input voltage DC value at IN_Dn+,

-

0

V

IN_Dn− inputs

R_ref(ext)

external reference

resistance^[2]

connected between

REXT pin (pin 6) and

GND; ± 1 %

-

10

-

kΩ

°C

T_amb

ambient temperature operating in free air

−40

+85

[1] Input signals to these pins must be AC-coupled.

[2] Operation without external reference resistor is possible but will result in reduced output voltage swing

accuracy. For details, see Section 6.2.

8.1 Current consumption

Table 6.

Symbol Parameter

I_DDsupply current

Current consumption

Conditions

Min

Typ

Max

Unit

OE_N = 0 and HPD_SINK = 1;

10

35

50

mA

Active mode

OE_N = 1 or HPD_SINK = 0;

-

5

50

µA

Standby mode

PTN3300A_1

Product data sheet

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12 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

9. Characteristics

9.1 Differential inputs

Table 7.

Symbol

UI

Differential input characteristics for IN_Dx signals

Parameter

Conditions

Min

400

0.175

0.8

Typ

Max

4000

1.200

-

Unit

ps

unit interval^[1]

-

[2]

[3]

V_{RX_DIFFp-p}differential input peak-to-peak voltage

V

T_{RX_EYE}

receiver eye time

minimum eye width at

IN_Dx input pair

UI

[4]

V_i(cm)M(AC)

peak common-mode input voltage (AC) includes all frequencies

above 30 kHz

-

100

mV

Z_{RX_DC}

DC input impedance

40

50

60

Ω

[5]

[6]

V_RX(bias)

bias receiver voltage

voltage at IN_Dx when

IN_Dx = open circuit

1.0

1.2

1.4

V

Z_I(se)

single-ended input impedance

inputs in high-impedance

state

100

-

kΩ

[1] UI (unit interval) = t_bit(bit time).

[2] UI is determined by the display mode. Nominal bit rate ranges from 250 Mbit/s to 2.25 Gbit/s per lane. Nominal UI at

2.25 Gbit/s = 444 ps. 400 ps = 444 ps − 10 %.

[3] V_{RX_DIFFp-p}= 2 × |V_{RX_D+}− V_{RX_D−}|. Applies to IN_Dx signals.

[4] V_i(cm)M(AC)= |V_{RX_D+}+ V_{RX_D−}| / 2 − V_RX(cm)

.

V_RX(cm)= DC (avg) of |V_{RX_D+}+ V_{RX_D−}| / 2.

[5] Intended to limit power-up stress on source side PCIe output buffers.

[6] Differential inputs will switch to a high-impedance state when OE_N is LOW.

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

13 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

9.2 Differential outputs

The level shifter’s differential outputs are designed to meet DVI version 1.0 and

HDMI v1.3a speciﬁcations.

Table 8.

Differential output characteristics for OUT_Dx signals

Symbol Parameter

Conditions

Min

Typ

Max

Unit

[1]

[2]

[3]

V_OH(se)

V_OL(se)

∆V_O(se)

single-ended HIGH-level

output voltage

V

_TT− 0.01 V_TT

V_TT+ 0.01 V

single-ended LOW-level

output voltage

V

_TT− 0.60 V_TT− 0.50 V_TT− 0.40 V

single-ended output voltage logic 1 and logic 0 state applied

450

500

600

mV

variation

respectively to differential inputs

IN_Dn; R_ref(ext)connected.

See Table 5

I_OZ

t_r

off-state output current

rise time

single-ended

20 % to 80 %

80 % to 20 %

intra-pair

-

10

µA

ps

[4]

[5]

[6]

[7]

75

-

180

10

t_f

fall time

t_sk

skew time

inter-pair

-

250

7.4

t_jit

jitter time

jitter contribution

-

[1] V_TTis the DC termination voltage in the DVI or HDMI sink. V_TTis nominally 3.3 V. Termination resistance is nominally 50 Ω.

[2] The open-drain output pulls down from V_TT

.

[3] Swing down from TMDS termination voltage (3.3 V ± 10 %).

[4] Maximum rise/fall time at 2.25 Gbit/s = 444 ps. 400 ps = 444 ps − 15 %.

[5] This differential skew budget is in addition to the skew presented between IN_D+ and IN_D− paired input pins.

[6] This lane-to-lane skew budget is in addition to skew between differential input pairs.

[7] Jitter budget for differential signals as they pass through the level shifter. 7.4 ps = 0.02 UI at 1.65 Gbit/s.

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

14 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

9.3 HPD_SINK input, HPD_SOURCE_N output

Table 9.

Symbol

V_IH

HPD characteristics

Parameter

Conditions

HPD_SINK

Min

2.0

0

Typ

Max

5.3

0.8

10

Unit

V

[1]

[2]

HIGH-level input voltage

LOW-level input voltage

input leakage current

HIGH-level output voltage

5.0

V_IL

-

V

I_LI

-

µA

V

V_OH

HPD_SOURCE_N; I_OH= 100 µA;

0.7

1.1

HPD_SINK = LOW

V_OL

t_PD

t_t

LOW-level output voltage

propagation delay

transition time

HPD_SOURCE_N; I_OL= 100 µA;

HPD_SINK = HIGH

0

-

0.2

200

20

V

[3]

[4]

[5]

from HPD_SINK to HPD_SOURCE_N;

50 % to 50 %; C_L= 10 pF

-

ns

kΩ

HPD_SOURCE_N rise/fall;

10 % to 90 %; C_L= 10 pF

1

-

R_pd

pull-down resistance

HPD_SINK input pull-down resistor

100

200

300

[1] Low-speed input changes state on cable plug/unplug.

[2] Measured with HPD_SINK at V_IHmaximum and V_ILminimum.

[3] Time from HPD_SINK changing state to HPD_SOURCE_N changing state. Includes HPD_SOURCE_N rise/fall time.

[4] Time required to transition from V_OHto V_OLor from V_OLto V_OH

.

[5] Guarantees HPD_SINK is LOW when no display is plugged in.

9.4 OE_N and DDC_EN inputs

Table 10. OE_N and DDC_EN input characteristics

Symbol

V_IH

Parameter

Conditions

Min

Typ

Max

-

Unit

V

HIGH-level input voltage

LOW-level input voltage

input leakage current

2.0

-

V_IL

-

0.8

10

V

[1]

I_LI

OE_N pin

µA

[1] Measured with input at V_IHmaximum and V_ILminimum.

9.5 DDC characteristics

Table 11. DDC characteristics

Symbol Parameter

f_clkclock frequency

Conditions

Min

Typ

Max

Unit

SCL_SOURCE, SDA_SOURCE, SCL_SINK,

SDA_SINK

-

400

kHz

ON state (DDC_EN = HIGH and HPD_SINK = HIGH)

R_ON

ON resistance

pass gate in ON state; I_O= 15 mA; V_O= 0.4 V

-

7

30

Ω

V

V_O(sw)

switch output voltage

SOURCE side; V_I= 3.3 V; I_O= −100 µA

SINK side; V_I= 5.0 V; I_O= −100 µA

V_I= 3.3 V; I_O= −100 µA

1.8

-

2.1

5

2.4

10

V

C_io

input/output capacitance

pF

OFF state (DDC_EN = LOW)

I_LI

input leakage current

SOURCE side; 0 V < V_I< 3.3 V

SINK side; 0 V < V_I< 5.0 V

V_I= 3.3 V; I_O= −100 µA

−1

-

+1

5

µA

pF

-

C_io

input/output capacitance

1

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

15 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

10. Package outline

HWQFN48R: plastic thermal enhanced very very thin quad flat package; no leads

48 terminals; resin based; body 7 x 7 x 0.7 mm

SOT1031-2

D

B

A

terminal 1

index area

E

A

detail X

e

1

C

e

M

v

C A

C

B

b

1/2 e

L

1

y

w

C

1

13

24

L

25

12

e

E

e

2

h

1/2 e

1

36

terminal 1

index area

48

37

D

h

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT

A

b

D

h

E

e

1

e

2

L

v

w

y

1

h

1

max 0.80 0.27

nom 0.70 0.25

7.1

7.0

6.9

5.35

5.25

5.15

7.1

7.0

6.9

5.35

5.25

5.15

0.42 0.10

0.40 0.05

0.38 0.00

mm

0.5

5.5

0.1

0.05 0.05

0.1

min

0.65 0.23

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

- - -

JEDEC

JEITA

08-03-06

08-03-26

SOT1031-2

- - -

Fig 5. Package outline SOT1031-2 (HWQFN48R)

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

16 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

HWQFN48: plastic thermal enhanced very very thin quad flat package; no leads;

48 terminals; body 7 x 7 x 0.65 mm

SOT1074-1

D

B

A

terminal 1

index area

E

A

1

c

detail X

e

1

1/2 e

C

M

v

C A

B

e

b

L

y

C

1

y

w

C

13

24

12

25

e

E

e

2

h

1/2 e

1

36

terminal 1

index area

48

37

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

A

1

b

c

D

h

E

e

1

e

2

L

v

w

y

1

h

max 0.80 0.05 0.30

nom 0.65 0.02 0.21

7.1

7.0

6.9

5.40

5.25

5.10

7.1

7.0

6.9

5.40

5.25

5.10

0.5

0.4

0.3

mm

0.2

0.5

5.5

0.1

0.05 0.05

0.1

min

0.60 0.00 0.18

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

- - -

08-03-06

08-03-14

SOT1074-1

- - -

Fig 6. Package outline SOT1074-1 (HWQFN48)

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

17 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

11. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

11.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

11.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

11.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

PTN3300A_1

Product data sheet

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18 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

11.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 7) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 12 and 13

Table 12. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 13. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 7.

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

19 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 7. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

12. Abbreviations

Table 14. Abbreviations

Acronym

CDM

CEC

Description

Charged-Device Model

Consumer Electronics Control

Data Display Channel

DDC

DVI

Digital Visual Interface

EMI

ElectroMagnetic Interference

ElectroStatic Discharge

ESD

HBM

HDMI

HPD

Human Body Model

High-Deﬁnition Multimedia Interface

Hot Plug Detect

I²C-bus

Inter-Integrated Circuit bus

Input/Output

I/O

NMOS

TMDS

VESA

Negative-channel Metal-Oxide Semiconductor

Transition Minimized Differential Signaling

Video Electronics Standards Association

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

20 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

13. Revision history

Table 15. Revision history

Document ID

Release date

20080630

Data sheet status

Change notice

Supersedes

PTN3300A_1

Product data sheet

-

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

21 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

14. Legal information

14.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

14.2 Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

14.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

14.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

15. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

PTN3300A_1

Product data sheet

Rev. 01 — 30 June 2008

22 of 23

PTN3300A

NXP Semiconductors

DVI/HDMI level shifter with inverting 1.1 V HPD

16. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

High-speed TMDS level shifting . . . . . . . . . . . . 3

DDC level shifting . . . . . . . . . . . . . . . . . . . . . . . 3

HPD level shifting . . . . . . . . . . . . . . . . . . . . . . . 3

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1

2.2

2.3

2.4

3

4

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 4

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

6

6.1

Functional description . . . . . . . . . . . . . . . . . . . 9

Flexible and power-efﬁcient enable and

disable features. . . . . . . . . . . . . . . . . . . . . . . . . 9

Hot plug detect with power-saving feature . . . . 9

Output Enable function (OE_N) . . . . . . . . . . . 10

DDC channel enable function (DDC_EN). . . . 10

Enable/disable truth table . . . . . . . . . . . . . . . . 10

Analog current reference . . . . . . . . . . . . . . . . 11

Backdrive current protection. . . . . . . . . . . . . . 11

6.1.1

6.1.2

6.1.3

6.1.4

6.2

6.3

7

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12

Recommended operating conditions. . . . . . . 12

Current consumption . . . . . . . . . . . . . . . . . . . 12

8

8.1

9

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 13

Differential inputs . . . . . . . . . . . . . . . . . . . . . . 13

Differential outputs . . . . . . . . . . . . . . . . . . . . . 14

HPD_SINK input, HPD_SOURCE_N output . 15

OE_N and DDC_EN inputs. . . . . . . . . . . . . . . 15

DDC characteristics . . . . . . . . . . . . . . . . . . . . 15

9.1

9.2

9.3

9.4

9.5

10

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

11

Soldering of SMD packages . . . . . . . . . . . . . . 18

Introduction to soldering . . . . . . . . . . . . . . . . . 18

Wave and reﬂow soldering . . . . . . . . . . . . . . . 18

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 19

11.1

11.2

11.3

11.4

12

13

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21

14

Legal information. . . . . . . . . . . . . . . . . . . . . . . 22

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

14.1

14.2

14.3

14.4

15

16

Contact information. . . . . . . . . . . . . . . . . . . . . 22

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 30 June 2008

Document identifier: PTN3300A_1

电子百科

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产品型号PTN3300AHF的概述

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