QL12X16B-2PF100C全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

QL12X16B

pASIC^®1 Family

Very-High-Speed CMOS FPGA

Rev C

pASIC

HIGHLIGHTS

Very High Speed – ViaLink metal-to-metal programmable–via

antifuse technology, allows counter speeds over 150 MHz and logic

cell delays of under 2 ns.

High Usable Density

–

A 12-by-16 array of 192 logic cells

provides 2,000 usable ASIC gates (4,000 PLD gates) in 68-pin and

84-pin PLCC, 84-pin CPGA and 100-pin TQFP packages.

…2,000

usable ASIC gates,

88 I/O pins

Low-Power, High-Output Drive

– Standby current typically 2

mA. A 16-bit counter operating at 100 MHz consumes less than 50

mA. Minimum IOL of 12 mA and IOH of 8 mA

Low-Cost, Easy-to-Use Design Tools

–

Designs entered and

4

simulated using QuickLogic's new QuickWorks development

environment, or with third-party CAE tools including Viewlogic,

Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place

and route on PC and workstation platforms using QuickLogic

software.

QL12x16B

Block Diagram

192 Logic Cells

=

Up to 80 prog. I/O cells, 6 Input high-drive cells, 2 Input/Clk (high-drive) cells

4-13

QL12x16B

PRODUCT

SUMMARY

The QL12x16B is a member of the pASIC 1 Family of very-high-speed

CMOS user-programmable ASIC devices. The 192 logic cell field-

programmable gate array (FPGA) offers 2,000 usable ASIC gates (4,000

usable PLD gates) of high-performance general-purpose logic in a wide

variety of package configurations.

Low-impedance, metal-to-metal, ViaLink interconnect technology

provides nonvolatile custom logic capable of operating above 150 MHz.

Logic cell delays under 2 ns, combined with input delays of under 1.5 ns

and output delays under 3 ns, permit high-density programmable devices

to be used with today’s fastest microprocessors and DSPs.

Designs can be entered using QuickLogic’s QuickWorks Toolkit or most

populart third-party CAE tools. QuickWorks combines Verilog/VHDL

design entry and simulation tools with device-specific place & route and

programming software. Ample on-chip routing channels allow fast, fully

automatic place and route of designs using up to 100% of the logic and

I/O cells, while maintaining fixed pin-outs.

FEATURES

Total of 88 I/O pins

– 80 Bidirectional Input/Output pins

– 6 Dedicated Input/High-Drive pins

– 2 Clock/Dedicated input pins with fanout-independent, low-skew

clock networks

Input + logic cell + output delays under 6 ns

Chip-to-chip operating frequencies up to 110 MHz

Internal state machine frequencies up to 150 MHz

Clock skew < 0.5 ns

Input hysteresis provides high noise immunity

Built-in scan path permits 100% factory testing of logic and I/O cells

and functional testing with Automatic Test Vector Generation

(ATVG) software after programming

Available in 68-pin and 84-pin PLCC, 84-pin CPGA and 100-pin

TQFP packages

68-pin PLCC compatible with QL8x12B

84-pin PLCC compatible with QL16x24B

100-pin TQFP compatible with QL8x12B and QL16x24B

0.65µ CMOS process with ViaLink programming technology

4-14

QL12x16B

Pinout

Diagram

68-pin PLCC

4

Pinout

Diagram

84-pin PLCC

Pins identified I/SCLK, SM, SO and SI are used during scan path testing operation.

4-15

QL12x16B

Pinout Diagram

84-pin CPGA

M

CPGA 84 Function/Connector Pin Table

B10

B9

A10

A9

B8

A8

A7

C7

A6

B7

C6

B6

B5

C5

A5

A4

B4

A3

A2

B3

A1

FUNC

B2

C2

B1

C1

D2

D1

E1

E3

E2

F1

F2

F3

G1

G3

G2

H1

H2

J1

FUNC

IO

K2

K3

L2

FUNC

IO

K10

J10

K11

J11

H10

H11

G11

G9

FUNC

IO

L3

IO

K4

L4

IO

L5

IO

GND

IO

J5

GND

IO

GND

IO

L6

G10

F11

F10

F9

I/(SCLK)

IO

K5

J6

I/(SI)

I/CLK

I

IO

I/CLK/(SM)

IO

I(P)

I

IO

K6

K7

J7

IO

I/(SO)

VCC

IO

E11

E9

IO

VCC

IO

VCC

IO

VCC

IO

L7

E10

D11

D10

C11

B11

C10

A11

IO

L8

IO

K8

L9

IO

K1

J2

IO

L10

K9

L11

IO

L1

IO

4-16

QL12x16B

Pinout Diagram

100-pin TQFP

4

4-17

QL12x16B

ABSOLUTE MAXIMUM RATINGS

Supply Voltage................................. –0.5 to 7.0V

Input Voltage....................... –0.5 to VCC +0.5V

ESD Pad Protection.................................. ±2000V

DC Input Current...................................... ±20 mA

Latch-up Immunity................................. ±200 mA

Storage Temperature .......–65°C to + 150°C

Lead Temperature ...................................300°C

OPERATING RANGE

Symbol

Parameter

Military

Industrial

Commercial Unit

Min

4.5

-55

Max

5.5

Min

4.5

-40

Max

5.5

85

Min

4.75

0

Max

5.25

70

VCC

TA

TC

Supply Voltage

Ambient Temperature

Case Temperature

V

°C

125

-X Speed Grade

0.4

2.75

1.67

1.43

1.35

0.46

2.55

1.55

1.33

1.25

K

Delay Factor

-0 Speed Grade

-1 Speed Grade

-2 Speed Grade

0.39

1.82

1.56

DC CHARACTERISTICS over operating range

Symbol

Parameter

Conditions

Min

Max Unit

VIH

VIL

Input HIGH Voltage

Input LOW Voltage

2.0

V

0.8

V

IOH = -4 mA

IOH = -8 mA

IOH = -10 µA

IOL = 12 mA*

IOL = 10 µA

3.7

2.4

VCC-0.1

VOH

VOL

Output HIGH Voltage

Output LOW Voltage

0.4

0.1

10

II

IOZ

CI

Input Leakage Current

3-State Output Leakage Current

Input Capacitance [1]

VI = VCC or GND

-10

µA

pF

IOS

Output Short Circuit Current [2]

VO = GND

VO = VCC

VI, VIO = VCC or GND

-10

30

-80

140

10

mA

ICC

D.C. Supply Current [3]

*IOL = 12 mA for commercial range only. IOL = 8 mA for the industrial and military ranges.

Notes:

[1] Capacitance is sample tested only. CI = 20 pF max on I/(SI).

[2] Only one output at a time. Duration should not exceed 30 seconds.

[3] Commercial temperature grade only. Maximum Icc for industrial grade is 15mA and for military grade is

20 mA. For AC conditions use the formula described in the Section 9 — Power vs Operating Frequency.

[4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified

in the Operating Range.

[5] These limits are derived from a representative selection of the slowest paths through the pASIC logic cell

including net delays. Worst case delay values for specific paths should be determined from timing analysis

of your particular design.

4-18

QL12x16B

AC CHARACTERISTICS at VCC = 5V, TA = 25°C (K = 1.00)

Logic Cell

Propagation Delays (ns)

Fanout

Symbol

Parameter

1

2

3

4

8

tPD

tSU

tH

tCLK

tCWHI

tCWLO

tSET

tRESET

tSW

Combinatorial Delay [5]

Setup Time [5]

Hold Time

Clock to Q Delay

Clock High Time

Clock Low Time

Set Delay

Reset Delay

Set Width

1.7

2.1

0.0

1.0

2.0

1.7

1.5

1.9

1.8

2.2

2.1

0.0

1.5

2.0

2.1

1.9

1.8

2.6

2.1

0.0

1.9

2.0

2.6

2.2

1.9

1.8

3.2

2.1

0.0

2.5

2.0

3.2

2.7

1.9

1.8

5.2

2.1

0.0

4.6

2.0

5.2

4.3

1.9

1.8

tRW

Reset Width

4

Input Cells

Symbol

Propagation Delays (ns) [4]

Parameter

1

2

3

4

6

8

tIN

High Drive Input Delay [6]

High Drive Input, Inverting Delay [6]

Input Delay (bidirectional pad)

Clock Buffer Delay [7]

2.4

2.5

1.4

2.7

2.0

2.5

2.6

1.9

2.8

2.0

2.6

2.7

2.2

2.8

2.0

2.7

2.8

2.9

2.0

3.0

3.1

3.7

2.9

2.0

3.3

3.4

4.6

3.0

2.0

tINI

tIO

tGCK

tGCKHI

tGCKLO

Clock Buffer Min High [7]

Clock Buffer Min Low [7]

Output Cell

Symbol

Propagation Delays (ns) [4]

Output Load Capacitance (pF)

Parameter

30

50

3.4

3.7

4.9

4.2

75

4.2

4.7

6.1

5.0

100

5.0

5.6

7.3

5.8

150

6.7

7.6

9.7

7.3

tOUTLH

tOUTHL

tPZH

tPZL

tPHZ

Output Delay Low to High

Output Delay High to Low

Output Delay Tri-state to High

Output Delay Tri-state to Low

Output Delay High to Tri-state [8]

Output Delay Low to Tri-state [8]

2.7

2.8

4.0

3.6

2.9

3.3

tPLZ

Notes:

[6] See High Drive Buffer Table for more information.

[7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half

columns used does not affect clock buffer delay.

[8] The following loads are used for tPXZ:

tPHZ

1KΩ

5 pF

1KΩ

tPLZ

5 pF

4-19

QL12x16B

High Drive Buffer

Symbol

Clock Drivers

Wired Together

Propagation Delays (ns) [4]

Parameter

Fanout

48

12

4.5

24

5.4

3.9

72

96

1

2

3

4

1

2

3

4

tIN

High Drive Input Delay

5.6

4.5

5.3

4.6

6.3

5.3

4.7

5.6

4.0

tINI

High Drive Input,

Inverting Delay

5.8

4.6

5.5

4.8

6.4

5.5

AC Performance

Propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature,

and process variation. The AC Characteristics are a design guide to provide initial timing estimates at

nominal conditions. Worst case estimates are obtained when nominal propagation delays are multiplied

by the appropriate Delay Factor, K, as specified in the Delay Factor table (Operating Range). The

effects of voltage and temperature variation are illustrated in the graphs on page 4-47, K Factor versus

Voltage and Temperature. The pASIC Development Tools incorporate data sheet AC Characteristics

into the QDIF database for pre-place-and-route timing analysis. The SpDE Delay Modeler extracts

specific timing parameters for precise path analysis or simulation results following place and route.

QL 12x16B - 1 PF100 C

ORDERING

INFORMATION

QuickLogic pASIC

device prefix

Operating Range

C = Commercial

I = Industrial

M = Military

M/883C = MIL-STD-883

pASIC device part number

B = 0.65 micron CMOS

Package Code

Speed Grade

X = quick

0 = fast

1 = faster

2 = fastest

PL68 = 68-pin PLCC

PL84 = 84-pin PLCC

CG84 = 84-pin CPGA

PF100 = 100-pin TQFP

4-20

型号:	QL12X16B-2PF100C
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	QFP
包装说明：	LFQFP, QFP100,.63SQ,20
针数：	100
Reach Compliance Code：	unknown
风险等级：	5.89
Is Samacsys：	N
其他特性：	MAX 80 I/OS
最大时钟频率：	150 MHz
CLB-Max的组合延迟：	6.5 ns
JESD-30 代码：	S-PQFP-G100
JESD-609代码：	e0
长度：	14 mm
湿度敏感等级：	3
可配置逻辑块数量：	192
等效关口数量：	2000
输入次数：	88
逻辑单元数量：	192
输出次数：	80
端子数量：	100
最高工作温度：	70 °C
最低工作温度：
组织：	192 CLBS, 2000 GATES
封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP
封装等效代码：	QFP100,.63SQ,20
封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified
座面最大高度：	1.6 mm
子类别：	Field Programmable Gate Arrays
最大供电电压：	5.25 V
最小供电电压：	4.75 V
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm
Base Number Matches：	1

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