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  • 北京元坤伟业科技有限公司

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  • QLX4270RIQT7
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产品型号QLX4270RIQT7的概述

芯片QLX4270RIQT7的概述 QLX4270RIQT7是一款高性能、低功耗的集成电路芯片,主要应用于嵌入式系统、物联网、移动设备、智能家居和工业自动化等领域。该芯片具备强大的运算能力、广泛的接口支持以及良好的抗干扰能力,成为了许多开发者和工程师的优选。在日益发展的智能科技市场中,QLX4270RIQT7凭借其稳定的性能和灵活的应用模式,逐渐占据了一席之地。 芯片QLX4270RIQT7的详细参数 QLX4270RIQT7的核心参数包括: - 处理器架构:该芯片采用ARM Cortex-M4架构,提供高达120 MHz的主频,适合运算密集型的应用。 - 内存:芯片内置128 KB的SRAM和256 KB的Flash存储,可以有效存储程序和数据。 - 输入输出接口: - GPIO:提供多达32个通用输入输出引脚,支持多种功能模式。 - UART:支持多个UART接口,用于串行...

产品型号QLX4270RIQT7的Datasheet PDF文件预览

DisplayPort Lane Extender  
QLx4270-DP  
Features  
• Supports data rates up to 2.7Gb/s per lane  
• Low power (78mW per channel)  
• Low latency (<500ps)  
The QLx4270-DP is a settable quad receive-side  
equalizer with extended functionality for DisplayPort  
applications. The QLx4270-DP compensates for the  
frequency dependent attenuation of copper cables,  
allowing operation on ultra-thin 40AWG cable.  
• Four equalizers in a 4mmx7mm QFN package for  
straight route-through architecture and simplified  
routing  
The small form factor, highly-integrated quad design is  
ideal for high-density data transmission applications  
including active copper cable assemblies.  
• Each equalizer boost is independently pin selectable  
and programmable  
Operating on a single 1.2V power supply, the  
QLx4270-DP enables per channel throughputs of up to  
2.7Gb/s. The QLx4270-DP uses current mode logic (CML)  
inputs/outputs and is packaged in a 4mmx7mm 46 lead  
QFN.  
• 1.2V supply voltage  
Applications  
• DisplayPort (VESA DisplayPort Standard v1.1a)  
• DisplayPort adaptors and repeaters  
Benefits  
• Thinner gauge cable  
• Extends cable reach greater than 5x  
• Improved BER  
Typical Application Circuit  
November 19, 2009  
FN6972.1  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2009. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
QLx4270-DP  
Ordering Information  
PART NUMBER  
TEMP. RANGE  
PACKAGE  
(Pb-Free)  
(Note)  
PART MARKING  
(°C)  
PKG. DWG. #  
L46.4x7  
QLX4270RIQT7  
QLX4270RIQ  
0 to +70  
46 Ld QFN  
7” Prod. Tape & Reel; Qty 1,000  
QLX4270RIQSR  
QLX4270RIQ  
0 to +70  
46 Ld QFN  
L46.4x7  
7” Sample Reel; Qty 100  
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach  
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering  
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free  
requirements of IPC/JEDEC J STD-020.  
Pin Configuration  
QLx4270-DP  
(46 LD QFN)  
TOP VIEW  
39  
46 45 44 43 42 41 40  
DT  
IN1[P]  
IN1[N]  
1
2
NC  
38  
37  
36  
35  
OUT1[P]  
OUT1[N]  
3
V
4
V
DD  
DD  
5
IN2[P]  
IN2[N]  
34 OUT2[P]  
33 OUT2[N]  
6
7
V
32  
V
DD  
DD  
EXPOSED PAD  
(GND)  
IN3[P]  
IN3[N]  
8
31 OUT3[P]  
9
30  
29  
28  
OUT3[N]  
10  
11  
12  
13  
14  
15  
V
V
DD  
DD  
IN4[P]  
IN4[N]  
IS1  
OUT4[P]  
27 OUT4[N]  
26  
25  
24  
IS3  
IS4  
NC  
IS2  
GND  
16 17 18 19 20 21 22  
23  
FN6972.1  
November 19, 2009  
2
QLx4270-DP  
Pin Descriptions  
PIN  
PIN NAME  
NUMBER  
DESCRIPTION  
DT  
1
Detection Threshold. Reference DC CURRENT threshold for input signal power detection. Data  
output Out[k] is muted when the power of the equalized version of In[k] falls below the threshold.  
Tie to ground to disable electrical idle preservation and always enable the limiting amplifier.  
IN1[P,N]  
2, 3  
Equalizer 1 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least  
4GHz frequency response is recommended.  
V
4, 7, 10, 29, Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to  
DD  
32, 35  
ground is recommended for each of these pins for broad high-frequency noise suppression.  
IN2[P,N]  
IN3[P,N]  
IN4[P,N]  
IS1  
5, 6  
Equalizer 2 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least  
4GHz frequency response is recommended.  
8, 9  
11, 12  
13  
Equalizer 3 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least  
4GHz frequency response is recommended.  
Equalizer 4 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least  
4GHz frequency response is recommended.  
Impedance Select 1. CMOS logic input. When the voltage on this pin is LOW, the single-ended input  
impedance of In1P and In1N each go above 200kΩ and powers down the channel. This can be used  
to disable some of the channels in case the DisplayPort application has less than four links, in order  
to save power consumption. Otherwise, connect to VDD to hold the input impedance at 50Ω.  
IS2  
14  
15  
Impedance Select 2. CMOS logic input. When the voltage on this pin is LOW, the single-ended input  
impedance of In1P and In1N each go above 200kΩ and powers down the channel. This can be used  
to disable some of the channels in case the DisplayPort application has less than four links, in order  
to save power consumption. Otherwise, connect to VDD to hold the input impedance at 50Ω.  
GND  
NC  
Ground  
16, 17, 24 No-Connect  
38, 45, 46  
CP3[A,B,C]  
CP4[A,B,C]  
IS4  
18, 19, 20 Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set the  
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.  
21, 22, 23 Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set the  
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.  
25  
Impedance Select 4. CMOS logic input. When the voltage on this pin is LOW, the single-ended input  
impedance of In1P and In1N each go above 200kΩ and powers down the channel. This can be used  
to disable some of the channels in case the DisplayPort application has less than four links, in order  
to save power consumption. Otherwise, connect to VDD to hold the input impedance at 50Ω.  
IS3  
26  
Impedance Select 3. CMOS logic input. When the voltage on this pin is LOW, the single-ended input  
impedance of In1P and In1N each go above 200kΩ and powers down the channel. This can be used  
to disable some of the channels in case the DisplayPort application has less than four links, in order  
to save power consumption. Otherwise, connect to VDD to hold the input impedance at 50Ω.  
OUT4[N,P]  
OUT3[N,P]  
OUT2[N,P]  
OUT1[N,P]  
CP2[C,B,A]  
CP1[C,B,A]  
Exposed Pad  
27, 28  
30, 31  
33, 34  
36, 37  
Equalizer 4 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least  
4GHz frequency response is recommended.  
Equalizer 3 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least  
4GHz frequency response is recommended.  
Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least  
4GHz frequency response is recommended.  
Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least  
4GHz frequency response is recommended.  
39, 40, 41 Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set the  
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.  
42, 43, 44 Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set the  
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.  
-
Exposed ground pad. For proper electrical and thermal performance, this pad should be connected  
to the PCB ground plane.  
FN6972.1  
November 19, 2009  
3
QLx4270-DP  
Absolute Maximum Ratings  
Thermal Information  
Supply Voltage (V  
Voltage at All Input Pins . . . . . . . . . . . -0.3V to V  
DD  
to GND) . . . . . . . . . . . . -0.3V to 1.3V  
+ 0.3V  
ESD Rating at all pins . . . . . . . . . . . . . . . . . . . . 2kV (HBM)  
Thermal Resistance (Typical)  
θ
JA (°C/W)  
32  
θ
Jc (°C/W)  
DD  
46 Ld QFN Package (Note 1) . . . . .  
2.3  
Operating Ambient Temperature Range . . . . . . 0°C to +70°C  
Storage Ambient Temperature Range . . . . -55°C to +150°C  
Maximum Junction Temperature . . . . . . . . . . . . . . . +125°C  
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below  
http://www.intersil.com/pbfree/Pb-FreeReflow.asp  
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact  
product reliability and result in failures not covered by warranty.  
NOTE:  
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief  
TB379 for details.  
Operating Conditions  
PARAMETER  
Supply Voltage  
SYMBOL  
CONDITION  
MIN  
1.1  
0
TYP  
1.2  
25  
MAX  
1.3  
70  
UNITS  
V
V
DD  
Operating Ambient Temperature  
Bit Rate  
T
°C  
A
NRZ data applied to any channel  
1.5  
2.7  
Gb/s  
Control Pin Characteristics V  
= 1.2V, T = +25°C, and V = 800mV , unless otherwise noted.  
IN P-P  
DD  
A
PARAMETER  
SYMBOL  
CONDITION  
MIN  
TYP MAX UNITS NOTES  
‘LOW’ Resistance State  
CP[k]  
CP[k]  
CP[k]  
0
1
27.5  
kΩ  
kΩ  
kΩ  
µA  
2
2
2
‘MID’ Resistance State  
‘HIGH’ Resistance State  
22.5  
500  
25  
30  
Input Current  
NOTE:  
Current draw on digital pin, i.e., CP[k]  
100  
2. If four CP pins are tied together, the resistance values in this table should be divided by four.  
Electrical Characteristics V  
= 1.2V, T = +25°C, and V = 800mV , unless otherwise noted.  
A IN P-P  
DD  
PARAMETER  
Supply Current  
SYMBOL  
CONDITION  
MIN TYP MAX UNITS NOTES  
I
260  
mA  
1380 mV  
DD  
IC Input Amplitude  
Range  
V
Measured differentially at data source before  
encountering channel loss  
340  
80  
40  
9
3
IN  
P-P  
DC Differential Input  
Resistance  
Measured on input channel IN[k]  
Measured on input channel IN[k]P or IN[k]N  
50MHz to 1.35GHz  
100  
50  
120  
60  
Ω
Ω
DC Single-Ended Input  
Resistance  
Input Return Loss  
(Differential)  
S
11  
dB  
4
DD  
Output Amplitude Range  
V
Measured differentially at OUT[k]P and OUT[k]N 150  
with 50Ω load on both output pins  
550  
105  
650  
120  
mV  
P-P  
OUT  
Differential Output  
Impedance  
Measured on OUT[k]  
50MHz to 1.35GHz  
50MHz to 1.35GHz  
80  
10  
5
Ω
Output Return Loss  
(Differential)  
S
22  
22  
dB  
dB  
4
4
DD  
Output Return Loss  
(Common Mode)  
S
CC  
FN6972.1  
November 19, 2009  
4
QLx4270-DP  
Electrical Characteristics V  
= 1.2V, T = +25°C, and V = 800mV , unless otherwise noted. (Continued)  
DD  
SYMBOL  
22  
A
IN  
P-P  
PARAMETER  
CONDITION  
MIN TYP MAX UNITS NOTES  
Output Return Loss  
(Com. to Diff.  
Conversion)  
S
50MHz to 1.35GHz  
20  
dB  
UI  
4
DC  
Output Residual Jitter  
2.7Gb/s; Up to 2m 38AWG standard twin-axial  
cable (11.5dB loss)  
0.15  
60  
0.2  
3, 5, 6  
7
Output Transition Time  
Lane-to-Lane Skew  
Propagation Delay  
NOTES:  
t , t  
20% to 80%  
30  
100  
50  
ps  
ps  
ps  
r
f
From IN[k] to OUT[k]  
500  
3. After channel loss, differential amplitudes at QLx4270-DP inputs must meet the input voltage range specified in “Absolute  
Maximum Ratings” on page 4.  
4. Temperature = +25°C, V  
= 1.2V.  
DD  
5. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted  
signal (as measured at the input to the channel). Total jitter (TJ) is DJ + 14.1 x RJ  
pp  
.
RMS  
7
6. Measured using a PRBS 2 -1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent,  
media-induced loss only.  
7. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.  
TABLE 1. MAPPING BETWEEN CP-SETTING RESISTOR  
Control Pin Boost Setting  
AND QLx4270-DP BOOST LEVELS (Continued)  
The voltages at the CP pins are used to determine the  
RESISTANCE BETWEEN CP PIN  
boost level of each channel of QLx4270-DP. For each of  
AND V  
DD  
the four channels, k, the [A], [B], and [C] control pins  
(CP[k]) are associated with a 3-bit non binary word.  
While [A] can take one of two values, ‘LOW’ or ‘HIGH,  
[B] and [C] can take one of three different values: ‘LOW,  
‘MIDDLE, or ‘HIGH. This is achieved by changing the  
value of a resistor connected between VDD and the CP  
pin, which is internally pulled low with a 25kΩ resistor.  
Thus, a ‘HIGH’ state is achieved by using a 0Ω resistor,  
‘MIDDLE’ is achieved with a 25kΩ resistor, and ‘LOW’ is  
achieved with an open resistance. Table 1 defines the  
mapping from the 3-bit CP word to the 18 out of 32  
possible levels available via the serial interface on the  
Evaluation Board kit.  
SERIAL BOOST  
LEVEL  
CP[A]  
0Ω  
CP[B]  
CP[C]  
25kΩ  
0Ω  
Open  
Open  
25kΩ  
25kΩ  
25kΩ  
0Ω  
17  
19  
21  
23  
24  
26  
28  
31  
0Ω  
0Ω  
Open  
25kΩ  
0Ω  
0Ω  
0Ω  
0Ω  
Open  
25kΩ  
0Ω  
0Ω  
0Ω  
0Ω  
0Ω  
TABLE 1. MAPPING BETWEEN CP-SETTING RESISTOR  
AND QLx4270-DP BOOST LEVELS  
If all four channels are to use the same boost level, then  
a minimum number of board resistors can be realized by  
tying together like CP[k][A,B,C] pins across all channels  
k. For instance, all four CP[k][A] pins can be tied to the  
same resistor running to VDD. Consequently, only three  
resistors are needed to control the boost of all four  
channels. If the CP Pins are tied together and the 25kΩ is  
used, the value changes to a 3.125kΩ resistor because  
the 25kΩ is divided by 4.  
RESISTANCE BETWEEN CP PIN  
AND V  
DD  
SERIAL BOOST  
CP[A]  
Open  
Open  
Open  
Open  
Open  
Open  
Open  
Open  
Open  
0Ω  
CP[B]  
Open  
Open  
Open  
25kΩ  
25kΩ  
25kΩ  
0Ω  
CP[C]  
Open  
25kΩ  
0Ω  
LEVEL  
0
2
4
Open  
25kΩ  
0Ω  
6
Channel Power-Down  
8
The IS[k] pin powers down the equalizer channel when  
pulled low. This feature allows individually to power down  
unused channels and to minimize power consumption.  
Example: for DisplayPort applications with 1 or 2 links,  
the unused channels may be powered down to save  
power. The current draw for a channel is reduced from  
50mA to 3.8mA when powered down.  
10  
12  
14  
15  
16  
Open  
25kΩ  
0Ω  
0Ω  
0Ω  
Open  
Open  
FN6972.1  
November 19, 2009  
5
QLx4270-DP  
®
About Q:Active  
Historically, cable manufacturers have relied on  
thick wire gauge cables to deliver Deep Color  
images to the monitors and projectors. However,  
these cables are bulky, unwieldy and esthetically  
unappealing. To address this, Intersil has  
®
developed its groundbreaking Q:ACTIVE product  
line. By integrating its analog ICs inside DisplayPort  
cables, Intersil is able to achieve unsurpassed  
improvements in cable gauges, reach and  
transmitted image quality.  
For additional products, see www.intersil.com/product_tree  
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted  
in the quality certifications found at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications  
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by  
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any  
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any  
patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN6972.1  
November 19, 2009  
6
QLx4270-DP  
Package Outline Drawing  
L46.4x7  
46 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (TQFN)  
Rev 0, 9/09  
2.80  
42X  
4.00  
A
0.40  
6
B
46  
39  
PIN 1  
INDEX AREA  
1
6
38  
PIN 1  
INDEX AREA  
5.50 ±0.1  
Exp. DAP  
5.60  
15  
24  
(4X)  
0.05  
4
46X 0.20  
16  
23  
0.10M C A B  
SIDE VIEW  
TOP VIEW  
2.50 ±0.1  
Exp. DAP  
46X 0.40  
BOTTOM VIEW  
SEE DETAIL "X"  
0.10 C  
C
0.70 ±0.05  
SEATING PLANE  
0.05 C  
5
SIDE VIEW  
C
0.152 REF  
0 . 00 MIN.  
0 . 05 MAX.  
DETAIL "X"  
( 3.80 )  
( 2.50)  
NOTES:  
1. Dimensions are in millimeters.  
Dimensions in ( ) for Reference Only.  
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.  
3. Unless otherwise specified, tolerance : Decimal ± 0.05  
( 6.80 )  
( 42X 0.40)  
( 5.50 )  
4. Dimension applies to the metallized terminal and is measured  
between 0.15mm and 0.30mm from the terminal tip.  
Tiebar shown (if present) is a non-functional feature.  
5.  
6.  
(46X 0.20)  
The configuration of the pin #1 identifier is optional, but must be  
located within the zone indicated. The pin #1 identifier may be  
either a mold or mark feature.  
( 46 X 0.60)  
TYPICAL RECOMMENDED LAND PATTERN  
FN6972.1  
November 19, 2009  
7
配单直通车
QLX4300SIQSR产品参数
型号:QLX4300SIQSR
Brand Name:Intersil
生命周期:Unknown
IHS 制造商:INTERSIL CORP
零件包装代码:QFN
包装说明:HVQCCN, LCC46,.16X.28,16
针数:46
Reach Compliance Code:compliant
HTS代码:8542.39.00.01
Factory Lead Time:9 weeks
风险等级:5.61
Is Samacsys:N
JESD-30 代码:R-PQCC-N46
JESD-609代码:e4
长度:7 mm
湿度敏感等级:1
功能数量:1
端子数量:46
最高工作温度:70 °C
最低工作温度:
封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN
封装等效代码:LCC46,.16X.28,16
封装形状:RECTANGULAR
封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260
电源:1.2 V
认证状态:Not Qualified
座面最大高度:0.75 mm
子类别:Other Telecom ICs
标称供电电压:1.2 V
表面贴装:YES
电信集成电路类型:TELECOM CIRCUIT
温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD
端子节距:0.4 mm
端子位置:QUAD
处于峰值回流温度下的最长时间:30
宽度:4 mm
Base Number Matches:1
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