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产品型号RT8065ZQW的概述

芯片RT8065ZQW的概述 RT8065ZQW是一款高效的DC-DC降压转换器，专为不同应用中的电力管理而设计。该芯片采用了高频PWM控制，具有出色的负载和线路调节能力，能够在宽输入电压范围内稳定输出所需电压。RT8065ZQW的设计目的在于满足移动设备、计算机和网络设备等现代电子产品对高效能和小型化的迫切需求。作为一款集成度高的电源管理单元，RT8065ZQW在许多电子产品中被广泛应用。这款芯片不仅能够提供恒定的输出电压和电流，还能有效降低功耗，提高整体系统的能效。这使它成为设计师和工程师在各种应用场景下的理想选择。芯片RT8065ZQW的详细参数 RT8065ZQW的功能参数包括： - 输入电压范围：2.5V至5.5V - 输出电压范围：0.6V至5V，可通过外部电阻调整 - 输出电流：高达3A - 效率：最高达96% - 开关频率：300kHz至2MHz可调 - 封装类型：...

产品型号RT8068A的Datasheet PDF文件预览

RT8068A

3A, 1MHz, Synchronous Step-Down Converter

General Description

Features

^zHigh Efficiency : Up to 95%

The RT8068A is a high efficiency synchronous, step-down

DC/DC converter. It's input voltage range from 2.7V to 5.5V

that provides an adjustable regulated output voltage from

0.6V to V_INwhile delivering up to 3A of output current.

The internal synchronous low on resistance power

switches increase efficiency and eliminate the need for

an external Schottky diode. The switching frequency is

fixed internally at 1MHz. The 100% duty cycle provides

low dropout operation, hence extending battery life in

portable systems. Current mode operation with internal

compensation allows the transient response to be

optimized over a wide range of loads and output capacitors.

The RT8068A is available in WDFN-10L 3x3 and SOP-8

(Exposed Pad) packages.

^zLow R_DS(ON)Internal Switches : 69mΩ/49mΩ at V_IN

= 5V

^zFixed Frequency : 1MHz

^zNo Schottky Diode Required

^zInternal Compensation

^z0.6V Reference Allows Low Output Voltage

^zLow Dropout Operation : 100% Duty Cycle

^zOCP, UVP, OVP, OTP

^zRoHS Compliant and Halogen Free

Applications

z Portable Instruments

z Battery Powered Equipment

z Notebook Computers

z Distrib uted Power Systems

z IP Phones

Ordering Information

RT8068A

Package Type

QW : WDFN-10L 3x3 (W-Type)

SP : SOP-8 (Exposed Pad-Option 2)

z Digital Cameras

Pin Configurations

Lead Plating System

Z : ECO (Ecological Element with

Halogen Free and Pb free)

(TOP VIEW)

PVIN

SVIN

Note :

PGOOD

Richtek products are :

ꢀRoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

ꢀSuitable for use in SnPb or Pb-free soldering processes.

WDFN-10L 3x3

PVIN

SVIN

PGOOD

GND

Marking Information

RT8068AZQW

13 : Product Code

SOP-8 (Exposed Pad)

YMDNN : Date Code

13 YM

DNN

RT8068AZSP

RT8068AZSP : Product Code

RT8068A

YMDNN : Date Code

ZSPYMDNN

DS8068A-03 May 2011

www.richtek.com

RT8068A

Typical Application Circuit

RT8068A

PGOOD

OUT

100k

PVIN

SVIN

FB1

10µF

1µF

FB2

Chip Enable

GND

Table 1. Recommended Component Selection

(kΩ) (kΩ) (pF) L (μH)

(V)

FB1

FB2

OUT

(μF)

OUT

3.3

2.5

1.8

1.5

1.2

1.0

229.5

161.5

102

76.5

22 x 2

1.5

Functional Pin Description

Pin No.

Pin Function

SOP-8

Name

WDFN-10L

(Exposed Pad)

1, 2, 3

1, 2

Switch Node. Connect this pin to the inductor.

Power Good Indicator. This pin is an open drain logic output that is

PGOOD pulled to ground when the output voltage is less than 90% of the

target output voltage. Hysteresis = 5%.

Enable Control. Pull high to turn on. Do not float.

Feedback Pin. This pin receives the feedback voltage from a

resistive voltage divider connected across the output.

No Internal Connection.

Signal Input Pin. Decouple this pin to GND with at least 1μF ceramic

cap.

SVIN

Power Input Pin. Decouple this pin to GND with at least 4.7μF

ceramic cap.

Ground. The exposed pad must be soldered to a large PCB and

connected to GND for maximum power dissipation.

9,10

7,8

PVIN

GND

(Exposed Pad) (Exposed Pad)

www.richtek.com

DS8068A-03 May 2011

RT8068A

Function Block Diagram

PVIN

ISEN

PGOOD

Slope

Com

OSC

REF

0.6V

Limit

Output

Clamp

Driver

Int-SS

0.72V

Control

Logic

0.54V

0.4V

NISEN

PGOOD

Zero Current

POR

SVIN

OTP

DS8068A-03 May 2011

www.richtek.com

RT8068A

Absolute Maximum Ratings (Note 1)

z Supply Input Voltage, PVIN, SVIN--------------------------------------------------------------------------------- −0.3V to 6.5V

z LX Pin

DC------------------------------------------------------------------------------------------------------------------------- (V_IN+ 0.3V) to 6.8V

< 20ns ------------------------------------------------------------------------------------------------------------------- −2.5V to 9V

z Other I/O Pin Voltage------------------------------------------------------------------------------------------------- −0.3V to 6.5V

z Power Dissipation, P_D@ T_A= 25°C

WDFN-10L 3x3 --------------------------------------------------------------------------------------------------------- 1.429W

SOP-8 (Exposed Pad) ----------------------------------------------------------------------------------------------- 1.333W

z Package Thermal Resistance (Note 2)

WDFN-10L 3x3, θ_JA--------------------------------------------------------------------------------------------------- 70°C/W

WDFN-10L 3x3, θ_JC--------------------------------------------------------------------------------------------------- 8.2°C/W

SOP-8 (Exposed Pad), θ_JA------------------------------------------------------------------------------------------ 75°C/W

SOP-8 (Exposed Pad), θ_JC----------------------------------------------------------------------------------------- 15°C/W

z Lead Temperature (Soldering, 10 sec.)--------------------------------------------------------------------------- 260°C

z Junction Temperature ------------------------------------------------------------------------------------------------- 150°C

z Storage Temperature Range ---------------------------------------------------------------------------------------- −65°C to 150°C

z ESD Susceptibility (Note 3)

HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 2kV

MM (Machine Mode) -------------------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions (Note 4)

z Supply Input Voltage, PVIN, SVIN--------------------------------------------------------------------------------- 2.7V to 5.5V

z Junction Temperature Range---------------------------------------------------------------------------------------- −40°C to 125°C

z Ambient Temperature Range---------------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics

(V_IN= 3.3V, T_A= 25°C, unless otherwise specified)

Parameter

Symbol

Test Conditions

Min

0.594

Typ

0.6

0.1

Max

0.606

0.4

Unit

Feedback Reference Voltage

Feedback Leakage Current

REF

μA

Active , V = 0.7V, Not

Switching

110

140

DC Bias Current

μA

Shutdown

0.3

= 2.7V to 5.5V

Output Voltage Line Regulation

%/V

= 0A

OUT

Output Voltage Load Regulation

Switch Leakage Current

Switching Frequency

= 0A to 3A

−1

μA

OUT

0.8

1.2

MHz

mΩ

Switch On Resistance, High

Switch On Resistance, Low

P-MOSFET Current Limit

= 5V

DS(ON)_P

DS(ON)_N

LIM

Rising

Falling

2.2

2.4

2.2

2.6

2.4

Under Voltage Lockout

Threshold

UVLO

To be continued

www.richtek.com

DS8068A-03 May 2011

RT8068A

Parameter

Symbol

Test Conditions

Min

1.6

Typ

Max

Unit

Logic-High

Logic-Low

EN Input

Threshold Voltage

0.4

EN Pull Low Resistance

500

150

kΩ

°C

Over Temperature Protection

Hysteresis

°C

Soft-Start Time

500

μs

Discharge Resistance

Over Voltage Protection

100

OUT

115

120

130

(Latch-Off, Delay Time = 10μs)

OUT

Under Voltage Lock Out

(Latch-Off)

Measured FB, With Respect to

Power Good

REF

Power Good Hysteresis

Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may remain possibility to affect device reliability.

Note 2. θ_JAis measured in natural convection at T_A= 25°C on a high effective thermal conductivity four-layer test board of

JEDEC 51-7 thermal measurement standard. The measurement case position of θ_JCis on the exposed pad of the

packages.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

DS8068A-03 May 2011

www.richtek.com

RT8068A

Typical Operating Characteristics

Efficiency vs. Load Current

100

V_IN= 4.2V

V_IN= 5V

V_IN= 3.3V

V_IN= 5V

V_OUT= 1.8V

2.5 3

V_OUT= 3.3V

2.5

0.5

1.5

0.5

1.5

Load Current (A)

Efficiency vs. Load Current

Output Voltage vs. Output Current

100

1.820

1.815

1.810

1.805

1.800

1.795

1.790

1.785

1.780

V_IN= 3.3V

V_IN= 5V

V_IN= 3.3V

V_OUT= 1.05V

2.5

V_OUT= 1.8V

2.5 3

0.5

1.5

0.5

1.5

Output Current (A)

Load Current (A)

Current Limit vs. Input Voltage

Current Limit vs. Temperature

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

V_IN= 5V

V_IN= 3.3V

V_OUT= 1.05V

75 100 125

2.5

3.5

4.5

5.5

-50

-25

Input Voltage (V)

Temperature (°C)

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DS8068A-03 May 2011

RT8068A

R_DS(ON)vs. Temperature

Load Transient Response

V_OUT

P-MOSFET

(50mV/Div)

I_OUT

(2A/Div)

N-MOSFET

V_IN= 5V

100 125

V_IN= 5V, V_OUT= 1.8V, I_OUT= 0.5A to 3A

-50

-25

Time (50μs/Div)

Temperature (°C)

Load Transient Response

Switching

V_OUT

(50mV/Div)

V_OUT

(5mV/Div)

V_LX

(5V/Div)

I_OUT

(2A/Div)

I_LX

(1A/Div)

V_IN= 5V, V_OUT= 1.8V, I_OUT= 1.5A to 3A

V_IN= 5V, V_OUT= 1.8V, I_OUT= 1.5A

Time (500ns/Div)

Time (50μs/Div)

Over Voltage Protection

Switching

V_OUT

(5mV/Div)

V_LX

(5V/Div)

V_OUT

(1V/Div)

I_LX

(2A/Div)

V_LX

(2V/Div)

V_IN= 5V, V_OUT= 1.8V, I_OUT= 1A

V_IN= 5V, V_OUT= 1.8V, I_OUT= 3A

Time (500ns/Div)

Time (10μs/Div)

DS8068A-03 May 2011

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RT8068A

Under Voltage Protection

Over Current Protection

V_IN= 5V, V_OUT= 1.8V

V_OUT

(1V/Div)

V_OUT

(1V/Div)

I_LX

(5A/Div)

V_LX

(2V/Div)

V_LX

(2V/Div)

Time (2.5μs/Div)

Time (5μs/Div)

Power On from V_IN

Power Off from V_IN

V_IN

(2V/Div)

V_IN

(2V/Div)

V_OUT

(1V/Div)

V_OUT

(1V/Div)

I_LX

(2A/Div)

I_LX

(2A/Div)

V_OUT= 1.8V, I_OUT= 3A

Time (2.5ms/Div)

Power On from EN

Power Off from EN

V_EN

(5V/Div)

V_EN

(5V/Div)

V_OUT

(1V/Div)

V_OUT

(1V/Div)

I_LX

(2A/Div)

I_LX

(2A/Div)

V_IN= 5V, V_OUT= 1.8V, I_OUT= 3A

Time (200μs/Div)

Time (40μs/Div)

www.richtek.com

DS8068A-03 May 2011

RT8068A

Application Information

UVLO Protection

The RT8068Ais a single-phase buck converter. It provides

single feedback loop, current mode control with fast

transient response. An internal 0.6V reference allows the

output voltage to be precisely regulated for low output

voltage applications. Afixed switching frequency (1MHz)

oscillator and internal compensation are integrated to

minimize external component count. Protection features

include over current protection, under voltage protection,

over voltage protection and over temperature protection.

The RT8068Ahas input Under Voltage Lockout protection

(UVLO). If the input voltage exceeds the UVLO rising

threshold voltage (2.4V typ.), the converter resets and

prepares the PWM for operation. If the input voltage falls

below the UVLO falling threshold voltage during normal

operation, the device will stop switching. The UVLO rising

and falling threshold voltage has a hysteresis to prevent

noise-caused reset.

Output Voltage Setting

Inductor Selection

Connect a resistive voltage divider at the FB between V_OUT

andGNDto adjust the output voltage. The output voltage

is set according to the following equation :

The switching frequency (on-time) and operating point (%

ripple or LIR) determine the inductor value as shown below:

× V − V

IN OUT

(

)

OUT

L =

R_FB1

R_FB2

⎛

⎝

⎞

⎟

⎠

× LIR × I

× V

V_OUT= V_REF× 1 +

LOAD(MAX) IN

⎜

where V_REFis 0.6V (typ.).

where LIR is the ratio of the peak-to-peak ripple current to

the average inductor current.

OUT

Find a low loss inductor having the lowest possible DC

resistance that fits in the allotted dimensions. Ferrite cores

are often the best choice, although powdered iron is

inexpensive and can work well at 200kHz. The core must

be large enough not to saturate at the peak inductor current

(I_PEAK) :

FB1

FB2

GND

Figure 1. Setting V_OUTwith a Voltage Divider

LIR

⎛

⎜

⎝

⎞

⎟

⎠

I_PEAK= I_LOAD(MAX)

×I_LOAD(MAX)

Chip Enable and Disable

The EN pin allows for power sequencing between the

controller bias voltage and another voltage rail. The

RT8068Aremains in shutdown if the ENpin is lower than

400mV. When the EN pin rises above the V_ENtrip point,

the RT8068Abegins a new initialization and soft-start cycle.

The calculation above serves as a general reference. To

further improve transient response, the output inductor

can be further reduced. This relation should be considered

along with the selection of the output capacitor.

Input Capacitor Selection

Internal Soft-Start

High quality ceramic input decoupling capacitor, such as

X5R or X7R, with values greater than 20μF are

recommended for the input capacitor. The X5R and X7R

ceramic capacitors are usually selected for power regulator

capacitors because the dielectric material has less

capacitance variation and more temperature stability.

The RT8068A provides an internal soft-start function to

prevent large inrush current and output voltage overshoot

when the converter starts up. The soft-start (SS)

automatically begins once the chip is enabled.During soft-

start, the internal soft-start capacitor becomes charged

and generates a linear ramping up voltage across the

capacitor. This voltage clamps the voltage at the FB pin,

causing PWM pulse width to increase slowly and in turn

reduce the output surge current. The internal 0.6V

reference takes over the loop control once the internal

ramping-up voltage becomes higher than 0.6V.

Voltage rating and current rating are the key parameters

when selecting an input capacitor. Generally, selecting an

input capacitor with voltage rating 1.5 times greater than

the maximum input voltage is a conservatively safe design.

DS8068A-03 May 2011

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RT8068A

The input capacitor is used to supply the input RMS

current, which can be approximately calculated using the

following equation :

during load transient. However, the ceramic capacitor can

only provide low capacitance value. Therefore, use a mixed

combination of electrolytic capacitor and ceramic capacitor

to obtain better transient performance.

OUT

⎛

⎝

⎞

⎟

⎠

OUT

= I

× 1−

IN_RMS

LOAD

⎜

Power Good Output (PGOOD)

The next step is selecting a proper capacitor for RMS

current rating. One good design is using more than one

capacitor with low equivalent series resistance (ESR) in

parallel to form a capacitor bank.

PGOODis an open-drain type output and requires a pull-

up resistor. PGOOD is actively held low in soft-start,

standby, and shutdown. It is released when the output

voltage rises above 90% of nominal regulation point. The

PGOOD signal goes low if the output is turned off or is

10% below its nominal regulation point.

The input capacitance value determines the input ripple

voltage of the regulator. The input voltage ripple can be

approximately calculated using the following equation :

I_OUT(MAX)×0.25

Under Voltage Protection (UVP)

ΔV

C_IN×f_SW

The output voltage can be continuously monitored for under

voltage. When under voltage protection is enabled, both

UGATE and LGATE gate drivers will be forced low if the

output is less than 66% of its set voltage threshold. The

UVP will be ignored for at least 3ms (typ.) after start up or

a rising edge on the ENthreshold. Toggle ENthreshold or

cycle V_INto reset the UVP fault latch and restart the

controller.

For example, if I_{OUT_MAX}= 3A, C_IN= 20μF, f_SW= 1MHz,

the input voltage ripple will be 37.5mV.

Output Capacitor Selection

The output capacitor and the inductor form a low pass

filter in the buck topology. In steady state condition, the

ripple current flowing into/out of the capacitor results in

ripple voltage. The output voltage ripple (V_P-P) can be

calculated by the following equation :

Over Voltage Protection (OVP)

The RT8068A is latched once OVP is triggered and can

only be released by toggling EN threshold or cycling V_IN.

There is a 10μs delay built into the over voltage protection

circuit to prevent false transition.

⎛

⎝

⎞

⎟

⎠

V_{P_P}= LIR×I_LOAD(MAX)× ESR +

⎜

8×C_OUT×f_SW

When load transient occurs, the output capacitor supplies

the load current before the controller can respond.

Therefore, the ESR will dominate the output voltage sag

Over Current Protection (OCP)

during load transient. The output voltage undershoot (V_SAG

can be calculated by the following equation :

V_SAG= ΔI_LOAD×ESR

)

The RT8068A provides over current protection by detecting

high side MOSFET peak inductor current. If the sensed

peak inductor current is over the current limit threshold

(4A typ.), the OCP will be triggered. When OCP is tripped,

the RT8068A will keep the over current threshold level

until the over current condition is removed.

For a given output voltage sag specification, the ESR value

can be determined.

Another parameter that has influence on the output voltage

sag is the equivalent series inductance (ESL). The rapid

change in load current results in di/dt during transient.

Therefore, the ESL contributes to part of the voltage sag.

Using a capacitor with low ESL can obtain better transient

performance. Generally, using several capacitors

connected in parallel can have better transient performance

than using a single capacitor for the same total ESR.

Thermal Shutdown (OTP)

The device implements an internal thermal shutdown

function when the junction temperature exceeds 150°C.

The thermal shutdown forces the device to stop switching

when the junction temperature exceeds the thermal

shutdown threshold. Once the die temperature decreases

below the hysteresis of 20°C, the device reinstates the

power up sequence.

Unlike the electrolytic capacitor, the ceramic capacitor has

relatively low ESR and can reduce the voltage deviation

www.richtek.com

DS8068A-03 May 2011

RT8068A

Thermal Considerations

The maximum power dissipation depends on the operating

ambient temperature for fixed T_J(MAX)and thermal

resistance, θ_JA. For the RT8068A package, the derating

curves in Figure 2 allow the designer to see the effect of

rising ambient temperature on the maximum power

dissipation.

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

Layout Considerations

Layout is very important in high frequency switching

converter design. The PCB can radiate excessive noise

and contribute to converter instability with improper layout.

Certain points must be considered before starting a layout

using the RT8068A.

P_D(MAX)= (T_J(MAX)− T_A) / θ_JA

where T_J(MAX)is the maximum junction temperature, T_Ais

the ambient temperature, and θ_JAis the junction to ambient

thermal resistance.

For recommended operating condition specifications of

the RT8068A, the maximum junction temperature is 125°C

and T_Ais the ambient temperature. The junction to ambient

thermal resistance, θ_JA, is layout dependent. For SOP-8

(Exposed Pad) packages, the thermal resistance, θ_JA, is

75°C/W on a standard JEDEC 51-7 four-layer thermal test

board. For WDFN-10L 3x3 packages, the thermal

resistance, θ_JA, is 70°C/W on a standard JEDEC 51-7

four-layer thermal test board. The maximum power

dissipation at T_A= 25°C can be calculated by the following

formulas :

ꢀ Make the traces of the main current paths as short and

wide as possible.

ꢀPut the input capacitor as close as possible to the device

pins (V_INandGND).

ꢀLX node encounters high frequency voltage swings so it

should be kept in a small area. Keep sensitive

components away from the LX node to prevent stray

capacitive noise pick-up.

ꢀ Ensure all feedback network connections are short and

direct. Place the feedback network as close to the chip

as possible.

P_D(MAX)= (125°C − 25°C) / (75°C/W) = 1.333W for

ꢀ TheGNDpin and Exposed Pad should be connected to

a strong ground plane for heat sinking and noise

protection.

SOP-8 (Exposed Pad) package

P_D(MAX)= (125°C − 25°C) / (70°C/W) = 1.429W for

WDFN-10L 3x3 package

ꢀ An example of PCB layout guide is shown in Figure 3.

1.50

for reference.

Four-Layer PCB

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

0.50

0.40

0.30

0.20

0.10

0.00

Input capacitor must be placed

as close to the IC as possible.

The output capacitor must

be placed near the IC.

WDFN-10L 3x3

GND

OUT

SOP-8 (Exposed Pad)

IN1

PVIN

SVIN

OUT

IN2

PGOOD

LX should be connected to

inductor by wide and short trace.

Keep sensitive components

away from this trace.

The voltage divider must

be connected as close to

the device as possible.

100

125

Ambient Temperature (°C)

Figure 3. PCB Layout Guide

Figure 2.Derating Curves for RT8068APackages

DS8068A-03 May 2011

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RT8068A

Outline Dimension

SEE DETAIL A

DETAILA

Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

Max

0.800

0.050

0.250

0.300

3.050

2.650

3.050

1.750

Min

Max

0.700

0.000

0.175

0.180

2.950

2.300

2.950

1.500

0.028

0.000

0.007

0.116

0.091

0.116

0.059

0.031

0.002

0.010

0.012

0.120

0.104

0.120

0.069

0.500

0.020

0.350

0.450

0.014

0.018

W-Type 10L DFN 3x3 Package

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DS8068A-03 May 2011

RT8068A

EXPOSED THERMAL PAD

(Bottom of Package)

Dimensions In Millimeters Dimensions In Inches

Symbol

Min

Max

Min

Max

4.801

3.810

1.346

0.330

1.194

0.170

0.000

5.791

0.406

2.000

2.100

3.000

5.004

4.000

1.753

0.510

1.346

0.254

0.152

6.200

1.270

2.300

2.500

3.500

0.189

0.150

0.053

0.013

0.047

0.007

0.000

0.228

0.016

0.079

0.083

0.118

0.197

0.157

0.069

0.020

0.053

0.010

0.006

0.244

0.050

0.091

0.098

0.138

Option 1

Option 2

8-Lead SOP (Exposed Pad) Plastic Package

Richtek Technology Corporation

Headquarter

Richtek Technology Corporation

Taipei Office (Marketing)

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

5F, No. 95, Minchiuan Road, Hsintien City

Taipei County, Taiwan, R.O.C.

Tel: (8863)5526789 Fax: (8863)5526611

Tel: (8862)86672399 Fax: (8862)86672377

Email: marketing@richtek.com

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit

design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be

guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

DS8068A-03 May 2011

www.richtek.com

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配单直通车

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

柒号芯城电子商务（深圳）有限公司服务专线: 18922803401 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

深圳市中利达电子科技有限公司服务专线: 0755-13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

RT8068A产品参数

型号:	RT8068A
Status：	Active
Vin (min) (V)：	2.7
Vin (max) (V)：	5.5
Number of Outputs：	1
Vout (min) (V)：	0.6
Vout (max) (V)：	5.5
Preset Vout (V)：
Output Adj. Method：	Resistor
Iout (max) (A)：	3
Current Limit (typ) (A)：	4
Freq (typ) (kHz)：	1000
Freq (min) (kHz)：
Freq (max) (kHz)：
Ext Sync：	No
Ron_HS (typ) (mOhm)：	69
Ron_LS (typ) (mOhm)：	49
Iq (typ) (mA)：	0.11
Features：	100% Duty Cycle;Current Mode Control;Enable Input;Fast Transient Response;Internal Compensation;OCP;OVP;PSM;Power Good;Stable with Ceramic Capacitor;UVP
Package Type：	WDFN3x3-10;PSOP-8

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产品导航

产品型号RT8065ZQW的概述

产品型号RT8068A的Datasheet PDF文件预览

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