SC417/SC427
Applications Information (continued)
current handling (including the chip power ground con-
nections). Power components should be placed to mini-
mize current loops and reduce losses. Make all the power
connections on one side of the PCB using wide copper
areas if possible. Do not use minimum land patterns for
power components.
Control Section
Locate all components referenced to AGND on the sche-
matic and place these components near the device and
on the same side if possible. Connect AGND to the AGND
pad and pins using a plane or island if possible.
The device supply decoupling capacitor (V5V to PGND)
should be located as close as possible to the pins. The V5V
decoupling capacitor preferred placement is on the oppo-
site side of the PCB. It should be routed with traces as
short as possible, using at least two vias when connecting
through the PCB.
Current Limit
Obtaining an accurate current limit for the SC417/SC427
requires careful PCB layout. The device uses the RDS(ON) of
the low-side MOSFET for current sensing. The ILIM com-
parator that performs the current limit function monitors
the ILIM pin with respect to AGND, but the low-side
MOSFET is internally connected to PGND. The PCB layout
needs to following these guidelines.
There are two sensitive feedback-related pins at the device
— VOUT and FB. Proper routing is essential to keep noise
away from these signals. All components connected to FB
should be located directly at the chip, and the copper area
of the FB node must be minimized. The VOUT trace that
feeds into the VOUT pin, which also feeds the FB resistor
divider, must be kept as far away as possible from noise
sources such as all switching signals (LX, DH, DL, BST) and
the inductor. Route the VOUT trace in a quiet layer if pos-
sible, from the output capacitor back to the chip.
• AGND and PGND must be connected together
directly at the pins of the IC and not anywhere
else. This can be done through PCB copper or a
zero ohm resistor. Keep the traces short and
direct. The preferred connection for PGND is at
pin 19. The preferred connection for AGND is at
the PAD1.
• The PGND path from the device to the input and
output capacitors requires a wide copper areas.
Use multiple vias and copper areas if available.
Do not break up these copper areas with inter-
vening components. The goal is to minimize
the IR drop between all PGND connections.
• Provide multiple vias and multiple copper areas
between the LX pins and the inductor. The goal
is to minimize any IR drop that might contrib-
uted to the RDS(ON). This is also good to carry
heat away from the device.
• For the connection from the RLIM resistor to the
LX node, use a direct Kelvin connection to pin 28
(LX), as near to the pin as possible. Do not
connect to a place further in the copper between
the LX pins and the inductor — the intervening
copper will appear as increased RDS(ON) and will
reduce the operating current limit.
Power Section
The switcher power section key guidelines are as follows.
• There should be a very small input loop between
the input capacitors, inductor, and output
capacitors. Locate the input decoupling capaci-
tors directly at the VIN pad on the device.
• The LX phase node should be a large enough to
carry the required current. Careful sizing is
required since this is the noisiest node.
• The PGND connection between the input capaci-
tors, low-side MOSFET, and output capacitors
should be as small as possible, with wide traces
or planes and multiple vias.
• The impedance of the PGND connection
between the low-side MOSFET and the PGND
pin should be minimized. This connection must
carry the DL drive current, which has high peaks
at both rising and falling edges. Use multiple
layers and multiple vias to minimize impedance
and keep the distance as short as practical.
The layout can be considered in two parts; the control
section referenced to AGND, and the switcher power
section referenced to GND.
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