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SC417/SC427

10A Integrated FET Regulator

with Programmable LDO

POWER MANAGEMENT

Features

Description

Input voltage — 3V to 28V

Internal power MOSFETs — 10A

Integrated bootstrap switch

Smart power-save protection

The SC417/SC427 is a stand-alone synchronous buck

power supply. It features integrated power MOSFETs, a

bootstrap switch, and a programmable LDO in a space-

saving MLPQ-5x5mm 32-pin package. The device is highly

eﬃcient and uses minimal PCB area. It uses pseudo-ﬁxed

frequency adaptive on-time operation to provide fast

transient response.

Conﬁgurable 150mA LDO with bypass capability

TC compensated R_DS(ON)sensed current limit

Pseudo-ﬁxed frequency adaptive on-time control

Designed for use with ceramic capacitors

Programmable V_INUVLO threshold

Independent enable for switcher and LDO

Selectable ultra-sonic power-save (SC417)

Selectable power-save (SC427)

Internal soft-start and soft-shutdown at output

Internal reference — 1% tolerance

Over-voltage/under-voltage fault protection

Power good output

The SC417/SC427 supports using standard capacitor types

such as electrolytic or special polymer in addition to

ceramic, at switching frequencies up to 1MHz. The pro-

grammable frequency, synchronous operation, and select-

able power-save provide high eﬃciency operation over a

wide load range.

The LDO output is programmable from 0.75V to 5.25V

using external resistors. The bias voltage for the device

can be supplied by the on-chip LDO when V_IN> 4.5V, or by

an external 5V supply. When a separate source is used as

the bias supply, the LDO can be programmed to provide a

diﬀerent voltage.

Lead-free 5x5mm, 32 Pin MLPQ package

Fully WEEE and RoHS compliant

Applications

Notebook, desktop, tablet, and server computers

Networking and telecommunication equipment

Printers, DSL, and STB applications

Embedded applications

Power supply modules

Point of load power supplies

Additional features include cycle-by-cycle current limit,

soft-start, under and over-voltage protection, program-

mable over-current protection, soft shutdown, and select-

able power-save. The device also provides separate enable

inputs for the PWM controller and LDO as well as a power

good output for the PWM controller.

The input voltage can range from 3V to 28V. The wide

input voltage range, programmable frequency, and pro-

grammable LDO make the device extremely ﬂexible and

easy to use in a broad range of applications. Support is

provided for single cell or multi-cell battery systems in

addition to traditional DC power supply applications.

November 11, 2008

1

SC417/SC427

Typical Application Circuit

ENABLE/

PSAVE

ENABLE

LDO

PGOOD

RILIM

7.5KΩ

RTON

154KΩ

Note:

PAD 1

V5V is tied to VLDO

AGND

24

23

22

21

20

19

18

17

1

2

LX

FB

FBL

V5V

3

4

5

6

PGND

AGND

VOUT

VIN

RLDO1

SC417/SC427

56.2KΩ

7

8

VLDO

BST

RLDO2

1μF

100nF

PAD 3

10KΩ

LX

CBST

0.1μF

VIN

+12V

RGND

0

CIN

22μF

A separate 5V supply for the

SC417/SC427 is not required

if VLDO is used to power the

device.

1.05V @ 10A, 250kHz

L1

0.88μH

+

COUT1

220μF

15mΩ

COUT2

220μF

15mΩ

VOUT

10nF

CFF

100pF

RFB1

11KΩ

RFB2

10KΩ

Key Components

Manufacturer

Component

Value

Part Number

Web

CIN

COUT1, COUT2

L1

22μF/25V

220μF/15mΩ/6.3V

0.88μH/20A

Murata

Panasonic

Vishay

www.murata.com

www.panasonic.com

www.vishay.com

GRM32ER61E226KE15L

EEFUE0J221R

IHLP4040DZERR88M11

All other small signal components (resistors and capacitors) are standard SMT devices.

2

SC417/SC427

Pin Conﬁguration

Ordering Information

Device

Package

SC417MLTRT⁽¹⁾⁽²⁾

SC427MLTRT⁽¹⁾⁽²⁾

SC417EVB

MLPQ-32 5X5

Evaluation Board

32

31

30

29

28

27

26

25

Top View

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

LX

FB

FBL

LX

SC427EVB

Notes:

1) Available in tape and reel only. A reel contains 3000 devices.

2) Lead-free packaging only. Device is WEEE and RoHS compliant.

AGND

PAD 1

V5V

PGND

AGND

VOUT

VIN

LX

PAD 3

VIN

PAD 2

VLDO

BST

9

10

11

12

13

14

15

16

MLPQ-32; 5x5, 32 LEAD

Marking Information

SC417

SC427

yyww.

xxxxxx

yyww.

xxxxxx

yyww. = Date Code

xxxxxx = Semtech Lot Number

3

SC417/SC427

Absolute Maximum Ratings⁽¹⁾

Recommended Operating Conditions

LX to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30

LX to PGND (V) (transient — 100ns) . . . . . . . . . . . -2 to +30

VIN to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30

EN/PSV, PGOOD, ILIM, to GND (V). . . . . . -0.3to+(V5V+0.3)

VOUT, VLDO, FB, FBL, to GND (V). . . . . . . -0.3to+(V5V+0.3)

V5V to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6

TON to PGND (V). . . . . . . . . . . . . . . . . . . . . -0.3 to +(V5V - 1.5)

ENL (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to V_IN

BST to LX (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0

BST to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +35

AGND to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3

Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 28

V5V to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5

VOUT to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 to 5.5

Thermal Information

Storage Temperature (°C). . . . . . . . . . . . . . . . . . . . -60 to +150

Maximum Junction Temperature (°C) . . . . . . . . . . . . . . . 150

Operating Junction Temperature (°C) . . . . . . -40 to +125

Thermal resistance, junction to ambient ⁽²⁾(°C/W)

High-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Low-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

PWM controller and LDO thermal resistance . . . . . 50

Peak IR Reﬂow Temperature (°C) . . . . . . . . . . . . . . . . . . . . 260

Exceeding the above speciﬁcations may result in permanent damage to the device or device malfunction. Operation outside of the parameters

speciﬁed in the Electrical Characteristics section is not recommended.

NOTES:

(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.

(2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.

Electrical Characteristics

Unless speciﬁed: V_IN=12V, T_A= +25°C for Typ, -40 to +85 °C for Min and Max, T_J< 125°C, V5V = +5V, Typical Application Circuit

Parameter

Conditions

Min

Typ

Max Units

Input Supplies

Input Supply Voltage

V5V Voltage

3

28

5.5

V

4.5

Sensed at ENL pin, rising edge

Sensed at ENL pin, falling edge

EN/PSV = High

2.40

2.235

2.60

2.40

0.2

2.95

2.565

VIN UVLO Threshold⁽¹⁾

VIN UVLO Hysteresis

V5V UVLO Threshold

V5V UVLO Hysteresis

VIN Supply Current

V

Measured at V5V pin, rising edge

Measured at V5V pin, falling edge

3.7

3.5

3.9

4.1

V

3.6

3.75

0.3

V

ENL , EN/PSV = 0V, V_IN= 28V

8.5

20

μA

Standby mode; ENL=V5V, EN/PSV = 0V

130

4

SC417/SC427

Electrical Characteristics (continued)

Parameter

Conditions

Min

Typ

Max Units

Input Supplies (continued)

ENL , EN/PSV = 0V

3

2

7

μA

SC417, EN/PSV = V5V, no load (f_SW= 25kHz),

_FB> 500mV⁽²⁾

V

V5V Supply Current

mA

SC427, EN/PSV = V5V, no load, V_FB> 500mV⁽²⁾

f_SW= 250kHz, EN/PSV = ﬂoating , no load⁽²⁾

static V_INand load, 0 to +85 °C

0.7

10

0.496

0.495

200

0.500

0.504

0.505

1000

V

FB On-Time Threshold

Frequency Range

static V_INand load, -40 to +85 °C

continuous mode operation

kHz

Ω

minimum f_SW, (SC417 only), EN/PSV = V5V, no load

25

10

Bootstrap Switch Resistance

Timing

continuous mode operation,

_IN= 15V, V_OUT= 5V, f_SW= 300kHz, R_TON= 133kΩ

On-Time

999

1110

1220

ns

V

Minimum On-Time ⁽²⁾

Minimum Oﬀ-Time ⁽²⁾

Soft-Start

50

ns

250

Soft-Start Ramp Time ⁽²⁾

Analog Inputs/Outputs

VOUT Input Resistance

Current Sense

850

500

0

μs

kΩ

mV

Zero-Crossing Detector Threshold

Power Good

LX - PGND

-3

+3

upper limit, V_FB> internal 500mV reference

lower limit, V_FB< internal 500mV reference

+20

-10

2

%

Power Good Threshold

Start-Up Delay Time

ms

ꢀs

ꢀA

Ω

Fault (noise immunity) Delay Time⁽²⁾

Leakage

5

1

Power Good On-Resistance

10

5

SC417/SC427

Electrical Characteristics (continued)

Parameter

Conditions

R_ILIM= 5.9k Ω

Min

6

Typ

Max Units

Fault Protection

Valley Current Limit

I_LIMSource Current

I_LIMComparator Oﬀset

8

10

0

10

A

μA

mV

with respect to AGND

-10

+10

V

_FBwith respect to internal 500mV reference,

8 consecutive clocks

Output Under-Voltage Fault

-25

%

Smart Power-save Protection Threshold ⁽²⁾

Over-Voltage Protection Threshold

Over-Voltage Fault Delay⁽²⁾

Over-Temperature Shutdown⁽²⁾

Logic Inputs/Outputs

V_FBwith respect to internal 500mV reference

+10

+20

5

%

μs

°C

10°C hysteresis

150

Logic Input High Voltage

Logic Input Low Voltage

EN/PSV Input Bias Current

ENL Input Bias Current

EN/PSV, ENL

2.0

-10

V

0.4

+10

18

V

EN/PSV= V5V or AGND

V_IN= 28V

μA

11

FBL, FB Input Bias Current

Linear Regulator (LDO)

FBL Accuracy

FBL, FB = V5V or AGND

-1

+1

VLDO load = 10mA

0.735

0.75

85

0.765

V

Start-up and foldback, V_IN= 12V

operating current limit, V_IN= 12V

LDO Current Limit

mA

135

-140

-450

200

VLDO to VOUT Switch-over Threshold ⁽³⁾

VLDO to VOUT Non-switch-over Threshold ⁽³⁾

VLDO to VOUT Switch-over Resistance

+140

+450

mV

Ω

V

_OUT= +5V

2

LDO Drop Out Voltage ⁽⁴⁾

from V_INto V_VLDO, V_VLDO= +5V, I_VLDO= 100mA

1.2

V

Notes:

(1) V_INUVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference.

(2) Guaranteed by design.

(3) The switch-over threshold is the maximum voltage diﬀerential between the VLDO and VOUT pins which ensures that VLDO will internally

switch-over to VOUT. The non-switch-over threshold is the minimum voltage diﬀerential between the VLDO and VOUT pins which ensures

that VLDO will not switch-over to VOUT.

(4) The LDO drop out voltage is the voltage at which the LDO output drops 2% below the nominal regulation point.

6

SC417/SC427

Typical Characteristics

Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC417).

Eﬃciency vs. Load — Powersave Mode

Eﬃciency vs. Load — Forced Continuous Mode

Internally biased at V_LDO= 5V, V_IN= 12V, V_OUT= 1.050V

100

90

80

70

60

50

100

90

80

70

60

50

85%

2.0

3.0

5.0

0.0

1.0

6.0

7.0

8.0

9.0

4.0

10.0

0.10

1.00

10.00

I_OUT(A)

I

_OUT(A)

Eﬃciency vs. Load — Powersave Mode

V_OUTvs. Load — Forced Continuous Mode

Externally biased at V_IN= 12V, V5V = 5V, V_OUT= 1.050V

100

90

80

70

60

50

Internally biased at V_LDO= 5V, V_IN= 12V, V_OUT= 1.050V

1.100

1.075

1.050

85%

+1%

-1%

1.025

1.000

0.10

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

10.0

1.00

10.00

9.0

I_OUT(A)

Frequency vs. Load — Forced Continuous Mode

V_RIPPLEvs. Load — Forced Continuous Mode

Internally biased at V_LDO= 5V, V_IN= 12V, V_OUT= 1.050V

400

0.20

0.15

0.10

0.05

0.00

350

300

250

200

150

100

+15%

-15%

50mV

VOUT_P-P

0.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

1.0

10.0

0.0

4.0

7.0

1.0

2.0

5.0

6.0

9.0

10.0

3.0

8.0

I

_OUT(A)

I_OUT(A)

7

SC417/SC427

Typical Characteristics (continued)

Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC417).

V_OUTvs. Load — Powersave Mode

V_OUTvs. Line — Forced Continuous Mode

Internally biased at V_LDO= 5V, V_IN= 12V, V_OUT= 1.050V

1.100

1.075

1.050

1.025

1.000

1.100

1.075

1.050

1.025

1.000

+1%

-1%

+1%

-1%

6.0

8.0

12.0

0.10

10.00

10.0

14.0

16.0

18.0

20.0

22.0

24.0

1.00

I_OUT(A)

V_IN(V)

Ultrasonic Powersave Mode — No Load

Forced Continuous Mode — No Load

V_IN= 12V, V_OUT= 1.05V, I_OUT= 0A, V_LDO= V_5V= ENL = 5V, EN/PSV= ﬂoat

V

_IN= 12V, V_OUT= 1.05V, I_OUT= 0A, V_LDO= V_5V= EN/PSV= ENL = 5V

1.078V

Δ V ~ 30mV

Δ V ~ 29mV

1.073V

1.044V

(50mV/div)

(10V/div)

1.048V

f=227.4kHz

f=26.22kHz

(10V/div)

(5V/div)

(10V/div)

(5V/div)

Time (10μs/div)

Time (2μs/div)

Enabled Loaded Output — Full Scale

Enabled Loaded Output — Power Good True

V

_IN= 12V, V_OUT= 1.05V, I_OUT= 1A, V_LDO= V_5V= ENL = 5V. EN/PSV= 5V

V

_IN= 12V, V_OUT= 1.05V, I_OUT= 1A, V_LDO= V_5V= ENL = 5V. EN/PSV= 5V

1.05V

ΔV/ΔT ~

1.4V/ms

0V

(50mV/div)

0V

(500mV/div)

(10V/div)

(5V/div)

(10V/div)

(5V/div)

~2ms

Time (400μs/div)

Time (100μs/div)

8

SC417/SC427

Typical Characteristics (continued)

Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC417).

Transient Response — Load Falling

Transient Response — Load Rising

V

_IN= 12V, V_OUT= 1.05V, I_OUT= 10A to 0A, V_LDO= V_5V= EN/PSV= ENL = 5V

V

_IN= 12V, V_OUT= 1.05V, I_OUT= 0A to 10A, V_LDO= V_5V= EN/PSV= ENL = 5V

1.101V

1.063V

(50mV/div)

(10V/div)

1.055V

1.025V

(10V/div)

(10A/div)

(5V/div)

Time (10μs/div)

Output Under-voltage Response — Normal Operation

Output Over-current Response — Normal Operation

V_IN= 12V, V_OUT= 1.05V, I_OUT= 0A, V_LDO= V_5V= ENL = 5V, ﬂoating EN/PSV

V_IN= 12V, V_OUT= 1.05V, V_LDO= V_5V= ENL = 5V, EN/PSV= ﬂoating; I_OUTramped to trip point

1.05V

(500mV/div)

(10V/div)

0V

(500mV/div)

(10A/div)

V₂~710mV

I

_OUT= 10.37A

(10V/div)

(5V/div)

Time (100μs/div)

Self-Biased Start-Up — Power Good True

V_IN= 0V to 12V step, V_OUT= 1.05V, I_OUT= 0A, V_LDO= V_5V= EN/PSV= ENL = 5V

(10V/div)

1.05V

ΔV/ΔT ~

(500mV/div)

1.4 V/ms

0V

(2V/div)

(5V/div)

Time (400μs/div)

9

SC417/SC427

Typical Characteristics (continued)

Characteristics in this section are based on using the Typical Application Circuit on page 2.

Shorted Output Response — Power-UP Operation

Shorted Output Response — Normal Operation

V_IN= 12V, V_OUT= 1.05V, I_OUT= 0A, V_LDO= V_5V= EN/PSV= ENL = 5V

1.05V

~1.7ms

(500mV/div)

0V

(10A/div)

(10V/div)

(10A/div)

(10V/div)

(5V/div)

Time (400μs/div)

Time (40μs/div)

10

SC417/SC427

Pin Descriptions

Pin #

Pin Name

Pin Function

Feedback input for switching regulator used to program the output voltage — connect to an external resis-

tor divider from VOUT to AGND.

1

FB

Feedback input for the LDO — connect to an external resistor divider from VLDO to AGND — used to pro-

gram the LDO output.

2

3

FBL

V5V

5V power input for internal analog circuits and gate drives — connect to external 5V supply or conﬁgure

the LDO for 5V and connect to VLDO.

4, 30, PAD 1

5

AGND

VOUT

Analog ground

Switcher output voltage sense pin — also the input to the internal switch-over between VOUT and VLDO.

6, 9-11,

PAD 2

VIN

VLDO

BST

DH

Input supply voltage

LDO output

7

8

Bootstrap pin — connect a capacitor from BST to LX to develop the ﬂoating supply for the high-side gate

drive.

12

High-side gate drive — do not connect this pin

Switching (phase) node

13, 23-25, 28,

PAD 3

LX

14

DL

Low-side gate drive — do not connect this pin

Power ground

15-22

PGND

Open-drain power good indicator — high impedance indicates power is good. An external pull-up

resistor is required.

26

27

PGOOD

ILIM

Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LX.

Enable/power-save input for the switching regulator — connect to AGND to disable the switching regulator.

Float to operate in forced continuous mode (power-save disabled). SC417 — connect to V5V to operate with

ultra-sonic power-save mode enabled. SC427 — connect to V5V to operate with power-save mode enabled

with no minimum frequency.

29

EN/PSV

31

32

TON

ENL

On-time programming input — set the on-time by connecting through a resistor to AGND

Enable input for the LDO — connect ENL to AGND to disable the LDO. Drive with logic to +3V for logic con-

trol, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND.

11

SC417/SC427

Block Diagram

VIN

A

V5V

3

EN/PSV

29

PGOOD

26

V5V

V_IN

V5V

Bootstrap

Switch

8

BST

AGND

D

Control & Status

Reference

Soft Start

DL

12 DH

Hi-side

MOSFET

B

LX

Gate Drive

Control

On- time

Generator

1

FB

V5V

Lo-side

MOSFET

FB Comparator

C

PGND

ILIM

31

5

TON

Zero Cross Detector

Valley Current Limit

VOUT

27

Bypass Comparator

A

V_IN

14

DL

7

2

VLDO

FBL

Y

B

LDO

VLDO Switchover MUX

32

A = connected to pins 6, 9-11, PAD 2

ENL

B = connected to pins 13, 23-25, 28, PAD 3

C = connected to pins 15-22

D = connect to pins 4, 30, PAD 1

12

SC417/SC427

Applications Information

The adaptive on-time is determined by an internal one-

shot timer. When the one-shot is triggered by the output

ripple, the device sends a single on-time pulse to the high-

side MOSFET. The pulse period is determined by V_OUTand

V_IN; the period is proportional to output voltage and

inversely proportional to input voltage. With this adaptive

on-time arrangement, the device automatically antici-

pates the on-time needed to regulate V_OUTfor the present

V_INcondition and at the selected frequency.

Synchronous Buck Converter

The SC417/SC427 is a step down synchronous DC-DC buck

converter with integrated power MOSFETs and a program-

mable LDO. The device is capable of 10A operation at very

high eﬃciency. A space saving 5x5 (mm) 32-pin package

is used. The programmable operating frequency range of

200kHz to 1MHz enables optimizing the conﬁguration for

PCB area and eﬃciency.

The buck controller uses a pseudo-ﬁxed frequency adap-

tive on-time control. This control method allows fast tran-

sient response which permits the use of smaller output

capacitors.

The advantages of adaptive on-time control are:

• ^{Predictable operating frequency compared to}

other variable frequency methods.

• ^{Reduced component count by eliminating the}

error ampliﬁer and compensation components.

• ^{Reduced component count by removing the}

need to sense and control inductor current.

• ^{Fast transient response — the response time is}

controlled by a fast comparator instead of a typi-

cally slow error ampliﬁer.

Input Voltage Requirements

The SC417/SC427 requires two input supplies for normal

operation: VIN and V5V. VIN operates over the wide range

from 3V to 28V. V5V requires a 5V supply input that can be

an external source or the internal LDO configured to

supply 5V.

• ^{Reduced output capacitance due to fast tran-}

Psuedo-ﬁxed Frequency Adaptive On-time Control

The PWM control method used by the SC417/SC427 is

pseudo-ﬁxed frequency, adaptive on-time, as shown in

Figure 1. The ripple voltage generated at the output

capacitor ESR is used as a PWM ramp signal. This ripple is

used to trigger the on-time of the controller.

sient response

One-Shot Timer and Operating Frequency

The one-shot timer operates as shown in Figure 2. The FB

Comparator output goes high when V_FBis less than the

internal 500mV reference. This feeds into the gate drive

and turns on the high-side MOSFET, and also starts the

one-shot timer. The one-shot timer uses an internal com-

parator and a capacitor. One comparator input is con-

nected to V_OUT, the other input is connected to the

capacitor. When the on-time begins, the internal capaci-

tor charges from zero volts through a current which is

proportional to V_IN. When the capacitor voltage reaches

TON

V_IN

V_LX

C_IN

Q1

Q2

V_FB

FB Threshold

V_OUT

V_LX

L

V

_OUT, the on-time is completed and the high-side MOSFET

turns oﬀ.

ESR

FB

+

C_OUT

Figure 1 — PWM Control Method, V_OUTRipple

13

SC417/SC427

Applications Information (continued)

Note that this control method regulates the valley of the

output ripple voltage, not the DC value. The DC output

voltage V_OUTis oﬀset by the output ripple according to the

following equation.

Gate

Drives

V_IN

FB Comparator

FB

-

500mV

+

Q1

DH

V_OUT

FB

L

V_LX

Q2

V_OUT

V_IN

ESR

C_OUT

§

·

R₁

R₂

V

RIPPLE

§

¨

·

¸

¨

¸

V_OUT 0.5u 1ꢁ

ꢁ

One-Shot

Timer

¨

©

+

DL

2

©

¹

R_TON

Enable and Power-save Inputs

On-time = K x R_TONx (V_OUT/V_IN)

The EN/PSV and ENL inputs are used to enable or disable

the switching regulator and the LDO. When EN/PSV is low

(grounded), the switching regulator is oﬀ and in its lowest

power state. When oﬀ, the output of the switching regula-

tor soft-discharges the output into a 15Ω internal resistor

via the V_OUTpin. When EN/PSV is allowed to ﬂoat, the pin

voltage will ﬂoat to 1.5V. The switching regulator turns on

with power-save disabled and all switching is in forced

continuous mode.

Figure 2 — On-Time Generation

This method automatically produces an on-time that is

proportional to V_OUTand inversely proportional to V_IN.

Under steady-state conditions, the switching frequency

can be determined from the on-time by the following

equation.

V_OUT

f_SW

T_ONu V

IN

When EN/PSV is high (above 2.0V) for SC417, the switch-

ing regulator turns on with ultra-sonic power-save

enabled. The SC417 ultra-sonic power-save operation

maintains a minimum switching frequency of 25kHz, for

applications with stringent audio requirements.

The SC417/SC427 uses an external resistor to set the on-

time which indirectly sets the frequency. The on-time can

be programmed to provide operating frequency from

200kHz to 1MHz using a resistor between the TON pin and

ground. The resistor value is selected by the following

equation.

When EN/PSV is high (above 2.0V) for SC427, the switch-

ing regulator turns on with power-save enabled. The

SC427 power-save operation is designed to maximize

eﬃciency at light loads with no minimum frequency limits.

This makes the SC427 an excellent choice for portable and

battery-operated systems.

(TONꢀ10ns)uV_IN

R_TON

25pFuV_OUT

The maximum R_TONvalue allowed is shown by the follow-

ing equation.

The ENL input is used to control the internal LDO. This

input serves a second function by acting as a V_INULVO

sensor for the switching regulator.

V

IN_MIN

R_{TON_MAX}

15PA

V_OUTVoltage Selection

When ENL is low (grounded), the LDO is oﬀ. When ENL is

a logic high but below the VIN UVLO threshold (2.6V

typical), then the LDO is on and the switcher is oﬀ. When

ENL is above the VIN UVLO threshold, the LDO is enabled

and the switcher is also enabled if the EN/PSV pin is not

grounded.

The switcher output voltage is regulated by comparing

V

_OUTas seen through a resistor divider at the FB pin to the

internal 500mV reference voltage, see Figure 3.

V_OUT

To FB pin

R₁

R₂

Forced Continuous Mode Operation

The SC417/SC427 operates the switcher in Forced

Continuous Mode (FCM) by ﬂoating the EN/PSV pin (see

Figure 4). In this mode one of the power MOSFETs is

Figure 3 — Output Voltage Selection

14

SC417/SC427

Applications Information (continued)

always on, with no intentional dead time other than to

avoid cross-conduction. This feature results in uniform

frequency across the full load range with the trade-oﬀ

being poor eﬃciency at light loads due to the high-fre-

quency switching of the MOSFETs.

Because the on-times are forced to occur at intervals no

greater than 40ꢀs, the frequency will not fall below

~25kHz. Figure 5 shows ultra-sonic power-save

operation.

FB Ripple

Voltage (V_FB)

FB threshold

(500mV)

minimum f_SW~ 25kHz

FB Ripple

Voltage (V_FB

)

FB threshold

(500mV)

DC Load Current

Inductor

Current

(0A)

Inductor

Current

DH on-time is triggered when

V_FBreaches the FB Threshold.

On-time

(T_ON

DH On-time is triggered when

V_FBreaches the FB Threshold

On-time

(T_ON

)

DH

DL

DH

DL

40μs time-out

After the 40μsec time-out, DL drives high if V_FB

DL drives high when on-time is completed.

DL remains high until V_FBfalls to the FB threshold.

has not reached the FB threshold.

Figure 5 — Ultrasonic Power-save Operation

Figure 4 — Forced Continuous Mode Operation

Power-save Mode Operation (SC427)

Ultra-sonic Power-save Operation (SC417)

The SC427 provides power-save operation at light loads

with no minimum operating frequency. With power-save

enabled, the internal zero crossing comparator monitors

the inductor current via the voltage across the low-side

MOSFET during the oﬀ-time. If the inductor current falls to

zero for 8 consecutive switching cycles, the controller

enters power-save operation. It will turn oﬀ the low-side

MOSFET on each subsequent cycle provided that the

current crosses zero. At this time both MOSFETs remain

oﬀ until V_FBdrops to the 500mV threshold. Because the

MOSFETs are oﬀ, the load is supplied by the output capaci-

tor. If the inductor current does not reach zero on any

switching cycle, the controller immediately exits power-

save and returns to forced continuous mode. Figure 6

shows power-save operation at light loads.

The SC417 provides ultra-sonic power-save operation at

light loads, with the minimum operating frequency ﬁxed

at 25kHz. This is accomplished using an internal timer that

monitors the time between consecutive high-side gate

pulses. If the time exceeds 40ꢀs, DL drives high to turn the

low-side MOSFET on. This draws current from V_OUTthrough

the inductor, forcing both V_OUTand V_FBto fall. When V_FB

drops to the 500mV threshold, the next DH on-time is trig-

gered. After the on-time is completed the high-side

MOSFET is turned oﬀ and the low-side MOSFET turns on.

The low-side MOSFET remains on until the inductor

current ramps down to zero, at which point the low-side

MOSFET is turned oﬀ.

15

SC417/SC427

Applications Information (continued)

V_OUTdrifts up to due to leakage

current flowing into C_OUT

Dead time varies

according to load

V_OUTdischarges via inductor

and low-side MOSFET

FB Ripple

Smart Power Save

Threshold (550mV)

Voltage

Normal V_OUTripple

FB threshold

(V_FB)

FB

threshold

(500mV)

DH and DL off

Inductor

Current

Zero (0A)

High-side

Drive (DH)

Single DH on-time pulse

after DL turn-off

On-time (T_ON

)

Low-side

DH On-time is triggered when

V_FBreaches the FB Threshold.

Drive (DL)

DH

DL turns on when Smart

PSAVE threshold is reached

Normal DL pulse after DH

on-time pulse

DL turns off when FB

threshold is reached

DL

Figure 7 — Smart Power-save

DL drives high when on-time is completed.

DL remains high until inductor current reaches zero.

Figure 6 — Power-save Operation

Current Limit Protection

Smart Power-save Protection

The device features programmable current limiting, which

is accomplished by using the RDSON of the lower MOSFET

for current sensing. The current limit is set by R_ILIMresistor.

The R_ILIMresistor connects from the ILIM pin to the LX pin

which is also the drain of the low-side MOSFET. When the

low-side MOSFET is on, an internal ~10μA current ﬂows

from the ILIM pin and through the R_ILIMresistor, creating a

voltage drop across the resistor. While the low-side

MOSFET is on, the inductor current ﬂows through it and

creates a voltage across the RDS_(ON). The voltage across the

MOSFET is negative with respect to ground. If this MOSFET

voltage drop exceeds the voltage across R_ILIM, the voltage

at the ILIM pin will be negative and current limit will acti-

vate. The current limit then keeps the low-side MOSFET on

and will not allow another high-side on-time, until the

current in the low-side MOSFET reduces enough to bring

the ILIM voltage back up to zero. This method regulates

the inductor valley current at the level shown by ILIM in

Figure 8.

Active loads may leak current from a higher voltage into

the switcher output. Under light load conditions with

power-save enabled, this can force V_OUTto slowly rise and

reach the over-voltage threshold, resulting in a hard shut-

down. Smart power-save prevents this condition. When

the FB voltage exceeds 10% above nominal (exceeds

550mV), the device immediately disables power-save, and

DL drives high to turn on the low-side MOSFET. This draws

current from V_OUTthrough the inductor and causes V_OUTto

fall. When V_FBdrops back to the 500mV trip point, a normal

T_ONswitching cycle begins. This method prevents a hard

OVP shutdown and also cycles energy from V_OUTback to

V_IN. It also minimizes operating power by avoiding forced

conduction mode operation. Figure 7 shows typical wave-

forms for the Smart Power-save feature.

16

SC417/SC427

Applications Information (continued)

This prevents negative inductor current, allowing the

device to start into a pre-biased output.

I_PEAK

I_LOAD

I_LIM

Power Good Output

The power good (PGOOD) output is an open-drain output

which requires a pull-up resistor. When the output voltage

is 10% below the nominal voltage, PGOOD is pulled low. It

is held low until the output voltage returns above -8% of

nominal. PGOOD is held low during start-up and will not

be allowed to transition high until soft-start is completed

(when V_FBreaches 500mV) and typically 2ms has passed.

Time

Figure 8 — Valley Current Limit

Setting the valley current limit to 10A results in a peak

inductor current of 10A plus peak ripple current. In this

situation, the average (load) current through the inductor

is 10A plus one-half the peak-to-peak ripple current.

PGOOD will transition low if the V_FBpin exceeds +20% of

nominal, which is also the over-voltage shutdown thresh-

old (600mV). PGOOD also pulls low if the EN/PSV pin is

low when V5V is present.

The internal 10μA current source is temperature compen-

sated at 4100ppm in order to provide tracking with the

Output Over-Voltage Protection

RDS_(ON)

.

Over-voltage protection becomes active as soon as the

device is enabled. The threshold is set at 500mV + 20%

(600mV). When V_FBexceeds the OVP threshold, DL latches

high and the low-side MOSFET is turned on. DL remains

high and the controller remains oﬀ, until the EN/PSV input

is toggled or V5V is cycled. There is a 5μs delay built into

the OVP detector to prevent false transitions. PGOOD is

also low after an OVP event.

The R_ILIMvalue is calculated by the following equation.

R_ILIM= 735 x I_LIM

Note that because the low-side MOSFET with low RDS_(ON)

is used for current sensing, the PCB layout, solder connec-

tions, and PCB connection to the LX node must be done

carefully to obtain good results. Refer to the layout guide-

lines for information.

Output Under-Voltage Protection

When V_FBfalls 25% below its nominal voltage (falls to

375mV) for eight consecutive clock cycles, the switcher is

shut oﬀ and the DH and DL drives are pulled low to tri-

state the MOSFETs. The controller stays oﬀ until EN/PSV is

toggled or V5V is cycled.

Soft-Start of PWM Regulator

Soft-start is achieved in the PWM regulator by using an

internal voltage ramp as the reference for the FB

Comparator. The voltage ramp is generated using an

internal charge pump which drives the reference from

zero to 500mV in ~1.2mV increments, using an internal

~500kHz oscillator. When the ramp voltage reaches

500mV, the ramp is ignored and the FB comparator

switches over to a ﬁxed 500mV threshold. During soft-start

the output voltage tracks the internal ramp, which limits

the start-up inrush current and provides a controlled soft-

start proﬁle for a wide range of applications. Typical soft-

start ramp time is 850μs.

V5V UVLO, and POR

Under-Voltage Lock-Out (UVLO) circuitry inhibits switch-

ing and tri-states the DH/DL drivers until V5V rises above

3.9V. An internal Power-On Reset (POR) occurs when V5V

exceeds 3.9V, which resets the fault latch and soft-start

counter to prepare for soft-start. The SC417/SC427 then

begins a soft-start cycle. The PWM will shut oﬀ if V5V falls

below 3.6V.

LDO Regulator

The device features an integrated LDO regulator with a

programmable output voltage from 0.75V to 5.25V using

During soft-start the regulator turns off the low-side

MOSFET on any cycle if the inductor current falls to zero.

17

SC417/SC427

Applications Information (continued)

external resistors. The feedback pin (FBL) for the LDO is

regulated to 750mV. There is also an enable pin (ENL) for

the LDO that provides independent control. The LDO

voltage can also be used to provide the bias voltage for

the switching regulator.

V_VLDOFinal

Voltage regulating with

~200mA current limit

90% of V_VLDOFinal

Constant current startup

VLDO

To FBL pin

R_LDO1

Figure 10 — LDO Start-Up

R_LDO2

LDO Switch-Over Operation

The SC417/SC427 includes a switch-over function for the

LDO. The switch-over function is designed to increase

eﬃciency by using the more eﬃcient DC-DC converter to

power the LDO output, avoiding the less efficient LDO

regulator when possible. The switch-over function con-

nects the VLDO pin directly to the VOUT pin using an

internal switch. When the switch-over is complete the

LDO is turned oﬀ, which results in a power savings and

maximizes eﬃciency. If the LDO output is used to bias the

SC417/SC427, then after switch-over the device is self-

powered from the switching regulator with the LDO

turned oﬀ.

Figure 9 — LDO Start-Up

The LDO output voltage is set by the following equation.

§

·

R_LDO1

R_LDO2

¨

¸

VLDO 750mV u 1ꢁ

¨

©

¹

A minimum capacitance of 1μF referenced to AGND is

normally required at the output of the LDO for stability. If

the LDO is providing bias power to the device, then a

minimum 0.1μF capacitor referenced to AGND is required

along with a minimum 1.0μF capacitor referenced to

PGND to ﬁlter the gate drive pulses. Refer to the layout

guidelines section.

The switch-over logic waits for 32 switching cycles before

it starts the switch-over. There are two methods that

determine the switch-over of V_LDOto V_OUT

.

In the ﬁrst method, the LDO is already in regulation and

the DC-DC converter is later enabled. As soon as the

PGOOD output goes high, the 32 cycles are started. The

voltages at the VLDO and VOUT pins are then compared;

if the two voltages are within 300mV of each other, the

VLDO pin connects to the VOUT pin using an internal

switch, and the LDO is turned oﬀ.

LDO Start-up

Before start-up, the LDO checks the status of the following

signals to ensure proper operation can be maintained.

1. ENL pin

2. VLDO output

3. V_INinput voltage

In the second method, the DC-DC converter is already

running and the LDO is enabled. In this case the 32 cycles

are started as soon as the LDO reaches 90% of its ﬁnal

value. At this time, the VLDO and VOUT pins are compared,

and if within 300mV the switch-over occurs and the LDO

is turned oﬀ.

When the ENL pin is high and V_INis above the UVLO point,

the LDO will begin start-up. During the initial phase, when

the LDO output voltage is near zero, the LDO initiates a

current-limited start-up (typically 85mA) to charge the

output capacitor. When V_LDOhas reached 90% of the ﬁnal

value (as sensed at the FBL pin), the LDO current limit is

increased to ~200mA and the LDO output is quickly driven

to the nominal value by the internal LDO regulator.

18

SC417/SC427

Applications Information (continued)

Switch-over Limitations on VOUT and VLDO

Because the internal switch-over circuit always compares

the VOUT and VLDO pins at start-up, there are limitations

on permissible combinations of VOUT and VLDO. Consider

the case where VOUT is programmed to 1.5V and VLDO is

programmed to 1.8V. After start-up, the device would

connect VOUT to VLDO and disable the LDO, since the two

voltage are within the 300mV switch-over window. To

avoid unwanted switch-over, the minimum difference

between the voltages for VOUT and VLDO should be

500mV.

ENL pin and VIN UVLO

The ENL pin also acts as the switcher under-voltage

lockout for the V_INsupply. The V_INUVLO voltage is pro-

grammable via a resistor divider at the VIN, ENL and AGND

pins.

ENL is the enable/disable signal for the LDO. In order to

implement the VIN UVLO there is also a timing require-

ment that needs to be satisﬁed.

If the ENL pin transitions low within 2 switching cycles and

is < 1V, then the LDO will turn oﬀ but the switcher remains

on. If ENL goes below the VIN UVLO threshold and stays

above 1V, then the switcher will turn off but the LDO

remains on.

It is not recommended to use the switch-over feature for

an output voltage less than 3V since this does not provide

suﬃcient voltage for the gate-source drive to the internal

p-channel switch-over MOSFET.

The VIN UVLO function has a typical threshold of 2.6V on

the VIN rising edge. The falling edge threshold is 2.4V.

Switch-over MOSFET Parasitic Diodes

The switch-over MOSFET contains parasitic diodes that

are inherent to its construction, as shown in Figure 11.

Note that it is possible to operate the switcher with the

LDO disabled, but the ENL pin must be below the logic

low threshold (0.4V maximum).

Switchover

control

MOSFET

V_OUT

V_LDO

ENL Logic Control of PWM Operation

When the ENL input is driven above 2.6V, it is impossible

to determine if the LDO output is going to be used to

power the device or not. In self-powered operation where

the LDO will power the device, it is necessary during the

LDO start-up to hold the PWM switching oﬀ until the LDO

has reached 90% of the ﬁnal value. This is to prevent over-

loading the current-limited LDO output during the LDO

start-up. However, if the switcher was previously operat-

ing (with EN/PSV high but ENL at ground, and V5V sup-

plied externally), then it is undesirable to shut down the

switcher.

Parasitic diode

V5V

Figure 11— Switch-over MOSFET Parasitic Diodes

There are some important design rules that must be fol-

lowed to prevent forward bias of these diodes. The fol-

lowing two conditions need to be satisﬁed in order for the

parasitic diodes to stay oﬀ.

• ^{V5V ≥ V}_LDO

• ^{V5V ≥ V}_OUT

To prevent this, when the ENL input is taken above 2.6V

(above the VIN UVLO threshold), the internal logic checks

the PGOOD signal. If PGOOD is high, then the switcher is

already running and the LDO will run through the start-up

cycle without aﬀecting the switcher. If PGOOD is low, then

the LDO will not allow any PWM switching until the LDO

output has reached 90% of it’s ﬁnal value.

If either V_LDOor V_OUTis higher than V5V, then the respective

diode will turn on and the SC417/SC427 operating current

will flow through this diode. This has the potential of

damaging the device.

19

SC417/SC427

Applications Information (continued)

• f_SW= 250kHz

Using the On-chip LDO to Bias the SC417/SC427

The following steps must be followed when using the on-

chip LDO to bias the device.

• ^{Load = 10A maximum}

Frequency Selection

Selection of the switching frequency requires making a

trade-oﬀ between the size and cost of the external ﬁlter

components (inductor and output capacitor) and the

power conversion eﬃciency.

• ^{Connect V5V to VLDO before enabling the LDO.}

• ^{The LDO has an initial current limit of 40mA at}

start-up, therefore, do not connect any external

load to VLDO during start-up.

• ^{When VLDO reaches 90% of its ﬁnal value, the}

LDO current limit increases to 200mA. At this

time the LDO may be used to supply the required

bias current to the device.

The desired switching frequency is 250kHz which results

from using component selected for optimum size and

cost .

A resistor (R_TON) is used to program the on-time (indirectly

setting the frequency) using the following equation.

Attempting to operate in self-powered mode in any other

conﬁguration can cause unpredictable results and may

damage the device.

(T_ONꢀ10ns)u V

IN

R_TON

25pFu V_OUT

Design Procedure

When designing a switch mode supply the input voltage

range, load current, switching frequency, and inductor

ripple current must be speciﬁed.

To select R_TON, use the maximum value for V_IN, and for T_ON

use the value associated with maximum V_IN.

V_OUT

T_ON

V_INMAXu f_SW

The maximum input voltage (V_INMAX) is the highest speci-

ﬁed input voltage. The minimum input voltage ( V_INMIN) is

determined by the lowest input voltage after evaluating

the voltage drops due to connectors, fuses, switches, and

PCB traces.

T_ON= 318 ns at 13.2V_IN, 1.05V_OUT, 250kHz

Substituting for R_TONresults in the following solution.

R_TON= 154.9kΩ, use R_TON= 154kΩ

The following parameters deﬁne the design.

Inductor Selection

• ^{Nominal output voltage (V}_OUT

• ^{Static or DC output tolerance}

• ^{Transient response}

)

In order to determine the inductance, the ripple current

must ﬁrst be deﬁned. Low inductor values result in smaller

size but create higher ripple current which can reduce

eﬃciency. Higher inductor values will reduce the ripple

current/voltage and for a given DC resistance are more

eﬃcient. However, larger inductance translates directly

into larger packages and higher cost. Cost, size, output

ripple, and eﬃciency are all used in the selection process.

• ^{Maximum load current (I}_OUT

)

There are two values of load current to evaluate — con-

tinuous load current and peak load current. Continuous

load current relates to thermal stresses which drive the

selection of the inductor and input capacitors. Peak load

current determines instantaneous component stresses and

ﬁltering requirements such as inductor saturation, output

capacitors, and design of the current limit circuit.

The ripple current will also set the boundary for power-

save operation. The switching will typically enter power-

save mode when the load current decreases to 1/2 of the

ripple current. For example, if ripple current is 4A then

Power-save operation will typically start for loads less than

2A. If ripple current is set at 40% of maximum load current,

then power-save will start for loads less than 20% of

maximum current.

The following values are used in this design.

• ^V_IN^{= 12V + 10%}

• ^V_OUT= 1.05V + 4%

20

SC417/SC427

Applications Information (continued)

The inductor value is typically selected to provide a ripple

current that is between 25% to 50% of the maximum load

current. This provides an optimal trade-oﬀ between cost,

eﬃciency, and transient performance.

The design goal is that the output voltage regulation be

4% under static conditions. The internal 500mV refer-

ence tolerance is 1%. Allowing 1% tolerance from the FB

resistor divider, this allows 2% tolerance due to V_OUTripple.

Since this 2% error comes from 1/2 of the ripple voltage,

the allowable ripple is 4%, or 42mV for a 1.05V output.

During the DH on-time, voltage across the inductor is (V_IN

- V_OUT). The equation for determining inductance is shown

next.

The maximum ripple current of 4.4A creates a ripple

voltage across the ESR. The maximum ESR value allowed

is shown by the following equations.

(V ꢀ V_OUT)u T_ON

IN

L

I_RIPPLE

V_RIPPLE

42mV

4.4A

ESR_MAX

Example

I_RIPPLEMAX

In this example, the inductor ripple current is set equal to

50% of the maximum load current. Thus ripple current

will be 50% x 10A or 5A. To ﬁnd the minimum inductance

needed, use the V_INand T_ONvalues that correspond to

ESR_MAX= 9.5 mΩ

The output capacitance is usually chosen to meet tran-

sient requirements. A worst-case load release, from

maximum load to no load at the exact moment when

inductor current is at the peak, determines the required

capacitance. If the load release is instantaneous (load

changes from maximum to zero in < 1ꢀs), the output

capacitor must absorb all the inductor’s stored energy.

This will cause a peak voltage on the capacitor according

to the following equation.

V_INMAX

.

(13.2 ꢀ1.05)u318ns

L

0.77PH

5A

A slightly larger value of 0.88ꢀH is selected. This will

decrease the maximum I_RIPPLEto 4.4A.

Note that the inductor must be rated for the maximum DC

load current plus 1/2 of the ripple current.

2

1

2

§

©

·

¸

L I

ꢁ

uI_RIPPLEMAX

¨

OUT

¹

The ripple current under minimum V_INconditions is also

checked using the following equations.

COUT_MIN

ꢂ

V_PEAKꢃ²

ꢀ

ꢂ

V_OUTꢃ²

Assuming a peak voltage V_PEAKof 1.150 (100mV rise upon

load release), and a 10A load release, the required capaci-

tance is shown by the next equation.

25pFuR_TONu V_OUT

T_{ON_ VINMIN}

ꢁ10ns 384ns

V

INMIN

(V ꢀ V_OUT)u T_ON

IN

I_RIPPLE

2

1

§

©

·

¸

L

0.88PH 10 ꢁ u 4.4

¨

2

¹

COUT_MIN

1.15ꢃ²1.05ꢃ²

ꢂ

ꢀ

(10.8 ꢀ1.05)u384ns

0.88PH

I_{RIPPLE _ VIN}

4.25A

ꢂ

COUT_MIN= 595μF

Capacitor Selection

The output capacitors are chosen based on required ESR

and capacitance. The maximum ESR requirement is con-

trolled by the output ripple requirement and the DC toler-

ance. The output voltage has a DC value that is equal to

the valley of the output ripple plus 1/2 of the peak-to-peak

ripple. Change in the output ripple voltage will lead to a

change in DC voltage at the output.

If the load release is relatively slow, the output capacitance

can be reduced. At heavy loads during normal switching,

when the FB pin is above the 500mV reference, the DL

output is high and the low-side MOSFET is on. During this

time, the voltage across the inductor is approximately

-V_OUT. This causes a down-slope or falling di/dt in the

21

SC417/SC427

Applications Information (continued)

inductor. If the load di/dt is not much faster than the -di/

dt in the inductor, then the inductor current will tend to

track the falling load current. This will reduce the excess

inductive energy that must be absorbed by the output

capacitor, therefore a smaller capacitance can be used.

Stability Considerations

Unstable operation is possible with adaptive on-time con-

trollers, and usually takes the form of double-pulsing or

ESR loop instability.

Double-pulsing occurs due to switching noise seen at the

FB input or because the FB ripple voltage is too low. This

causes the FB comparator to trigger prematurely after the

250ns minimum oﬀ-time has expired. In extreme cases

the noise can cause three or more successive on-times.

Double-pulsing will result in higher ripple voltage at the

output, but in most applications it will not aﬀect opera-

tion. This form of instability can usually be avoided by

providing the FB pin with a smooth, clean ripple signal

that is at least 10mVp-p, which may dictate the need to

increase the ESR of the output capacitors. It is also impera-

tive to provide a proper PCB layout as discussed in the

Layout Guidelines section.

The following can be used to calculate the needed capaci-

tance for a given dI_LOAD/dt:

Peak inductor current is shown by the next equation.

I_LPK= I_MAX+ 1/2 x I_RIPPLEMAX

I_LPK= 10 + 1/2 x 4.4 = 12.2A

dl_LOAD

Rate of change of Load Current

dt

I_MAX= maximum load release = 10A

Another way to eliminate doubling-pulsing is to add a

small (~ 10pF) capacitor across the upper feedback resis-

tor, as shown in Figure 13. This capacitor should be left

unpopulated until it can be conﬁrmed that double-pulsing

exists. Adding the C_TOPcapacitor will couple more ripple

into FB to help eliminate the problem. An optional con-

nection on the PCB should be available for this capacitor.

I_LPK

I_MAX

Lu

ꢀ

u dt

V_OUTdl_LOAD

V_PKꢀ V_OUT

C_OUT I_LPK

u

2

ꢂ

ꢃ

Example

dl_LOAD2.5A

Load

C_TOP

dt

Ps

This would cause the output current to move from 10A to

zero in 4ꢀs as shown by the following equation.

To FB pin

V_OUT

R1

12.2 10

R2

0.88PHu

ꢀ

u1Ps

1.05 2.5

1.15 ꢀ1.05

C_OUT 12.2u

C_OUT= 379 μF

2

ꢂ

ꢃ

Figure 13 — Capacitor Coupling to FB Pin

Note that C_OUTis much smaller in this example, 379ꢀF

compared to 595ꢀF based on a worst-case load release. To

meet the two design criteria of minimum 379ꢀF and

maximum 9mΩ ESR, select two capacitors rated at 220ꢀF

and 15mΩ ESR.

ESR loop instability is caused by insufficient ESR. The

details of this stability issue are discussed in the ESR

Requirements section. The best method for checking sta-

bility is to apply a zero-to-full load transient and observe

the output voltage ripple envelope for overshoot and

ringing. Ringing for more than one cycle after the initial

step is an indication that the ESR should be increased.

It is recommended that an additional small capacitor be

placed in parallel with C_OUTin order to ﬁlter high frequency

switching noise.

22

SC417/SC427

Applications Information (continued)

One simple way to solve this problem is to add trace resis-

tance in the high current output path. A side eﬀect of

adding trace resistance is output decreased load

regulation.

L

High-

side

C_L

R_L

C_C

ESR Requirements

R1

A minimum ESR is required for two reasons. One reason is

to generate enough output ripple voltage to provide

10mVp-p at the FB pin (after the resistor divider) to avoid

double-pulsing.

C_OUT

Low-

side

R2

FB

The second reason is to prevent instability due to insuﬃ-

cient ESR. The on-time control regulates the valley of the

output ripple voltage. This ripple voltage is the sum of the

two voltages. One is the ripple generated by the ESR, the

other is the ripple due to capacitive charging and dis-

charging during the switching cycle. For most applica-

tions the minimum ESR ripple voltage is dominated by the

output capacitors, typically SP or POSCAP devices. For

stability the ESR zero of the output capacitor should be

lower than approximately one-third the switching fre-

quency. The formula for minimum ESR is shown by the

following equation.

Figure 14 — Virtual ESR Ramp Current

Dropout Performance

The output voltage adjust range for continuous-conduc-

tion operation is limited by the fixed 250ns (typical)

minimum oﬀ-time of the one-shot. When working with

low input voltages, the duty-factor limit must be calcu-

lated using worst-case values for on and oﬀ times.

The duty-factor limitation is shown by the next equation.

3

T_ON(MIN)

DUTY

ESR_MIN

2u SuC_OUTu f_sw

T_ON(MIN)ꢁ T_OFF(MAX)

For applications using ceramic output capacitors, the ESR

is normally too small to meet the above ESR criteria. In

these applications it is necessary to add a small virtual ESR

network composed of two capacitors and one resistor, as

shown in Figure 14. This network creates a ramp voltage

across C_L, analogous to the ramp voltage generated across

the ESR of a standard capacitor. This ramp is then capaci-

tively coupled into the FB pin via capacitor C_C.

The inductor resistance and MOSFET on-state voltage

drops must be included when performing worst-case

dropout duty-factor calculations.

System DC Accuracy (V_OUTController)

Three factors aﬀect V_OUTaccuracy: the trip point of the FB

error comparator, the ripple voltage variation with line

and load, and the external resistor tolerance. The error

comparator oﬀset is trimmed so that under static condi-

tions it trips when the feedback pin is 500mV, 1%.

The on-time pulse from the SC417/SC427 in the design

example is calculated to give a pseudo-ﬁxed frequency of

23

SC417/SC427

Applications Information (continued)

250kHz. Some frequency variation with line and load is

expected. This variation changes the output ripple

voltage. Because constant on-time converters regulate to

the valley of the output ripple, ½ of the output ripple

appears as a DC regulation error. For example, if the

output ripple is 50mV with V_IN= 6 volts, then the measured

DC output will be 25mV above the comparator trip point.

If the ripple increases to 80mV with V_IN= 25V, then the

measured DC output will be 40mV above the comparator

trip. The best way to minimize this eﬀect is to minimize

the output ripple.

Switching Frequency Variations

The switching frequency will vary depending on line and

load conditions. The line variations are a result of ﬁxed

propagation delays in the on-time one-shot, as well as

unavoidable delays in the external MOSFET switching. As

V_INincreases, these factors make the actual DH on-time

slightly longer than the ideal on-time. The net eﬀect is

that frequency tends to falls slightly with increasing input

voltage.

The switching frequency also varies with load current as a

result of the power losses in the MOSFETs and the induc-

tor. For a conventional PWM constant-frequency con-

verter, as load increases the duty cycle also increases

slightly to compensate for IR and switching losses in the

MOSFETs and inductor. A constant on-time converter

must also compensate for the same losses by increasing

the effective duty cycle (more time is spent drawing

energy from V_INas losses increase). The on-time is essen-

tially constant for a given V_OUT/V_INcombination, to oﬀset

the losses the oﬀ-time will tend to reduce slightly as load

increases. The net effect is that switching frequency

increases slightly with increasing load.

To compensate for valley regulation, it may be desirable to

use passive droop. Take the feedback directly from the

output side of the inductor and place a small amount of

trace resistance between the inductor and output capaci-

tor. This trace resistance should be optimized so that at

full load the output droops to near the lower regulation

limit. Passive droop minimizes the required output capaci-

tance because the voltage excursions due to load steps

are reduced as seen at the load.

The use of 1% feedback resistors contributes up to 1%

error. If tighter DC accuracy is required, 0.1% resistors

should be used.

The output inductor value may change with current. This

will change the output ripple and therefore will have a

minor eﬀect on the DC output voltage. The output ESR

also aﬀects the output ripple and thus has a minor eﬀect

on the DC output voltage.

24

SC417/SC427

Applications Information (continued)

AGND should connect to PGND (power ground) using an

external zero ohm resistor or using a short PCB trace.

Connect AGND to PGND only at one place, as near to the

AGND and PGND pins as is practical.

PCB Layout Guidelines

The optimum layout for the SC417/SC427 is shown in

Figure 15. The layout highlights the device as a space

saving and high performance solution. This layout shows

an integrated FET buck regulator with a maximum current

of 10A. The total PCB area is approximately 20 x 25 mm.

Power ground (PGND) should be a separate plane which is

not used for routing analog traces.

This ﬁgure shows the total area and optimum layout for

the device. If optimum layout is not possible due to PCB

limitations, the following generic guidelines should be

followed.

All PGND connections should connect directly to the

PGND plane. Indirect connections between AGND and

GND which will create ground loops should be avoided.

The V5V input provides power to the internal analog cir-

cuits and the upper and lower gate drivers. The V5V supply

decoupling capacitors should be tied between V5V and

PGND with short traces.

Generic Layout Guidelines

One or more ground planes are recommended to mini-

mize the eﬀect of switching noise, resistive losses, and to

maximize heat removal. The analog ground reference

AGND should connect directly to the AGND pad and pins.

An AGND plane or island should be used near the device.

All components that are referenced to AGND should

connect directly to this plane and mounted on the IC side

of the PCB.

The switcher power section should be connected directly

to the PGND plane(s) using multiple vias as required for

RGND — AGND connects to

PGND close to SC417/SC427

AGND plane on

inner layer

RILIM

Pin 1 marking

RLDO2

RLDO1

CLDO

RFB2

SC417/SC427

with vias for LX,

AGND, VIN

All components

shown Top Side

RFB1

CFF

C_IN

V_INplane on inner

or bottom layer

PGND

VOUT Plane

on Top layer

PGND on inner

or bottom layer

C_OUT

L

LX plane on inner

or bottom layer

PGND on

Top layer

Figure 15 — PCB Layout

25

SC417/SC427

Applications Information (continued)

current handling (including the chip power ground con-

nections). Power components should be placed to mini-

mize current loops and reduce losses. Make all the power

connections on one side of the PCB using wide copper

areas if possible. Do not use minimum land patterns for

power components.

Control Section

Locate all components referenced to AGND on the sche-

matic and place these components near the device and

on the same side if possible. Connect AGND to the AGND

pad and pins using a plane or island if possible.

The device supply decoupling capacitor (V5V to PGND)

should be located as close as possible to the pins. The V5V

decoupling capacitor preferred placement is on the oppo-

site side of the PCB. It should be routed with traces as

short as possible, using at least two vias when connecting

through the PCB.

Current Limit

Obtaining an accurate current limit for the SC417/SC427

requires careful PCB layout. The device uses the RDS_(ON)of

the low-side MOSFET for current sensing. The ILIM com-

parator that performs the current limit function monitors

the ILIM pin with respect to AGND, but the low-side

MOSFET is internally connected to PGND. The PCB layout

needs to following these guidelines.

There are two sensitive feedback-related pins at the device

— VOUT and FB. Proper routing is essential to keep noise

away from these signals. All components connected to FB

should be located directly at the chip, and the copper area

of the FB node must be minimized. The VOUT trace that

feeds into the VOUT pin, which also feeds the FB resistor

divider, must be kept as far away as possible from noise

sources such as all switching signals (LX, DH, DL, BST) and

the inductor. Route the VOUT trace in a quiet layer if pos-

sible, from the output capacitor back to the chip.

• AGND and PGND must be connected together

directly at the pins of the IC and not anywhere

else. This can be done through PCB copper or a

zero ohm resistor. Keep the traces short and

direct. The preferred connection for PGND is at

pin 19. The preferred connection for AGND is at

the PAD1.

• ^{The PGND path from the device to the input and}

output capacitors requires a wide copper areas.

Use multiple vias and copper areas if available.

Do not break up these copper areas with inter-

vening components. The goal is to minimize

the IR drop between all PGND connections.

• ^{Provide multiple vias and multiple copper areas}

between the LX pins and the inductor. The goal

is to minimize any IR drop that might contrib-

uted to the RDS_(ON). This is also good to carry

heat away from the device.

• ^{For the connection from the RLIM resistor to the}

LX node, use a direct Kelvin connection to pin 28

(LX), as near to the pin as possible. Do not

connect to a place further in the copper between

the LX pins and the inductor — the intervening

copper will appear as increased RDS_(ON)and will

reduce the operating current limit.

Power Section

The switcher power section key guidelines are as follows.

• There should be a very small input loop between

the input capacitors, inductor, and output

capacitors. Locate the input decoupling capaci-

tors directly at the VIN pad on the device.

• ^{The LX phase node should be a large enough to}

carry the required current. Careful sizing is

required since this is the noisiest node.

• ^{The PGND connection between the input capaci-}

tors, low-side MOSFET, and output capacitors

should be as small as possible, with wide traces

or planes and multiple vias.

• ^{The impedance of the PGND connection}

between the low-side MOSFET and the PGND

pin should be minimized. This connection must

carry the DL drive current, which has high peaks

at both rising and falling edges. Use multiple

layers and multiple vias to minimize impedance

and keep the distance as short as practical.

The layout can be considered in two parts; the control

section referenced to AGND, and the switcher power

section referenced to GND.

26

SC417/SC427

Applications Information (continued)

LDO Section

Connect the control and switcher power sections as

follows.

There are three components for the LDO that need to be

optimized for this layout, the two feedback resistors and

the output capacitor. Use the following guidelines to

locate these components.

• Route the V_OUTfeedback trace in a quiet layer,

away from noise sources.

• ^{BST is a noisy node and should be kept as short}

as possible. The high-side DH driver uses the

boost capacitor to provide the DH drive current.

The boost capacitor must be placed near the

device and connected to the BST and LX pins

using short, wide traces to minimize

impedance.

• ^{Connect the PGND pin on the chip to the V5V}

decoupling capacitor and then insert vias

directly to the ground plane.

• The feedback resistors should be placed as close

to the FBL pin as possible. This minimizes the

trace length for the FBL pin.

• ^{For the feedback divider connection, the top}

resistor must connect directly to the LDO output

capacitor. There should be no PCB inductance

between the top of the resistor divider and the

LDO output capacitor.

• ^{If VLDO is not used to power the device, then a}

minimum 1.0μF capacitor referenced to AGND is

required.

• ^{If VLDO is used to power-up the device by con-}

necting it to V5V, then the LDO output capacitor

also becomes the decoupling capacitor for the

V5V input. A minimum 0.1μF capacitor refer-

enced to AGND is required along with a

minimum 1.0μF capacitor referenced to PGND

to filter the gate drive pulses. Each capacitor

should be placed near the V5V pin and con-

nected with short, direct traces. Each capacitor

should connect directly to its respective

ground.

27

SC417/SC427

Outline Drawing — MLPQ-5x5-32

DIMENSIONS

INCHES MILLIMETERS

B

E

A

D

DIM

A

A1 .000

A2

b

D

D1

E

MIN NOM MAX MIN NOM MAX

-

.031

.039

.002 0.00

1.00

0.05

-

0.80

-

(.008)

(0.20)

0.25 0.30

4.90 5.00 5.10

1.92 1.97

.193 .197 .201 4.90 5.00 5.10

.007

.010 .012 0.18

PIN 1

INDICATOR

(LASER MARK)

.193 .197 .201

.076 .078

.080

2.02

3.43

E1

e

3.48

.135

3.53

.137 .139

.020 BSC

0.50 BSC

L

N

.012 .016 .020 0.30 0.40 0.50

A2

32

aaa

bbb

.003

.004

0.08

0.10

A

SEATING

PLANE

aaa

C

A1

3.48

D1

0.76

1.05

LxN

1.49

E1

3.61

1.66

2

1

0.76

bxN

N

R0.20

PIN 1

IDENTIFICATION

e

bbb

C

A

B

NOTES:

1.

2.

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).

COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

28

SC417/SC427

Land Pattern — MLPQ-5x5-32

3.48

K1

K

DIMENSIONS

1.74

DIM

INCHES

MILLIMETERS

(.195)

.165

.137

.059

.065

.078

.041

.020

.012

.030

.224

(4.95)

4.20

3.48

1.49

1.66

1.97

1.05

0.50

0.30

0.75

5.70

C

G

H

H2

1.74

H1

H2

K

(C)

G

H

3.61

Z

H1

K1

P

Y

X

Y

X

Z

P

NOTES:

1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).

2.

THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.

CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR

COMPANY'S MANUFACTURING GUIDELINES ARE MET.

3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD

SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.

FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR

FUNCTIONAL PERFORMANCE OF THE DEVICE.

4. SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS.

Contact Information

Semtech Corporation

Power Mangement Products Division

200 Flynn Road, Camarillo, CA 93012

Phone: (805) 498-2111 Fax: (805) 498-3804

www.semtech.com

29

型号:	SC417MLTRT
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	QFN
包装说明：	HVQCCN, LCC32,.2SQ,20
针数：	32
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	1.7
其他特性：	OUTPUT VOLTAGE IS ADJUSTABLE FROM 0.5V TO 5.5V
模拟集成电路 - 其他类型：	DUAL SWITCHING CONTROLLER
控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	28 V
最小输入电压：	3 V
标称输入电压：	12 V
JESD-30 代码：	S-XXMA-N32
长度：	5 mm
功能数量：	1
端子数量：	32
最高工作温度：	125 °C
最低工作温度：	-40 °C
最大输出电流：	10 A
标称输出电压：	5 V
封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN
封装等效代码：	LCC32,.2SQ,20
封装形状：	SQUARE
封装形式：	MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	BUCK
最大切换频率：	1000 kHz
温度等级：	AUTOMOTIVE
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	UNSPECIFIED
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	5 mm
Base Number Matches：	1

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