SC900供应商报价哪里找芯片批发报价原理和应用中文资料-中国IC网-芯三七

SC900

Programmable Penta ULDO with

RESET and I²C Interface

POWER MANAGEMENT

Features

Description

The SC900 is a highly integrated power management

device for low power portable applications. The device

contains five adjustable low-dropout linear regulators

(LDOs) with CMOS pass-devices as well as a band-gap

reference, I²C interface, and DACs to control the output

voltages.

! Five LDO regulators in one package

! I²C interface with multiple device capability

! Independent I²C enable/disable of LDOs

! Independent I²C control of output voltages

! Low thermal impedance of 40°C per watt

! 150mV dropout at 150mA

! Input range from 2.7V to 5.5V

! Programmable power-good flag

Many features of the SC900 are programmable through

the I²C interface. These include the ability to indepen-

dently turn on any combination of the five regulators. All

five of the LDO output voltages are programmable in

50mV steps from 1.45V to 3.00V. Each LDO can have

an active shutdown or nonactive shutdown program op-

tion through the interface. There is also a reset monitor

flag that is associated with LDOA. In addition, the device

has a separate programmable power-good monitor flag

that activates when one or more LDOs go out of regula-

tion.

! Minimal number of external components

! Over temperature protection

! Small 4mm x 4mm 20-lead MLPQ package

! Small input/output filter capacitors

! Programmable V_OUTrange - 1.45V to 3.00V for

each LDO

The SC900 offers significant quiescent current and space

savings to the system designer by sharing reference and

biasing among five LDOs. The small and thermally effi-

cient 20-lead MLPQ package make it ideal for use in por-

table products where minimizing layout area is critical.

Applications

! Palmtop/Laptop computers

! Personal Digital Assistants

! Cellular telephones

! Battery-powered equipment

! High efficiency linear power supplies

Typical Application Circuit

SC900

LDOE

LDOD

2.2µF

VIN

LDOA

LDOB

LDOC

INA

4.7µF

VBAT

INB

2.2µF 2.2µF

2.2µF

INCD

INE

LNA

Baseband

Processor

Receiver

Section

EN

VREF

LDOPGD

ARST

SDA

SCL

A0

TXCO

&

0.1µF

Synthesizer

Audio

Processing

VASEL

DGND

Transmitter

Section

GND

PA

Keypad

2.2µF

Digital Interface

1

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SC900

POWER MANAGEMENT

Absolute Maximum Ratings

Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters

specified in the Electrical Characteristics section is not implied.

Parameter

Symbol

V_IN

Maximum

-0.3 to +7

-0.3 to V_IN+0.3

-40 to +85

-40 to +125

260

Units

V

Input Supply Voltage

Digital Input Voltage

V_DIG

T_A

V

Operating Ambient Temperature Range

Operating Junction Temperature Range

Peak IR Reflow Temperature

Storage Temperature

°C

T_J

°C

T_LEAD

T_STG

θ_JA

°C

-60 to +150

* 40

°C

Thermal Resistance Junction to Ambient

°C/W

*1 Square inch, 2 ounce copper.

Electrical Characteristics

Unless otherwise noted: V_IN= 3.7V, EN = V_IN, T_A= -40 to 85°C. Typical values are at T_A= +25°C.

Parameter

Symbol

Condition

Min

Typ

Max

Units

General

Supply Voltage

V_IN

I_Q-SHUTDOWN

C_VCC

All outputs < V_IN- dropout

Per input pin

2.7

5.5

10

V

Quiescent Current Shutdown

Supply Bypass Capacitor

Digital Inputs

µA

µF

1

Digital Input Voltage

V_IL

V_IH

I_DIG

0.4

0.2

10

V

1.6

Digital Input Current

Digital Outputs

-0.2

µA

Digital Output Voltage⁽¹⁾

V_OL

V_OH

I_SINK= 1.2mA, V_LDOB≥ 1.8V

2

%

LDOB

I_SOURCE= 0.5mA, V_LDOB≥ 1.8V

90

98

%

LDOB

Reference and Biasing Circuitry

Quiescent Current Reference

Reference Voltage

I_Q-REF

V_REF

t_VREF

25

1.227

15

µA

V

V_REFStart-up Time

C_VREF= 100nF

ms

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SC900

POWER MANAGEMENT

Electrical Characteristics (Cont.)

Unless otherwise noted: V_IN= 3.7V, EN = V_IN, T_A= -40 to 85°C. Typical values are at T_A= +25°C.

Parameters

Symbol

Conditions

Min

Typ Max Units

Reference and Biasing Circuitry (cont.)

VREF Bypass Capacitor

LDO Regulators

CVREF

0.1

µF

Quiescent Supply Current

I_Q

All LDOs active in default states

190

125

360

µA

Quiescent Supply Current

at Start-up

I_QSUP

LDO A, B, C active in default states

V

_OUT+ 0.5V < V_IN< 5.5V

Dropout Voltage

LDO B,C,D,E

V

= 3.0V, I_OUT= 1mA

1.1

50

V ^OUT= 3.0V, I = 50mA

64

V_D

V_O^O_U^U_T^T= 3.0V, I ^OUT= 150mA

150

190

mV

OUT

V

_OUT= 3.0V, I_OUT= 200mA

200

410

250

650

LDO A

Current Limit

I_LIM

250

mA

dB

f = 10Hz -1kHz, C_BYP= 0.1µF,

Power Supply Rejection Ratio

Output Voltage Noise⁽²⁾

PSRR

I_OUT= 50mA

60

45

2.5V < V_OUT< 3.0V

f =10Hz to 100kHz, I_OUT= 50mA

e_n

C

_VREF= 0.1µF, C_OUT= 2.2µF

µVrms

µF

2.5V ≤ V_OUT≤ 3.0V

Bypass Capacitor

C_BYP

Ceramic, low ESR

2.2

-3

LDO Regulator A (CORE SUPPLY)

Output Voltage Accuracy

VOA_A

1.45V ≤ V

≤ 3.00V

V

_OUT+0.2V ^O≤^UTV_IN≤ 5.5V

+3

%

I_OUT= 1mA, T_A= 25^OC

I_OUT= 1mA

Output Voltage Accuracy at

2.80V (DAC=11011)

-2

-3

+2

+3

%

Output Voltage Accuracy at

1.80V (DAC=00111)

I

_OUT= 1mA, T_A= 25^OC

VOAS_A

Output Voltage Accuracy at

2.80V (DAC=11011)

I_OUT= 200mA, V_OUT+0.5V ≤ V_IN≤ 5.5V

-3.5

200

+3.5

Maximum Output Current

Default Setting: ON

IOMAX_A

VO_A-HI

mA

V

VASEL – High

VASEL – Low

2.80

1.80

2.5

VO_A-LO

V

Line Regulation at 1.8V, 2.8V

Load Regulation at 1.8V, 2.8V

LINEREG_A

LOADREG_A

I_OUT= 1mA, V_OUT+0.2V < V_IN< 5.5V

1mA < I_OUT< 200mA

12

mV

-3

-20

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SC900

POWER MANAGEMENT

Electrical Characteristics (Cont.)

Unless otherwise noted: V_IN= 3.7V, EN = V_IN, T_A= -40 to 85°C. Typical values are at T_A= +25°C.

Parameter

Symbol

Condition

Min

Typ Max Units

LDO Regulator B (DIGITAL I/O SUPPLY)

1.45V ≤ V

≤ 3.00V

Output Voltage Accuracy

VOA_B

V_OUT+0.15V^O≤^UTV_IN≤ 5.5V

-3

-2

+3

%

I_OUT= 1mA, T_A= 25^OC

I_OUT= 1mA

+2

%

Output Voltage Accuracy at

2.80V (DAC=11011)

VOAS_B

I

_OUT= 150mA, V_OUT+0.5V ≤ V_IN≤ 5.5V -3.5

+3.5

Maximum Output Current

Default Setting: ON

IOMAX_B

VO_B

150

mA

V

2.80

2.5

-3

Line Regulation 2.80V

Load Regulation at 2.80V

LDO Regulator C

LINEREG_B

LOADREG_B

I_OUT= 1mA, V_OUT+0.15V ≤ V_IN≤ 5.5V

12

mV

1mA < I_OUT<150mA

-20

1.45V ≤ V

≤ 3.00V

Output Voltage Accuracy

VOA_C

V_OUT+0.15V^O≤^UTV_IN≤ 5.5V

-3

-2

+3

%

I_OUT= 1mA, T_A= 25^OC

I_OUT= 1mA

+2

%

Output Voltage Accuracy at

2.60V (DAC=10111)

VOAS_C

I_OUT= 150mA, V_OUT+0.5V ≤ V_IN≤ 5.5V -3.5

+3.5

Maximum Output Current

Default Setting: ON

IOMAX_C

VO_C

mA

V

150

2.60

2.5

Line Regulation at 2.60V

Load Regulation at 2.60V

LINEREG_C

I_OUT= 1mA, V_OUT+0.15V < V_IN< 5.5V

1mA < I_OUT<150mA

mV

12

-3

-20

LOADREG_C

LDO Regulator D

1.45V ≤ V

≤ 3.00V

Output Voltage Accuracy

VOA_D

V_OUT+0.15V^O≤^UTV_IN≤ 5.5V

-3

-2

+3

%

I_OUT= 1mA, T_A= 25^OC

VOAS_D

I_OUT= 1mA

+2

%

Output Voltage Accuracy

at 2.80V (DAC=11011)

I_OUT= 150mA, V_OUT+0.5V ≤ V_IN≤ 5.5V -3.5

+3.5

Maximum Output Current

Default Setting: OFF

IOMAX_D

VO_D

mA

V

150

2.80

2.5

Line Regulation at 2.80V

Load Regulation at 2.80V

LINEREG_D

I_OUT= 1mA, V_OUT+0.15V < V_IN< 5.5V

1mA < I_OUT<150mA

12

mV

-3

-20

LOADREG_D

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SC900

POWER MANAGEMENT

Electrical Characteristics (Cont.)

Unless otherwise noted: VIN = 3.7V, EN = VIN, T_A= -40 to 85°C. Typical values are at T_A= +25°C.

Parameter

Symbol

Condition

Min

Typ Max Units

LDO Regulator E

VOA_E

1.45V < V

< 3.00V

Output Voltage Accuracy

V_OUT+0.15V^OU<^TV_IN< 5.5V

-3

-2

+3

%

I

_OUT= 1mA, T_A= 25^OC

Output Voltage Accuracy at 2.80V

(DAC=11011)

VOAS_E

I_OUT= 1mA

+2

%

I

_OUT= 150mA, V_OUT+ 0.5V < V_IN< 5.5V -3.5

+3.5

Maximum Output Current

Default Setting: OFF

Line Regulation at 2.80V

Load Regulation at 2.80V

I²C Interface

IOMAX_E

VO_E

150

mA

V

2.80

2.5

-3

LINEREG_E

LOADREG_E

I_OUT= 1mA, V_OUT+0.15V < V_IN< 5.5V

1mA < I_OUT< 150mA

12

mV

-20

Interface complies with slave mode I²C interface as described by Philips I²C specification version 2.1 dated January

2000.

V_IL

0.4

V

Digital Input Voltage

1.6

V_IH

I_DIN(SDA) = 3mA

I_DIN(SDA) = 6mA

0.4

0.6

0.2

V

SDA Output Low Level

Digital Input Current

I/O Pin Capacitance

I²C Timing

I_DG

-0.2

µA

pF

C_IN

10

Clock Frequency

SCL Low Period

SCL High Period

Data Hold Time

Data Setup Time

SCL

t_LOW

400

kHz

µs

1.3

0.6

0

t_HIGH

µs

t_{HD_DAT}

µs

100

ns

t_{SU_DAT}

t_{SU_STA}

t_{HD_STA}

Setup Time for Repeated

Start Condition

0.6

µs

Hold Time for Repeated

Start Condition

SetupTime for Stop Condition

t_{SU_STO}

t_BUF

0.6

1.3

µs

Bus-Free Time Between

STOP and START

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SC900

POWER MANAGEMENT

Electrical Characteristics (Cont.)

Unless otherwise noted: V_IN= 3.7V, EN = V_IN, T_A= -40 to 85°C. Typical values are at T_A= +25°C.

Parameter

Symbol

Condition

Min

Typ Max Units

A RESET

Reset Threshold

77

%

RESET_THLD

t_RD

Reset Active Timeout Delay

LDO POWER GOOD

PGOOD Threshold

PGOOD Active Timeout Delay

Delay in default state

75

100

125

ms

77

%

PGOOD_THLD

t_PG

100

ms

Notes:

(1) Digital outputs are powered from LDOB, so LDOB must be active for operation of LDOPGD and ARST.

(2) Below 2.5V: becomes digital regulator.

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SC900

POWER MANAGEMENT

Pin Configuration

Ordering Information

DEVICE

SC900IMLTRT⁽²⁾

SC900EVB

PACKAGE⁽¹⁾

MLPQ20L

Evaluation Board

20

19

18

17

16

Notes:

(1) Available in tape and reel only. A reel contains 3,000 devices.

(2) Available in Lead-free package only. This product is fully WEEE and

RoHS compliant.

LDOB

INB

LDOE

INE

1

2

3

4

5

15

14

13

12

11

TOP VIEW

SDA

SCL

EN

VIN

GND

VREF

T

10

9

6

7

8

MLPQ20: 4X4 20 LEAD

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SC900

POWER MANAGEMENT

Pin Description

Pin#

Pin Function

Name

LDOB

INB

1

2

3

4

5

LDO B output.

Input supply for the digital system logic and the LDO B pass transistor.

Bidirectional open drain digital I/O pin. I²C serial data.

Digital input. I²C serial clock.

Digital input. High to enable part. Low to disable part (sleep mode). Note I²C control is active only

when part is enabled.

SDA

SCL

EN

6

7

8

9

A0

One bit address for connecting two SC900 devices onto the system through the I²C interface.

DGND

Digital ground.

VASEL LDO A selection default voltage. Tie this pin to ground for 1.8V or INB for 2.8V.

Digital output. State change indicates that one of four LDO output voltages (A,C,D or E) is out of

LDOPGD

spec. Note, desired state of pin is programmable through the I²C interface.

10

Digital output. State change indicates LDOA output voltage is out of spec. Note; desired state of

ARST

pin is programmable through the I²C interface.

11

12

13

14

15

16

17

18

19

20

T

VREF

GND

VIN

Bandgap reference output voltage. Connect at least 0.1µF to ground (CV_REF≥ 0.1µF).

Analog ground.

Analog supply voltage.

INE

Input supply for the LDO E pass transistor.

LDO E output.

LDOE

LDOD

INCD

LDOC

INA

LDO D output.

Input supply for the LDO C and LDO D pass transistors.

LDO C output.

Input supply for the LDO A pass transistor.

LDO A output.

LDOA

Thermal Pad for heat sinking purposes. Connect to ground plane using multiple vias. Not connected

internally.

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SC900

POWER MANAGEMENT

Block Diagram

INA

INB

VIN

INB

Reference

VREF

EN

DACs

LDO

ref

en

input

dac

out

I2C

DAC A

LDOA

en

Interface

DAC B

DAC C

DAC D

DAC E

en

vasel

VASEL

DAC

CTRL

Input

LDO

CTRL

VOB

scl

sda

a0

ref

en

out

SCL

SDA

A0

LDO

CTRL

reset

input

dac

LDOB

LDOC

CTRL

INB

Reset/

Shutdown

CTRL

LDO

ref

en

out

VOB

input

dac

arst

ARST

reset

ldopgd

LDOPGD

LDO

ref

en

input

dac

out

LDOD

LDOE

LDO

INCD

INE

ref

en

out

input

dac

DGND

GND

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SC900

POWER MANAGEMENT

Applications Information

General Description

LDO RESET Control Register:

ARST Pin

There are two functions that can be programmed, defin-

ing the ARST pin action:

Each of the five low-dropout linear regulators (LDOs) can

be independently enabled or disabled and their output

voltages can each be set by an independent DAC. These

controls can be accessed through the I²C serial port.

There are five 8-bit volatile registers in the SC900; one

for each LDO (registers A,B,C,D,E). In addition there is

one common reset and power good control register and

one on/off control register. The active shutdown circuitry

can be accessed through each LDO register (refer to the

section “Active Shutdown” on page 11 for more informa-

tion).

• Set the polarity of the reset signal

• Set the reset clear delay time in milliseconds

As soon as the LDOA output voltage falls below its pro-

grammed value, the ARST pin is asserted. The polarity

of the ARST pin can be set to active high or active low

during a reset condition, by bit 6 of the LDO Reset Con-

trol Register. Once the error condition is resolved (out-

put rises to the programmed value), a delay is initiated

before the ARST pin is cleared. The delay is program-

mable by bits 0-1 of the LDO Reset Control Register. The

Default delay time is 100ms, and the delay can be pro-

grammed for 0, 50, 100, or 150ms.

At power-up, the register contents are reset to their de-

fault values and the ARST for LDO A has a default start-

up delay of 100ms. At any time the part can be put into

it’s lowest power state (shutdown) by pulling the EN pin

low. Whenever the EN pin is forced low, the previous

settings are lost and the part requires reprogramming to

return to the desired state. When EN is pulled high, the

device starts up in the default state. A detailed descrip-

tion of the protocol used to load the registers with data

is described in the section entitled “Using the I²C Inter-

face” on page 13.

LDOPGD Pin

There are three functions that can be programmed to

define the LDOPGD pin action:

• Set which LDOs are to be monitored for power-good

• Set the polarity of the power-good signal

• Set the power-good delay time in milliseconds

VIN and Enable Pin

The VIN supply must be ≥ 2.7V before the EN pin can be

asserted. This means that the EN pin should not be tied

to VIN so that it does not reach a logic high level before

the input supply reaches 2.7V.

Bits 4 and 5 of the LDO Reset Control Register select

which LDO or LDOs are monitored. LDO C, D and E can

be monitored independently or LDOs A, C, D, & E can be

monitored collectively. The polarity of the LDOPGD pin

can be set to active high or active low by bit 7 of the LDO

Reset Control Register. As soon as any of the selected

LDO output voltages which are monitored falls within spec,

the LDO power-good (LDOPGD) pin is asserted. Once the

LDO output power is stable (output rises to the pro-

grammed value), a delay is initiated before the LDOPGD

pin is set. The delay is programmable by bits 2 and 3 of

the LDO Reset Control Register. The default delay is

100ms, and this delay can be programmed to 0, 50,

100, or 150ms.

LDOA (Core Supply)

LDOA is intended to be used as the MSM core supply. It

has an output current capability of 200mA and a dedi-

cated reset signal ARST. INA is the dedicated input sup-

ply for this regulator.

LDOB (Digital I/O Supply)

INB supplies power for the internal I²C interface and other

digital I/O functions, while LDOB supplies power for ARST

and LDOPGD output ports (see block diagram). There-

fore it is imperative that LDOB be operational to make

use of ARST and LDOPGD. If LDOB is turned off by the

on/off control register, these output ports will not func-

tion.

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SC900

POWER MANAGEMENT

Applications Information (Cont.)

Active Shutdown

When the A0 pin is tied to GND, device 1 has an address

The shutdown control bits determine how the on-chip of 0 and the combination of device type ID and address

active shutdown switches behave. Each LDO register is 0x08H. When the A0 pin is tied to VIN, device 2 has

uses bit 5 of the LDO output voltage data byte to control and address of 1 and the combination of device type ID

the shutdown behavior. When the active shutdown bit is and address is 0x09H.

enabled (set to 1), the capacitance on the LDO output

will be discharged by an on-chip FET after the LDO is dis- The last bit of the slave address defines the operation to

abled. When the active shutdown bit is disabled (set to be performed. When set to a one a read operation is

0), the output capacitance on the LDO output is dis- selected; when set to a zero a write operation is selected.

charged by the load. The default active shutdown state Following a start condition, the SC900 monitors the SDA

for all LDOs is on.

line comparing the slave address being transmitted with

its slave address (device type ID and state of A0 input).

Upon a correct compare the SC900 outputs an acknowl-

ON/OFF Control Register

Each individual LDO may be turned on or off by access- edge on the SDA line. Depending on the state of the R/

ing the ON/OFF control register. LDOs are turned on by W bit, the SC900 will execute a read or write operation.

setting their respective on/off bit to 1. Likewise, they

can be turned off by setting the on/off bit to 0. This Protection Circuitry

allows for on/off control with a single write command. If The SC900 provides protection circuitry that prevents

the enable (EN) pin is high and data is written to the LDO the device from operating in an unspecified state. These

voltage registers, the LDO outputs will go to the voltage include Under-voltage Lockout Protection, Over-tempera-

prescribed by the Output Voltage Code bits (0-4). Data ture Protection and Short-circuit Protection.

will not be lost when toggling the on/off bit from 0 to 1.

However, if the EN pin is forced low, all circuitry in the Under Voltage Lockout

device is disabled. All programmed information is lost The SC900 provides an Under Voltage Lockout (UVLO)

when the enable bit is subsequently pulled high.

circuit to protect the device from operating in an unknown

state if the input voltage supply is too low. When the

battery voltage drops below the UVLO threshold, the LDOs

are disabled. As the battery voltage increases above

the hysteresis level, the LDOs are re-enabled into their

previous states, provided ENABLE has remained high. If

ENABLE goes low, the SC900 will shut down.

VASEL Pin

The VASEL pin sets the default voltage of LDO A, the

core supply. When this pin is set to VIN, the default volt-

age is 2.80V. When this pin is set to GND, the default

voltage is 1.80V. The voltage can be changed from its

default state after start up by writing to the LDO voltage

code register.

Over-temperature Protection

The SC900 provides an internal Over-temperature (OT)

protection circuit that monitors the internal junction tem-

perature. When the temperature exceeds the OT thresh-

old, the OT protection disables all the LDO outputs. As

the junction temperature drops below the hysteresis level

the OT protection re-enables all the LDOs in their previ-

ous states, provided ENABLE has remained high. If EN-

ABLE goes low, the SC900 will shut down.

Device Addressing

Following a start condition, the master must output the

address of the slave it is accessing. The most significant

six bits of the slave are the device type identifier (ID).

For the SC900 this is fixed at 000100[B]. The next sig-

nificant bit addresses a particular device. A system can

have up to two SC900 devices on the bus. The two

addresses are defined by the state of the A0 input (see

Figure 1).

Short-circuit Protection

Each LDO output has short-circuit protection. If a short

is applied to any output, the output voltage will drop and

the output current will be limited to the short circuit cur-

rent until the short is removed.

DEVICE TYPE IDENTIFIER

DEVICE ADDRESS R/W

0

1

0

Pin A0 to GND = 0

Pin A0 to VIN = 1

X

Figure 1 - Slave Address Structure

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SC900

POWER MANAGEMENT

Applications Information (Cont.)

Layout Considerations

voltage track is very thin, then use five 1µF capacitors

Layout is straightforward if you use the Gerber files on placed very close to the input pins of the SC900. If the

page 21 as a reference. Notice that the input voltage input track is fairly thick, then you can use a single 4.7µF

feed to the SC900 is on the bottom of the board and capacitor at the beginning of the voltage feed track since

vias connect this voltage track to the top of the board a wider track has less inductance per inch. The

and then to the SC900 itself. The input bypass can be SC900EVB has five 1µF capacitors, but these can be

one 4.7µF capacitor, two 3.3µF capacitors, three 2.2µF replaced with one 4.7µF in place of C1 and opens in

capacitors or five 1µF capacitors. The determining fac- place of C9, C14, C15, and C16 (see page 20 for de-

tor is how much copper is available on the input voltage tails).

feed track and how much room is available. If the input

LDO Reset Control Logic Table (Defaults are in Bold)

Register

Name

Register

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

LDO A

LDO B

LDO C

LDO D

LDO E

0x00

0x01

0x02

0x03

0x04

0x05

X

Active

Shutdown

1 = ON

LDO Output Voltage Codes

Table A

0 = OFF

LDO Reset

Control

LDOPGD Pin

ARST Pin

LDOPGD Monitor Logic Bits

LDOPGD Delay Bits

LDO (A) Reset Delay Bits

Reset Polarity Bit Reset Polarity Bit

On/Off Control

Register

0x06

X

ON/OFF Control

LDO E

ON/OFF Control

LDO D

ON/OFF Control

LDO C

ON/OFF Control

LDO B

ON/OFF Control

LDO A

1

0

1

0

1

0

1

0

1

0

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

LDO Reset Control Logic Table (Defaults are in Bold)

Bit 7

Result

Bit 6

Result

Bit 5

Bit 4

Result

Bit 3

Bit 2

Result

Bit 1 Bit 0 Result

LDOPGD Pin Polarity

ARST Pin Polarity

LDOPGD Monitor Logic

LDOPGD Delay

ARST Delay

0

High: Power Fail

Low: Power Good

0

1

High: Reset

0

1

LDOs

0

1

150ms

0

1

150ms

50ms

Low: Power Good

A,C,D&E

Good

High: Power Good

Low: Power Fail

High: Power Good

Low: Reset

LDO E Good

100ms

1

0

1

LDO C Good

LDO D Good

1

0

1

50ms

0ms

1

0

100ms

1

0ms

Notes:

Digital outputs are powered from INB, additionally LDOB must be on for operation of LDOPGD and ARST.

SC900 Slave Address:

DEVICE TYPE IDENTIFIER

DEVICE

R/W

X

ADDRESS

0

1

0

A0

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SC900

POWER MANAGEMENT

Applications Information (Cont.)

Output Voltage Code Bits:

A 5-bit linear DAC controls the output voltage of each LDO. The DAC and error-amp gain are scaled so that the LSB

size at the output is 50mV. Output voltage can be set by writing the proper code to the desired LDO register. See

Table A for the bitcodes and their corresponding voltages.

Table A - LDO Output Voltage Control Settings

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

LDO Output Voltage

0

-

0

-

0

1

-

0

1

0

-

0

1

0

1

0

-

1.45V

1.50V

1.55V

1.60V

1.65V

-

1

0

1

2.95V

3.00V

Using the I²C Interface

The SC900 is a read-write slave-mode I²C device and complies with the Philips I²C standard Version 2.1 dated

January 2000. The SC900 has six user-accessible internal 8-bit registers. The I²C interface has been designed for

program flexibility, in that once the slave address has been sent to the SC900 enabling it to be a slave transmitter/

receiver, any register can be written or read from independent of each other. While there is no auto increment/

decrement capability in the SC900 I²C logic, a tight software loop can be designed to randomly access the next

register independent of which register you begin accessing. The start and stop commands frame the data-packet

and the repeat start condition is allowed if necessary.

SC900 Limitations to the I²C Specifications

Seven-bit addressing is required for communicating with the SC900; ten-bit addressing is not allowed. Any general

call address will be ignored by the SC900. Note that the SC900 is not CBUS compatible. Finally, the SC900 can

operate in standard mode (100kbit/s) or fast mode (400kbit/s).

2005 Semtech Corp.

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SC900

POWER MANAGEMENT

Applications Information (Cont.)

Supported Formats

Direct Format - Write

The simplest format for an I²C write is the direct format. After the start condition [S], the slave address is sent,

followed by an eighth bit indicating a write. The SC900 I²C then acknowledges that it is being addressed, and the

master responds with an 8-bit data byte consisting of the register address. The slave acknowledges and the

master sends the appropriate 8-bit data byte. Once again the slave acknowledges and the master terminates the

transfer with the stop condition [P].

I²C Direct Format - Write

S

W

A

Register Address

A

Data

A

Slave Address

P

S : Start Condition

W: Write = '0'

Slave Address : 7 bit

Register Address : 8 bit

Data : 8 Bit

A : Acknowledge (sent by slave)

Sr: Repeated Start Condition

P : Stop Condition

Combined Format - Read

After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC900 I²C

then acknowledges that it is being addressed, and the master responds with an 8-bit data byte consisting of the

register address. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again the

slave address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge and the

previously addressed 8-bit data byte. The master then sends a non-acknowledge (NACK). Finally, the master

terminates the transfer with the stop condition [P].

I²C Combined Format - Read

S

W

A

Register Address

A

R

Slave Address

A

Data

B

Slave Address

Sr

P

Slave Address : 7 bit

Register Address : 8 bit

Data : 8 Bit

S : Start Condition

W: Write = '0'

R : Read = '1'

A : Acknowledge (Sent by Slave)

B : Acknowledge (Sent by Master)

Sr: Repeated Start Condition

P : Stop Condition

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SC900

POWER MANAGEMENT

Applications Information (Cont.)

Stop Separated Reads

Another read format is available which is, in effect, an extension of the combined format read. This format allows

a master to set up the register address pointer for a read and return to that slave some time later to read the data.

After the start condition [S], the slave address is sent, followed by a write. The SC900 I²C then acknowledges that

it is being addressed, and the master responds with the 8-bit register address. The master then sends a stop or

restart condition, and may address another slave. Some time later the master sends a start or restart condition,

and a valid slave address is sent, followed by a read. The SC900 I²C then acknowledges and returns the data at the

register address location that had previously been set up.

2

II2CCSStotopp Separated Format - Read

Master Addresses

Register Address Setup Access

Register Read Access

other Slaves

S/

S

Slave Address AW

A

Register Address

A

Slave Address B

Slave Address AR

A

Data

B

P

S

Sr

S : Start Condition

W: Write = '0'

Slave Address : 7 bit

Register Address : 8 bit

Data : 8 Bit

R : Read = '1'

A : Acknowledge (sent by slave)

B : Acknowledge (sent by master)

Sr: Repeated Start Condition

P : Stop Condition

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SC900

POWER MANAGEMENT

Timing Diagrams

ARST & LDOPGD Timing

LDO A:

V_OUTA

V_TH(A)

T_RD

V_ARST

90% V_ARST

10% V_ARST

LDO A, C, D, & E:

V_OUT

V_TH

T_PGD

V_LDOPGD

90% V_LDOPGD

10% V_LDOPGD

LDO On/Off Control via the I²C Interface

STOP

START

STOP

SCL

SDA

V_LDOn

40us

300us

2005 Semtech Corp.

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SC900

POWER MANAGEMENT

Timing Diagram

Default Start-Up, Shut-Down Timing Diagram

Enable

VREF

LDO A

LDO B

LDO C

LDO D

LDO E

ARST

LDOPGD

200us

15ms

100ms

15ms

2005 Semtech Corp.

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SC900

POWER MANAGEMENT

Typical Characteristics

Dropout Voltage (LDOA)

Dropout Voltage (LDOB-E)

180

160

140

120

100

80

180

160

140

120

100

80

T

_A= 85°C

T_A= 85°C

T_A= -40°C

T_A= 25°C

60

T_A= -40°C

40

20

0

25

50

75

100

125

150

175

200

0

25

50

75

Load Current (mA)

100

125

150

Load Current (mA)

Load Regulation (LDOA-E)

Line Regulation (LDOA-E)

T_A= 25°C, V_IN= 3.7V

V

_IN(MIN)< V_IN< 5.5V

7

6

5

4

3

2

1

0

-0.5

-1

-1.5

-2

-2.5

-3

-3.5

-4

-4.5

0

25

50

75

100

125

150

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

Load Current (mA)

Output Voltage (V)

Output Noise vs. Load Current (LDOA-E)

60

50

40

30

20

10

0

V_OUT= 2.5V

V_OUT= 3.0V

0

25

50

75

100

125

150

175

200

Load Current (mA)

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SC900

POWER MANAGEMENT

Typical Characteristics

Load Transient (LDOA-E)

Line Transient

V_IN= 3.7V, Io = 10mA to 150mA step

V_IN= 3.7V, Io = 100mA

V_IN

500mV/div

Vo

20mV/div

Vo

10mV/div

Io

100mA/div

100µs/div

1ms/div

2005 Semtech Corp.

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SC900

POWER MANAGEMENT

Evaluation Board

PROBE

A

PROBE

B

PROBE

C

PROBE

D

PROBE E

SC900 PWR

TP1

1

AM1

R1

R2

150

R3

0

TP2

1

AM2

D1

LDOPGD

D2

J1

J2

J3

J4

LDOD

J5

TP8

TP7

ARST

LDOA

LDOB

LDOC

LDOE

ARST LDOPGD

R4

U1

7.5K

VIN

Q1

FMMT3904

13

19

2

20

1

VIN

LDOA

LDOB

LDOC

LDOD

LDOE

VREF

INA

INB

INCD

INE

INA

R5

18

16

15

11

INB

7.5K

17

14

5

INCD

INE

Q2

FMMT3904

EN

9

LDOPGD

ARST

SDA

SCL

A0

10

3

4

C2

C3

C4

2.2uF

C5

2.2uF

C6

C7

2.2uF

TP3

TP4

6

8

7

0.1uF

2.2uF

SCLK

SDAT

VASEL

DGND

12

GND

TP9

ENABLE

SC900

R6

J6

1

2

J7

J8

SC900 PWR

GND

R18

100K

VASEL

+5V EXTRNAL

R7

SC900 PWR

TP5

A0

TP6

100K (No-Pop)

J9

4.75k

R8

VASEL

1

2

SC900 PWR

R9

C8

R10

150

10uF

4.75k

SC900 PWR

EXTERNAL SUPPLY

R17

100K

0

D3

R11

100K

ENABLE

SC900 PWR

5

U2

U3

SW1

SC900 PWR

6

18

17

16

15

14

13

12

11

1

2

3

VDD

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

2

1

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

32

31

30

29

28

27

26

25

24

23

22

21

20

19

4

J10

NC7S04

C2DAT

C2CLK

1

2

3

C10

0.1uF

R12

150

R13

150

R14

R15

100K

+5V USB

C11 SC900 Power Select

0.1uF

100K

10

9

P3.0/C2D

C2CK/RST

PROGRAM & DEBUG

7

8

5

4

VREGIN

VBUS

D-

BOARD

D4

D5

EXTERNAL

USB

APPLICATION

I.D.

D+

+5V USB

3

R16

150

GND

J11

F1

1A

C8051F320

C12

C13

1uF

4.7uF

1

2

3

4

D6

USB BUS

USB

VIN

INA

INB

INCD

INE

C1

C9

C14

1uF

C15

1uF

C16

1uF

2005 Semtech Corp.

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SC900

POWER MANAGEMENT

Evaluation Board Gerbers

Top Gerber

Top Silk Screen Gerber

Bottom Gerber

Bottom Silk Screen Gerber

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SC900

POWER MANAGEMENT

Outline Drawing - MLPQ-20L 4 x 4

A

D

B

E

DIMENSIONS

INCHES MILLIMETERS

DIM

A

MIN NOM MAX MIN NOM MAX

.031

.040

0.90 1.00

.035

.001

0.80

A1 .000

.002 0.00 0.02 0.05

-

(.008)

A2

b

(0.20)

PIN 1

0.25 0.30

INDICATOR

(LASER MARK)

.007 .010

.012 0.18

D

.153 .157 .161 3.90 4.00 4.10

2.70

D1

E

.100 .106 .110 2.55

2.80

3.90 4.00 4.10

.153 .157 .161

E1

e

2.70

.100

2.80

.106 .110 2.55

.020 BSC

0.50 BSC

L

N

.011 .016 .020 0.30 0.40 0.50

20

aaa

.004

0.10

A2

bbb

A

SEATING

PLANE

aaa C

A1

C

D1

LxN

E/2

E1

2

1

N

bxN

bbb

C A B

e

D/2

NOTES:

1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).

COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

2.

Marking Information

SC900

yyww

xxxxx

yy = two digit year of manufacture

ww = two digit week of manufacture

xxxxx = lot number

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SC900

POWER MANAGEMENT

Land Pattern - MLPQ-20L 4 x 4

K

DIMENSIONS

INCHES MILLIMETERS

DIM

(.155)

.122

.106

.021

.010

.033

.189

(3.95)

3.10

2.70

0.50

0.25

0.85

4.80

C

G

H

K

P

X

Y

Z

G

Y

(C)

H

X

P

NOTES:

1.

THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.

CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR

COMPANY'S MANUFACTURING GUIDELINES ARE MET.

Contact Information

Semtech Corporation

Power Management Products Division

200 Flynn Road, Camarillo, CA 93012

Phone: (805) 498-2111 FAX (805)498-3804

Visit us at: www.semtech.com

2005 Semtech Corp.

23

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型号:	SC9000
生命周期：	Contact Manufacturer
IHS 制造商：	ADC
Reach Compliance Code：	unknown
风险等级：	5.73
射频/微波设备类型：	COMBINER
Base Number Matches：	1

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