SCF5250CAG120中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

Document Number: SCF5250EC

Rev. 1.1, 04/2005

Freescale Semiconductor

Data Sheet

SCF5250 Integrated ColdFire®

Microprocessor Data Sheet

Table of Contents

Introduction..........................................................1

SCF5250 Block Diagram.....................................8

Documentation ....................................................8

Signal Descriptions..............................................9

Electrical Characteristics...................................21

Pin-Out and Package Information .....................38

1 Introduction

1

2

3

4

5

6

This document provides an overview of the SCF5250

®

ColdFire processor and general descriptions of

SCF5250 features and its various modules.

The SCF5250 was designed as a system

controller/decoder for compressed audio music players,

especially portable and automotive CD and hard disk

drive players. The 32-bit ColdFire core with Enhanced

Multiply Accumulate (EMAC) unit provides optimum

performance and code density for the combination of

control code and signal processing required for audio

decoding and post processing, file management, and

system control.

Low power features include a hardwired CD ROM

decoder, advanced 0.13um CMOS process technology,

1.2V core power supply, and on-chip 128KByte SRAM

that enables Windows Media Audio (WMA) decoding

without the need for external DRAM in CD applications.

The SCF5250 is also an excellent general purpose

system controller with over 110 Dhrystone 2.1 MIPS @

120MHz performance at a very competitive price. The

integrated peripherals and enhanced MAC unit allow the

Introduction

SCF5250 to replace both the microcontroller and the DSP in certain applications. Most peripheral pins can

also be remapped as General Purpose I/O pins.

1.1 Orderable Part Numbers

1.1.1 Orderable Part Table

Table 1. Orderable Part Numbers

Orderable Part

Number

Maximum Clock

Frequency

Operating

Temperature Range

Package Type

Part Status

SCF5250PV120

SCF5250AG120

SCF5250CPV120

SCF5250CAG120

SCF5250VM120

120 MHz

144 pin QFP

-20°C to 70°C

-40°C to 85°C

-20°C to 70°C

Leaded

Lead Free

Leaded

144 pin QFP

Lead Free

196 ball MAPBGA

1.2 SCF5250 Features

1.2.1 ColdFire V2 Core

The ColdFire processor Version 2 core consists of two independent, decoupled pipeline structures to

maximize performance while minimizing core size.The instruction fetch pipeline (IFP) is a two-stage

pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage

operand execution pipeline (OEP), which decodes the instruction, fetches the required operands, and then

executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer

that serves as a FIFO queue, the IFP can prefetch instructions in advance of their actual use by the OEP,

which minimizes time stalled waiting for instructions. The OEP is implemented in a two-stage pipeline

featuring a traditional RISC data path with a dual-read-ported register file feeding an arithmetic/logic unit

(ALU).

1.2.2 DMA Controller

The SCF5250 provides four fully programmable DMA channels for quick data transfer. Single and dual

address mode is supported with the ability to program bursting and cycle stealing. Data transfer is

selectable as 8, 16, 32, or 128-bits. Packing and unpacking is supported.

Two internal audio channels and the dual UART can be used with the DMA channels. All channels can

perform memory to memory transfers. The DMA controller has a user-selectable, 24- or 16-bit counter and

a programmable DMA exception handler.

External requests are not supported.

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

2

Freescale Semiconductor

Introduction

1.2.3 Enhanced Multiply and Accumulate Module (EMAC)

The integrated EMAC unit provides a common set of DSP operations and enhances the integer multiply

instructions in the ColdFire architecture. The EMAC provides functionality in three related areas:

1. Faster signed and unsigned integer multiplies

2. New multiply-accumulate operations supporting signed and unsigned operands

3. New miscellaneous register operations

Multiplies of 16x16 and 32x32 with 48-bit accumulates are supported in addition to a full set of extensions

for signed and unsigned integers plus signed, fixed-point fractional input operands. The EMAC has a

single-clock issue for 32x32-bit multiplication instructions and implements a four-stage execution

pipeline.

1.2.4 Instruction Cache

The instruction cache improves system performance by providing cached instructions to the execution unit

in a single clock. The SCF5250 processor uses a 8K-byte, direct-mapped instruction cache to achieve 107

MIPS at 120 MHz. The cache is accessed by physical addresses, where each 16-byte line consists of an

address tag and a valid bit. The instruction cache also includes a bursting interface for 16-bit and 8-bit port

sizes to quickly fill cache lines.

1.2.5 Internal 128-KByte SRAM

The 128-KByte on-chip SRAM is available in two banks, SRAM0 (64K) and SRAM1 (64K). It provides

one clock-cycle access for the ColdFire core. This SRAM can store processor stack and critical code or

data segments to maximize performance. Memory in SRAM1 can be accessed under DMA.

1.2.6 SDRAM Controller

The SCF5250 SDRAM controller provides a glueless interface for one bank of SDRAM up to 32 MB (256

Mbits). The controller supports a 16-bit data bus. A unique addressing scheme allows for increases in

system memory size without rerouting address lines and rewiring boards. The controller operates in page

mode, non-page mode, and burst-page mode and supports SDRAMS.

1.2.7 System Interface

The SCF5250 provides a glueless interface to 16-bit port size SRAM, ROM, and peripheral devices with

independent programmable control of the assertion and negation of chip-select and write-enable signals.

The SCF5250 also supports bursting ROMs.

1.2.8 External Bus Interface

The bus interface controller transfers information between the ColdFire core or DMA and memory,

peripherals, or other devices on the external bus. The external bus interface provides 23 bits of address bus

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

3

Introduction

space, a 16-bit data bus, Output Enable, and Read/Write signals. This interface implements an extended

synchronous protocol that supports bursting operations.

1.2.9 Serial Audio Interfaces

The SC5250 digital audio interface provides three serial Philips IIS/Sony EIAJ interfaces. One interface

is a 4-pin (1 bit clock, 1 word clock, 1 data in, 1 data out), the other two interfaces are 3-pin (1 bit clock,

1 word clock, 1 data in or out). The serial interfaces have no limit on minimum sampling frequency.

Maximum sampling frequency is determined by maximum frequency on bit clock input. This is 1/3 the

frequency of the internal system clock.

1.2.10 IEC958 Digital Audio Interfaces

The SCF5250 has one digital audio input interface, and one digital audio output interface. The single

output carries the consumer “c” channel.

1.2.11 Audio Bus

The audio interfaces connect to an internal bus that carries all audio data. Each receiver places its received

data on the audio bus and each transmitter takes data from the audio bus for transmission. Each transmitter

has a source select register.

In addition to the audio interfaces, there are six CPU accessible registers connected to the audio bus. Three

of these registers allow data reads from the audio bus and allow selection of the audio source. The other

three register provide a write path to the audio bus and can be selected by transmitters as the audio source.

Through these registers, the CPU has access to the audio samples for processing.

Audio can be routed from a receiver to a transmitter without the data being processed by the core so the

audio bus can be used as a digital audio data switch. The audio bus can also be used for audio format

conversion.

1.2.12 CD-ROM Encoder/Decoder

The SCF5250 is capable of processing CD-ROM sectors in hardware. Processing is compliant with

CD-ROM and CD-ROM XA standards.

The CD-ROM decoder performs following functions in hardware:

•

Sector sync recognition

Descrambling of sectors

Verification of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors

Third-layer error correction is not performed

The CD-ROM encoder performs following functions in hardware:

•

Sector sync recognition

Scrambling of sectors

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

4

Freescale Semiconductor

Introduction

•

Insertion of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors.

Third-layer error encoding needs to be done in software. This can use approximately 5-10 Mhz of

performance for single-speed.

1.2.13 Dual UART Module

Two full-duplex UARTs with independent receive and transmit buffers are in this module. Data formats

can be 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16 increments. Four-byte

receive buffers and two-byte transmit buffers minimize CPU service calls. The Dual UART module also

provides several error-detection and maskable-interrupt capabilities. Modem support includes

request-to-send (RTS) and clear-to-send (CTS) lines.

The system clock provides the clocking function from a programmable prescaler. You can select full

duplex, auto-echo loopback, local loopback, and remote loopback modes. The programmable Dual UARTs

can interrupt the CPU on various normal or error-condition events.

1.2.14 Queued Serial Peripheral Interface QSPI

The QSPI module provides a serial peripheral interface with queued transfer capability. It supports up to

16 stacked transfers at a time, making CPU intervention between transfers unnecessary. Transfers of up to

15 Mbits/second are possible at a CPU clock of 120 MHz. The QSPI supports master mode operation only.

1.2.15 Timer Module

The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer.

Timer0 has an external pin TOUT0, which can be used in Output Compare mode. This mode triggers an

external signal or interrupts the CPU when the timer reaches a set value, and can also generate waveforms

on TOUT0.

The timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is

derived from the system clock. In addition to the ÷1 and ÷16 clock derived from the bus clock (CPU clock

/ 2), the programmable timer-output pins either generate an active-low pulse or toggle the outputs.

1.2.16 IDE and SmartMedia Interfaces

The SCF5250 system bus allows connection of an IDE hard disk drive or SmartMedia flash card with a

minimum of external hardware. The external hardware consists of bus buffers for address and data and are

intended to reduce the load on the bus and prevent SDRAM and Flash accesses to propagate to the IDE

bus. The control signals for the buffers are generated in the SCF5250.

1.2.17 Analog/Digital Converter (ADC)

The six channel ADC is a based on the Sigma-Delta concept with 12-bit resolution. Both the analogue

comparator and digital sections of the ADC are provided internally. An external integrator circuit

(resistor/capacitor) is required, which is driven by the ADC output. A software interrupt is provided when

the ADC measurement cycle is complete.

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

5

Introduction

2

1.2.18 I C Module

The two-wire I C bus interface, which is compliant with the Philips I C bus standard, is a bidirectional

2

serial bus that exchanges data between devices. The I C bus minimizes the interconnection between

devices in the end system and is best suited for applications that need occasional bursts of rapid

communication over short distances among several devices. Bus capacitance and the number of unique

addresses limit the maximum communication length and the number of devices that can be connected.

1.2.19 Chip-Selects

Up to four programmable chip-select outputs provide signals that enable glueless connection to external

memory and peripheral circuits. The base address, access permissions and automatic wait-state insertion

are programmable with configuration registers. These signals also interface to 16-bit ports.

CS0 is active after reset to provide boot-up from external FLASH/ROM.

1.2.20 GPIO Interface

A total of 60 General Purpose inputs and 57 General Purpose outputs are available. These are multiplexed

with various other signals. Seven of the GPIO inputs have edge sensitive interrupt capability.

1.2.21 Interrupt Controller

The interrupt controller provides user-programmable control of a total of 57 interrupts. There are 49

internal interrupt sources. In addition, there are 7 GPIOs where interrupts can be generated on the rising

or falling edge of the pin. All interrupts are autovectored and interrupt levels are programmable.

1.2.22 JTAG

To help with system diagnostics and manufacturing testing, the SCF5250 includes dedicated

user-accessible test logic that complies with the IEEE 1149.1A standard for boundary scan testability,

often referred to as Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1A

standard. Freescale provides BSDL files for JTAG testing.

1.2.23 System Debug Interface

The ColdFire processor core debug interface supports real-time instruction trace and debug, plus

background-debug mode. A background-debug mode (BDM) interface provides system debug.

In real-time instruction trace, four status lines provide information on processor activity in real time (PST

pins). A four-bit wide debug data bus (DDATA) displays operand data and change-of-flow addresses,

which helps track the machine’s dynamic execution path.

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

6

Freescale Semiconductor

Introduction

1.2.24 Crystal and On-chip PLL

Typically, an external 16.92 Mhz or 33.86 Mhz clock input is used for CD R/W applications, while an

11.2896 MHz clock is more practical for Portable CD player applications. However, the on-chip

programmable PLL, which generates the processor clock, allows the use of almost any low frequency

external clock (5-35 Mhz).

Two clock outputs (MCLK1 and MCLK2) are provided for use as Audio Master Clock. The output

frequencies of both outputs are programmable to Fxtal, Fxtal/2, Fxtal/3, and Fxtal/4. The Fxtal/3 option is

only available when the 33.86 Mhz crystal is connected.

The SCF5250 supports VCO operation of the oscillator by means of a 16-bit pulse density modulation

output. Using this mode, it is possible to lock the oscillator to the frequency of an incoming IEC958 or IIS

signal. The maximum trim depends on the type and design of the oscillator. Typically a trim of +/- 100

ppm can be achieved with a crystal oscillator and over +/- 1000 ppm with an LC oscillator.

1.2.25 Boot ROM

The boot ROM on the SCF5250 serves to boot the CPU in designs which do not have external Flash

memory or ROM. Typically this occurs in systems which have a separate MCU to control the system,

and/or the SCF5250 is used as a stand-alone decoder.

The SCF5250 can be booted in one of three modes:

•

External ROM

Internal ROM Master mode – boots from I2C, SPI, or IDE

Internal ROM Slave mode – boots from I2C or UART

1.2.26 Voltage Regulator

The SCF5250 contains an on-chip linear regulator that generates 1.2V from a 3.3V input. The regulator is

self-contained and drives the 1.2V core voltage out on one pin that can be used to power the core supply

pins at the board level. In battery powered portable applications, it is recommended that an external dc-dc

converter be used to generate the 1.2V core voltage to minimize power consumption.

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

7

SCF5250 Block Diagram

2 SCF5250 Block Diagram

I²S Rx

I²S Tx

x2

CD ROM

block encode

& decode

Flash

Media Int

x3

IDE

Interface

12-bit

ADC

SPDIF

Tx

UART x2

DMAs /

Timers

SPDIF

Rx

QSPI

BDM

I²C x2

PLL

1.2V

Regulator

GPI/O

Boot

ROM

JTAG

128K

SRAM

8K

I-Cache

Oscillator

V2

ColdFire^®

Core

System

Bus

Controller

SDRAM Ctr

&

Chip Selects

Figure 1. SCF5250 Block Diagram

3 Documentation

Table 2 lists the documents that provide a complete description of the SCF5250 and are required to design

properly with the part. Documentation is available from a local Freescale distributor, a Freescale

semiconductor sales office, a Freescale Literature Distribution Center, or through the Freescale DSP home

page on the Internet; http://e-www.Freescale.com/ (the source for the latest information).

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

8

Freescale Semiconductor

Signal Descriptions

.

Table 2. SCF5250 Documentation

Document Name

Description

Order Number

CFPRM/D

ColdFire Family Programmer’s Reference Manual

CFPRM/D

ColdFire2UM

Version 2/2M ColdFire Core

Processor User’s Manual

ColdFire2UM/D

ColdFire2UMAD

SCF5250UM

Version 2/2M ColdFire Core

Processor User’s Manual Addendum

ColdFire2UMAD/D

SCF5250UM/D

SCF5250 User’s Manual

4 Signal Descriptions

4.1 Introduction

This section describes the SCF5250 input and output signals. The signal descriptions as shown in Table

2-A are grouped according to relevant functionality.

Table 3. SCF5250 Signal Index

Input/

Output

Reset

State

Signal Name

Address

Mnemonic

Function

A[24:1]

A[23]/GPO54

24 address lines, address line 23

multiplexed with GPO54 and address

24 is multiplexed with A20 (SDRAM

access only).

Out

X

Read-write control

Output enable

Data

R/W

Bus write enable - indicates if read or

write cycle in progress

Out

H

OE

Output enable for asynchronous

memories connected to chip selects

negated

D[31:16]

Data bus used to transfer word data

In/Out

Out

Hi-Z

Synchronous row address SDRAS/GPIO59

strobe

Row address strobe for external

SDRAM.

negated

Synchronous column

address strobe

SDCAS/GPIO39

Column address strobe for external

SDRAM

Out

negated

SDRAM write enable

SDWE/GPIO38

Write enable for external SDRAM

Out

SDRAM upper byte enableSDUDQM/GPO53

Indicates during write cycle if high byte

is written

SDRAM lower byte enable SDLDQM/GPO52

Indicates during write cycle if low byte

is written

Out

SDRAM chip selects

SDRAM clock enable

System clock

SD_CS0/GPIO60

BCLKE/GPIO63

BCLK/GPIO40

SDRAM chip select

SDRAM clock enable

SDRAM clock output

In/Out

Out

negated

In/Out

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

9

Signal Descriptions

Table 3. SCF5250 Signal Index (continued)

Input/

Output

Reset

State

Signal Name

Mnemonic

IDE-DIOR/GPIO31

Function

ISA bus read strobe

There is 1 ISA bus read strobe and 1

ISA bus write strobe. They allow

connection of one independent ISA

bus peripherals, e.g. an IDE slave

device.

In/Out

(CS2)

ISA bus write strobe

IDE-DIOW/GPIO32

(CS2)

In/Out

ISA bus wait signal

Chip Selects[2:0]

IDE-IORDY/GPIO33

ISA bus wait line - available for both

busses

In/Out

CS0/CS4

CS1/QSPI_CS3/GPIO28

Enables peripherals at programmed

addresses.

Out

In/Out

negated

CS[0] provides boot ROM selection

Buffer enable 1

Buffer enable 2

BUFENB1/GPIO29

BUFENB2/GPIO30

Two programmable buffer enables

allow seamless steering of external

buffers to split data and address bus in

sections.

In/Out

Transfer acknowledge

Wake Up

TA/GPIO12

Transfer Acknowledge signal

In/Out

In

WAKE_UP/GPIO21

Wake-up signal input

Serial Clock Line

SCL0/SDATA1_BS1/GPIO41

SCL1/TXD1/GPIO10

Clock signal for Dual I²C module

operation

In/Out

Serial Data Line

Receive Data

Transmit Data

Request-To-Send

Clear-To-Send

Timer Output

SDA0/SDATA3/GPIO42

SDA1/RXD1/GPIO44

Serial data port for second I²C module In/Out

operation

SDA1/RXD1/GPIO44

RXD0/GPIO46

Signal is receive serial data input for

DUART

In

Out

In

SCL1/TXD1/GPIO10

TXD0/GPIO45

Signal is transmit serial data output for

DUART

DDATA3/RTS0/GPIO4

DDATA1/RTS1/SDATA2_BS2/GPIO2 data query

DUART signals a ready to receive

DDATA2/CTSO/GPIO3

DDATA0/CTS1/SDATA0_SDIO1/GPIO1 transmitted to peripheral

Signals to DUART that data can be

SDATAO1/TOUT0/GPIO18

Capable of output waveform or pulse

generation

Out

In

IEC958 inputs

EBUIN1/GPIO36

audio interfaces IEC958 inputs

EBUIN2/SCLK_OUT/GPIO13

EBUIN3/CMD_SDIO2/GPIO14

QSPI_CS0/EBUIN4/GPIO15

IEC958 outputs

Serial data in

Serial data out

Word clock

EBUOUT1/GPIO37

QSPI_CS1/EBUOUT2/GPIO16

audio interfaces IEC958 outputs

audio interfaces serial data inputs

audio interfaces serial data outputs

audio interfaces serial word clocks

Out

In

SDATAI1/GPIO17

SDATAI3/GPIO8

SDATAO1/TOUT0/GPIO18

SDATAO2/GPIO34

In/Out

Out

LRCK1/GPIO19

In/Out

LRCK2/GPIO23

LRCK3/GPIO43/AUDIO_CLOCK

Bit clock

SCLK1/GPIO20

SCLK2/GPIO22

SCLK3/GPIO35

audio interfaces serial bit clocks

In/Out

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

10

Freescale Semiconductor

Signal Descriptions

Table 3. SCF5250 Signal Index (continued)

Mnemonic Function

error flag serial in

Input/

Output

Reset

State

Signal Name

Serial input

EF/GPIO6

In/Out

Serial input

CFLG/GPIO5

C-flag serial in

Subcode clock

RCK/QSPI_DIN/QSPI_DOUT/

GPIO26

audio interfaces subcode clock

Subcode sync

QSPI_DOUT/SFSY/GPIO27

QSPI_CLK/SUBR/GPIO25

XTRIM/GPIO0

audio interfaces subcode sync

audio interfaces subcode data

clock trim control

In/Out

Out

Subcode data

Clock frequency trim

Audio clocks out

MCLK1/GPIO11

DAC output clocks

Out

QSPI_CS2/MCLK2/GPIO24

Audio clock in

LRCK3/GPIO43/AUDIO_CLOCK

Optional Audio clock Input

MemoryStick/SecureDigita EBUIN3/CMD_SDIO2/GPIO14

l interface

Secure Digital command lane

MemoryStick interface 2 data i/o

In/Out

EBUIN2/SCLK_OUT/GPIO13

Clock out for both MemoryStick

interfaces and for Secure Digital

DDATA0/CTS1/SDATA0_SDIO1/GPIO1 SecureDigital serial data bit 0

MemoryStick interface 1 data i/o

SCL0/SDATA1_BS1/GPIO41

SecureDigital serial data bit 1

MemoryStick interface 1 strobe

DDATA1/RTS1/SDATA2_BS2/GPIO2 SecureDigital serial data bit 2

MemoryStick interface 2 strobe

Reset output signal

SDA0/SDATA3/GPIO42

SecureDigital serial data bit 3

In/Out

In

ADC IN

ADIN0/GPI52

ADIN1/GPI53

ADIN2/GPI54

ADIN3/GPI55

ADIN4/GPI56

ADIN5/GPI57

Analog to Digital converter input

signals

ADC OUT

ADREF

ADOUT/SCLK4/GPIO58

Analog to digital convertor output

signal. Connect to ADREF via

integrator network.

In/Out

QSPI clock

QSPI_CLK/SUBR/GPIO25

QSPI clock signal

In/Out

QSPI data in

QSPI data out

RCK/QSPI_DIN/QSPI_DOUT/GPIO26 QSPI data input

RCK/QSPI_DIN/QSPI_DOUT/GPIO26 QSPI data out

QSPI_DOUT/SFSY/GPIO27

QSPI chip selects

QSPI_CS0/EBUIN4/GPIO15

QSPI_CS1/EBUOUT2/GPIO16

QSPI_CS2/MCLK2/GPIO24

CS1/QSPI_CS3/GPIO28

QSPI chip selects

In/Out

Crystal in

CRIN

Crystal input

In

Out

In

Crystal out

CROUT

RSTI

Crystal Out

Reset In

Processor Reset Input

TEST pins.

Freescale Test Mode

Linear regulator output

TEST[2:0]

LINOUT

In

outputs 1.2 V to supply core

Out

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

11

Signal Descriptions

Signal Name

Table 3. SCF5250 Signal Index (continued)

Input/

Output

Reset

State

Mnemonic

Function

Linear regulator input

Linear regulator ground

High Impedance

LININ

LINGND

HI-Z

Input, typically I/O supply (3.3V)

In

Assertion Tri-states all output signal

pins.

Debug Data

DDATA0/CTS1/SDATA0_SDIO1/GPIO1 Displays captured processor data and In/Out

DDATA1/RTS1/SDATA2_BS2/GPIO2 break-point status.

DDATA2/CTS0/GPIO3

Hi-Z

DDATA3/RTS0/GPIO4

Processor Status

PST0/GPIO50

Indicates internal processor status.

In/Out

PST1/GPIO49

PST2/INTMON2/GPIO48

PST3/INTMON1/GPIO47

Processor clock

Test Clock

PSTCLK/GPIO51

TCK

processor clock output

Out

In

Clock signal for IEEE 1149.1A JTAG.

Test Reset/Development TRST/DSCLK

Serial Clock

Multiplexed signal that is

asynchronous reset for JTAG

controller. Clock input for debug

module.

In

Test Mode Select/ Break TMS/BKPT

Point

Multiplexed signal that is test mode

select in JTAG mode and a hardware

break-point in debug mode.

In

Test Data Input /

Development Serial Input

TDI/DSI

Multiplexed serial input for the JTAG or

background debug module.

In

Test Data

Output/DevelopmentSerial

Output

TDO/DSO

Multiplexed serial output for the JTAG

or background debug module.

Out

4.2 GPIO

Many pins have an optional GPIO function.

•

General purpose input is always active, regardless of state of pin.

General purpose output or primary output is determined by the appropriate setting of the Pin

Multiplex Control Registers, GPIO-FUNCTION, GPIO1-FUNCTION and PIN-CONFIG.

•

At Power-on reset, all pins are set to their primary function.

4.3 SCF5250 Bus Signals

These signals provide the external bus interface to the SCF5250.

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

12

Freescale Semiconductor

Signal Descriptions

4.3.1 Address Bus

•

The address bus provides the address of the byte or most significant byte of the word or longword

being transferred.The address lines also serve as the DRAM address pins, providing multiplexed

row and column address signals.

•

Bits 23 down to 1 and 24 of the address are available. A24 is intended to be used with 256 Mbit

DRAM’s. Signals are named:

— A[23:1]

— A20/24

4.3.2 Read-Write Control

This signal indicates during any bus cycle whether a read or write is in progress. A low is write cycle and

a high is a read cycle.

4.3.3 Output Enable

The OE signal is intended to be connected to the output enable of asynchronous memories connected to

chip selects. During bus read cycles, the ColdFire processor will drive OE low.

4.3.4 Data Bus

The data bus (D[31:16]) is bi-directional and non-multiplexed. Data is registered by the SCF5250 on the

rising clock edge. The data bus uses a default configuration if none of the chip-selects or DRAM bank

match the address decode. All 16 bits of the data bus are driven during writes, regardless of port width or

operand size.

4.3.5 Transfer Acknowledge

The TA/GPIO12 pin is the transfer acknowledge signal.

4.4 SDRAM Controller Signals

The following SDRAM signals provide a glueless interface to external SDRAM. An SDRAM width of 16

bits is supported and can access as much as 32MB of memory. ADRAMs are not supported.

Table 4. SDRAM Controller Signals

SDRAM Signal

Description

Synchronous DRAM row address strobe The SDRAS/GPIO59 active low pin provides a seamless interface to the

RAS input on synchronous DRAM

Synchronous DRAM Column Address StrobeThe SDCAS/GPIO39 active low pin provides a seamless interface to

CAS input on synchronous DRAM.

Synchronous DRAM Write

The SDWE/GPIO38 active-low pin is asserted to signify that a SDRAM

write cycle is underway. This pin outputs logic ‘1’ during read bus cycles.

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

13

Signal Descriptions

Table 4. SDRAM Controller Signals (continued)

Description

SDRAM Signal

Synchronous DRAM Chip Enable

The SD_CS0/GPIO60 active-low output signal is used during

synchronous mode to route directly to the chip select of a SDRAM

device.

Synchronous DRAM UDQM and LQDM The DRAM byte enables UDMQ and LDQM are driven by the

signals

SDUDQM/GPO53 and SDLDQM/GPO52 byte enable outputs.

Synchronous DRAM clock

Synchronous DRAM Clock Enable

The DRAM clock is driven by the BCLK/GPIO40 signal

The BCLKE active high output signal is used during synchronous mode

to route directly to the SCKE signal of external SDRAMs. This signal

provides the clock enable to the SDRAM.

4.5 Chip Selects

There are three chip select outputs on the SCF5250 device. CS0/CS4 and CS1/QSPI_CS3/GPIO28 and

CS2 which is associated with the IDE interface read and write strobes - IDE-DIOR and IDE-DIOW.

CS0 and CS4 are multiplexed. The SCF5250 has the option to boot from an internal Boot Rom.

The function of the CS0/CS4 pin is determined by the boot mode. When the device is booted from internal

ROM, the internal ROM is accessed with CS0 (required for boot) and the CS0/CS4 pin is driven by CS4.

When the device is booted from external ROM / Flash, the CS0/CS4 pin is driven by CS0 and the internal

ROM is disabled.

The active low chip selects can be used to access asynchronous memories. The interface is glueless.

4.6 ISA bus

The SCF5250 supports an ISA bus. Using the ISA bus protocol, reads and writes for one ISA bus

peripheral is possible. IDE-DIOR/GPIO31 and IDE-DIOW/GPIO32 are the read and write strobe. The

peripheral can insert wait states by pulling IDE-IORDY/GPIO33.

CS2 is associated with the IDE-DIOR and IDE-DIOW.

4.7 Bus Buffer Signals

As the SCF5250 has a complicated slave bus, which allows SDRAM, asynchronous memories, and ISA

peripherals on the bus, it may become necessary to introduce a buffer on the bus in certain applications.

The SCF5250 has a glueless interface to steer these bus buffers with two bus buffer output signals

BUFENB1/GPIO29 and BUFENB2/GPIO30.

4.8 I²C Module Signals

2

There are two I C interfaces on this device.

2

The I C module acts as a two-wire, bidirectional serial interface between the SCF5250 processor and

2

peripherals with an I C interface (e.g., LED controller, A-to-D converter, D-to-A converter). When

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

14

Freescale Semiconductor

Signal Descriptions

2

devices connected to the I C bus drive the bus, they will either drive logic-0 or high-impedance. This can

be accomplished with an open-drain output.

2

Table 5. I C Module Signals

I²c Module Signal

Description

I²C Serial Clock

The SCL0/SDATA1_BS1/GPIO41 and SCL1/TXD1/GPIO10

bidirectional signals are the clock signal for first and second I²C module

operation. The I²C module controls this signal when the bus is in master

mode; all I²C devices drive this signal to synchronize I²C timing.

Signals are multiplexed

I²C Serial Data

The SDA0/SDATA3/GPIO42 and SDA1/RXD1/GPIO44 bidirectional

signals are the data input/output for the first and second serial I²C

interface.

Signals are multiplexed

4.9 Serial Module Signals

The following signals transfer serial data between the two UART modules and external peripherals.

Table 6. Serial Module Signals

Serial Module Signal

Description

Receive Data

The RXD0/GPIO46 and SDA1/RXD1/GPIO44 are the inputs on which

serial data is received by the DUART. Data is sampled on RxD[1:0] on

the rising edge of the serial clock source, with the least significant bit

received first.

Transmit Data

The DUART transmits serial data on the TXD0/GPIO45 and

SCL1/TXD1/GPIO10 output signals. Data is transmitted on the falling

edge of the serial clock source, with the least significant bit transmitted

(LSB) first. When no data is being transmitted or the transmitter is

disabled, these two signals are held high. TxD[1:0] are also held high in

local loopback mode.

Request To Send

Clear To Send

The DDATA3/RTS0/GP104 and DDATA1/RTS1/SDATA2_BS2/GPIO2

request-to-send outputs indicate to the peripheral device that the

DUART is ready to send data and requires a clear-to-send signal to

initiate transfer.

Peripherals drive the DDATA2/CTS0/GPIO3 and

DDATA0/CTS1/SDATA0_SDIO1/GPIO1 inputs to indicate to the

SCF5250 serial module that it can begin data transmission.

4.10 Timer Module Signals

The following signal provides an external interface to Timer0.

Table 7. Timer Module Signals

Serial Module Signal

Description

Timer Output

The SDATAO1/TOUT0/GPIO18 programmable output pulse or toggle

on various timer events.

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

15

Signal Descriptions

4.11 Serial Audio Interface Signals

The following signals provide the external audio interface.

Table 8. Serial Audio Interface Signals

Serial Module Signal

Description

Serial Audio Bit Clock

The SCLK1/GPIO20, SCLK2/GPIO22 and SCLK3/GPIO35,

multiplexed pins can serve as general purpose I/Os or serial audio bit

clocks. As bit clocks, these bidirectional pins can be programmed as

outputs to drive their associated serial audio (IIS) bit clocks. Alternately,

these pins can be programmed as inputs when the serial audio bit

clocks are driven internally. The functionality is programmed within the

Audio module. During reset, these pins are configured as input serial

audio bit clocks.

Serial Audio Word Clock

The LRCK1/GPIO19, LRCK2/GPIO23 and

LRCK3/GPIO43/AUDIO_CLOCK multiplexed pins can serve as general

purpose I/Os or serial audio word clocks. As word clocks, the

bidirectional pins can be programmed as inputs to drive their associated

serial audio word clock. Alternately, these pins can be programmed as

outputs when the serial audio word clocks are derived internally. The

functionality is programmed within the Audio module. During reset,

these pins are configured as input serial audio word clocks.

LRCK3/GPIO43/AUDIO_CLOCK can be used as the external audio

clock input. If the core clock chosen to be non-audio specific.

Serial Audio Data In

The SDATAI1/GPIO17 and SDATAI3/GPIO8 multiplexed pins can serve

as general purpose I/Os or serial audio inputs. As serial audio inputs the

data is sent to interfaces 1and 3 respectively. During reset, the pins are

configured as serial data inputs.

Serial Audio Data Out

Serial audio error flag

SDATO1/TOUT0/GPIO18 AND SDATAO2/GPIO34 multiplexed pins can

serve as general purpose I/Os or serial audio outputs. During reset, the

pins are configured as serial data outputs.

The EF/GPIO6 multiplexed pin can serve as general purpose I/Os or

error flag input. As error flag input, this pin will input the error flag

delivered by the CD-DSP. EF/GPIO6 is only relevant for serial interface

SDATAI1.

Serial audio CFLG

The CFLG/GPIO5 multiplexed pin can serve as general purpose I/O or

CFLG input. As CFLG input, the pin will input the CFLG flag delivered

by the CD-DSP. CFLG/GPIO5 is only relevant for serial interface

SDATAI1.

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

16

Freescale Semiconductor

Signal Descriptions

4.12 Digital Audio Interface Signals

Table 9. Digital Audio Interface Signals

Serial Module Signal

Description

The EBUIN1/GPIO36, EBUIN2/SCLK_OUT/GPIO13,

Digital Audio In

EBUIN3/CMD_SDIO2/GPIO14, and QSPI_CS0/EBUIN4/GPIO15

multiplexed signals can serve as general purpose input or can be driven

by various digital audio (IEC958) input sources. Both functionalities are

always active. Input chosen for IEC958 receiver is programmed within

the audio module. Input value on the 4 pins can always be read from the

appropriate GPIO register.

Digital Audio Out

The EBUOUT1/GPIO37 and QSPI_CS1/EBUOUT2/GPIO16

multiplexed pins can serve as general purpose I/O or as digital audio

(IEC958) output. EBUOUT1 is digital audio out for consumer mode,

EBUOUT2 is digital audio out for professional mode. During reset, the

pin is configured as a digital audio output.

4.13 Subcode Interface

There is a 3-line subcode interface on the SCF5250. This 3-line subcode interface allows the device to

format and transmit subcode in EIAJ format to a CD channel encoder device. The three signals are

described in Table 10.

Table 10. Subcode Interface Signal

Signal name

Description

RCK/QSPI_DIN/QSPI_DOUT/GPIO26

Subcode clock input. When pin is used as subcode clock, this pin is

driven by the CD channel encoder.

QSPI_DOUT/SFSY/GPIO27

QSPI_CLK/SUBR/GPIO25

Subcode sync output

This signal is driven high if a subcode sync needs to be inserted in the

EFM stream.

Subcode data output

This signal is a subcode data out pin.

4.14 Analog to Digital Converter (ADC)

The ADOUT signal on the ADOUT/SCLK4/GPIO58 pin provides the reference voltage in PWM format.

This output requires an external integrator circuit (resistor/capacitor) to convert it to a DC level to be input

to the ADREF pin.

The six AD inputs are each fed to their own comparator. The reference input to each (ADREF) is then

multiplexed as only one AD comparison can be made at any one time.

NOTE

To use the ADINx as General Purpose inputs (rather than there analogue

function) it is necessary to generate a fixed comparator voltage level of

VDD/2. This can be accomplished by a potential divider network connected

to the ADREF pin. However in portable applications where stand-by power

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

17

Signal Descriptions

consumption is important the current taken by the divider network (in

stand-by mode) could be excessive. Therefore it is possible to generate a

VDD/2 voltage by selecting SCLK4 output mode and feeding this clock

signal (which is 50% duty cycle) through an external integration circuit.

This would generate a voltage level equal to VDD/2 but would be disabled

when stand-by mode was selected.

4.15 Secure Digital/ MemoryStick Card Interface

The device has a versatile flash card interface that supports both SecureDigital and MemoryStick cards.

The interface can either support one SecureDigital or two MemoryStick cards. No mixing of card types is

possible. Table 11 gives the pin descriptions.

Table 11. Flash Memory Card Signals

Flash Memory Signal

Description

EBUIN2/SCLKOUT/GPIO13

Clock out for both MemoryStick interfaces and for SecureDigital

EBUIN3/CMD_SDIO2/GPIO14

Secure Digital command line

MemoryStick interface 2 data i/o

DDATAO/CTS1/SDATA0_SDIO1/GPIO1 SecureDigital serial data bit 0

MemoryStick interface 1 data i/o

SCL0/SDATA1_BS1/GPIO41

SecureDigital serial data bit 1

MemoryStick interface 1 strobe

DDATA1/RTS1/SDATA2_BS2/GPIO2

SecureDigital serial data bit 2

MemoryStick interface 2 strobe

Reset output signal

Selection between Reset function and SDATA2_BS2 is done by

programming PLLCR register.

SDA0/SDATA3/GPIO42

SecureDigital serial data bit 3

4.16 Queued Serial Peripheral Interface (QSPI)

The QSPI interface is a high-speed serial interface allowing transmit and receive of serial data. Pin

descriptions are given in Table 12.

Table 12. Queued Serial Peripheral Interface (QSPI) Signals

Serial Module Signal

Description

QSPICLK/SUBR/GPIO25

Multiplexed signal IIC interface clock or QSPI clock output

Function select is done via PLLCR register.

RCK/QSPIDIN/QSPI_DOUT/GPIO26

Multiplexed signal IIC interface data or QSPI data input.

Function select is done via PLLCR register.

RCK/QSPI_DIN/QSPI_DOUT/GPIO26

QSPI_DOUT/SFSY/GPIO27

QSPI data output

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

18

Freescale Semiconductor

Signal Descriptions

Table 12. Queued Serial Peripheral Interface (QSPI) Signals (continued)

Serial Module Signal

Description

QSPICS0/EBUIN4GPIO15

QSPICS1/EBUOUT2/GPIO16

QSPICS2/MCLK2/GPIO24

CS1/QSPICS3/GPIO28

4 different QSPI chip selects

4.17 Crystal Trim

The XTRIM/GPIO0 output produces a pulse-density modulated phase/frequency difference signal to be

used after low-pass filtering to control varicap-voltage to control crystal oscillation frequency. This will

lock the crystal to the incoming digital audio signal.

4.18 Clock Out

The MCLK1/GPIO11 and QSPI_CS2/MCLK2/GPIO24 can serve as DAC clock outputs. When

programmed as DAC clock outputs, these signals are directly derived from the crystal oscillator or clock

Input (CRIN).

4.19 Debug and Test Signals

These signals interface with external I/O to provide processor debug and status signals.

4.19.1 Test Mode

The TEST[2:0] inputs are used for various manufacturing and debug tests. For normal mode TEST [2:1]

should be ways be tied low. TEST0 should be set high for BDM debug mode and set low for JTAG mode.

4.19.2 High Impedance

The assertion of HI_Z will force all output drivers to a high-impedance state. The timing on HI_Z is

independent of the clock.

NOTE

JTAG operation will override the HI_Z pin.

4.19.3 Processor Clock Output

The internal PLL generates this PSTCLK/GPIO51 and output signal, and is the processor clock output that

is used as the timing reference for the Debug bus timing (DDATA[3:0] and PST[3:0]). The

PSTCLK/GPIO51 is at the same frequency as the core processor.

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

19

Signal Descriptions

4.19.4 Debug Data

The debug data pins, DDATA0/CTS1/SDATA0_SDIO1/GPIO1, DDATA1/RTS1/SDATA2_BS2/GPIO2,

DDATA2/CTS0/GPIO3, and DDATA3/RTS0/GPIO4, are four bits wide. This nibble-wide bus displays

captured processor data and break-point status.

4.19.5 Processor Status

The processor status pins, PST0/GPIO50, PST1/GPIO49, PST2/INTMON/GPIO48, and

PST3/INTMON/GPIO47, indicate the SCF5250 processor status. During debug mode, the timing is

synchronous with the processor clock (PSTCLK) and the status is not related to the current bus transfer.

Table 13 shows the encodings of these signals.

.

Table 13. Processor Status Signal Encodings

PST[3:0]

Definition

(HEX)

(BINARY)

$0

$1

$2

$3

$4

$5

$6

$7

$8

$9

$A

$B

$C

$D

$E

$F

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Continue execution

Begin execution of an instruction

Reserved

Entry into user-mode

Begin execution of PULSE and WDDATA instructions

Begin execution of taken branch or Synch_PC¹

Reserved

Begin execution of RTE instruction

Begin 1-byte data transfer on DDATA

Begin 2-byte data transfer on DDATA

Begin 3-byte data transfer on DDATA

Begin 4-byte data transfer on DDATA

Exception processing²

Emulator mode entry exception processing²

Processor is stopped, waiting for interrupt²

Processor is halted²

Rev. B enhancement.

These encodings are asserted for multiple cycles.

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

20

Freescale Semiconductor

Electrical Characteristics

4.20 BDM/JTAG Signals

The SCF5250 complies with the IEEE 1149.1A JTAG testing standard. The JTAG test pins are multiplexed

with background debug pins.

4.21 Clock and Reset signals

These signals configure the SCF5250 and provide interface signals to the external system.

4.21.1 Reset In

Asserting RSTI causes the SCF5250SCF5250 to enter reset exception processing. When RSTI is

recognized, the data bus is tri-stated.

4.21.2 Clock Input

SCF5250 includes on -chip crystal oscillator. The crystal should be connected between CRIN and CROUT.

An externally generated clock signal can also be used and should be connected directly to the CRIN pin.

4.22 Wake-Up Signal

To exit power down mode, apply a LOW level to the WAKE_UP/GPIO21 input pin.

4.23 On-chip Linear Regulator

The SCF5250 includes an on-chip linear regulator. This regulator provides an 1.2 V output which is

intended to be used to power the SCF5250 core. Three pins are associated with this function.

LININ, LINOUT and LINGND. Typically LININ would be fed by the I/O (PAD) supply (3.3 V) with

separate filtering recommended to provide some isolation between the I/O and the core.

In portable solutions this linear regulator may not be efficient enough and in this case we would expect the

1.2 V supply to be generated externally, possibly by a highly efficient DC-DC convertor.

If not used leave pins not connected.

5 Electrical Characteristics

Table 14. Maximum Ratings

Rating

Supply Core Voltage

Symbol

Value

Units

V_cc

-0.5 to +2.5

+1.32

V

Maximum Core Operating Voltage

Minimum Core Operating Voltage

+1.08

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

21

Electrical Characteristics

Table 14. Maximum Ratings (continued)

Rating

Symbol

Value

Units

Supply I/O Voltage

V_cc

V_in

-0.5 to +4.6

+3.6

V

Maximum I/O Operating Voltage

Minimum I/O Operating Voltage

Input Voltage

+3.0

V

-0.5 to +6.0

-65 to150

V

Storage Temperature Range

T_stg

^oC

Table 15. Operating Temperature

Symbol

Characteristic

Value

Units

Maximum Operating Ambient Temperature

Minimum Operating Ambient Temperature

T_Amax

T_Amin

85¹

-40

^οC

^oC

Note: This published maximum operating ambient temperature should be used only as a system design guideline. All device

operating parameters are guaranteed only when the junction temperature does not exceed 105^°C.

Table 16. Recommended Operating Supply Voltages

Pin Name

CORE-VDD

Min

Typ

Max

1.08V

1.2V

gnd

3.3v

gnd

3.3v

gnd

3.3v

gnd

1.2V

gnd

1.2v

gnd

3.3V

1.32V

---

CORE-VSS

PAD-VDD

3.0V

3.6V

PAD-VSS

ADVDD

3.6V

ADGND

OSCPAD-VDD

OSCPAD-GND

PLLCORE1VDD

PLLCORE1GND

PLLCORE2VDD

PLLCORE2GND

LIN

3.0V

1.08V

3.0v

1.32V

3.6V

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

22

Freescale Semiconductor

Electrical Characteristics

Table 17. Linear Regulator Operating Specification

Characteristic

Input Voltage

Symbol

Min

Typ

Max

Vin

Vout

Iout

Pd

3.0V

3.3V

1.2V

3.6

Output Voltage (LINOUT)

Output Current

1.14V

1.26V

100mA

150mA

436uW

60mV

Power Dissipation

Load Regulation

10% Iout -> 90% Iout

40mV

50mV

40dB

Power Supply Rejection

PSRR

Note: A pmos regulator is employed as a current source in this Linear regulator, so

a 10µF capacitor (ESR 0 ... 5 Ohm) is needed on the output pin (LINOUT) to

integrate the current. Typically this will require the use of a Tantalum type

capacitor.

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

23

Electrical Characteristics

Table 18. DC Electrical Specifications (I/O Vcc = 3.3 Vdc + 0.3 Vdc)

Characteristic

Operation Voltage Range for I/O

Symbol

Min

Max

Units

V_cc

V_IH

V_IL

I_in

3.0

2

3.6

5.5

0.8

±1

V

Input High Voltage

Input Low Voltage

-0.3

-

V

Input Leakage Current @ 0.0 V /3.3 V

During Normal Operation

µµA

Hi-Impedance (Three-State) Leakage Current

@ 0.0 V/3.3 V During Normal Operation

I_TSI

-

±1

µµA

Output High Voltage I_OH= 8mA¹, 4mA², 2mA³

Output Low Voltage I_OL= 8mA¹, 4mA², 2mA³

Schmitt Trigger Low to High Threshold Point⁶

Schmitt Trigger High to Low Threshold Point⁶

V_OH

V_OL

V_T+

V_T-

2.4

-

V

-

0.4

-

1.47

V

-

.95

50

V

Load Capacitance (DATA[31:16], SCLK[4:1], SCLKOUT,

EBUOUT[2:1], LRCK[3:1], SDATAO[2:1], CFLG, EF, DDATA[3:0],

PST[3:0], PSTCLK, IDE-DIOR, IDE-DIOW, IORDY)

C_L

pF

Load Capacitance (ADDR[24:9], BCLK)

C_L

-

40

30

pF

Load Capacitance (BCLKE, SDCAS, SDRAS, SDLDQM,

SD_CS0, SDUDQM, SDWE, BUFENB[2:1])

Load Capacitance (SDA0, SDA1, SCL0, SCL1, CMD_SDIO2,

SDATA2_BS2, SDATA1_BS1, SDATA0_SDIO1, CS0/CS4, CS1,

OE, R/W, TA, TXD[1:0], XTRIM, TDO/DSO, RCK, SFSY, SUBR,

SDATA3, TOUT0, QSPID_OUT, QSPICS[3:0], GP[6:5])

C_L

-

20

pF

Capacitance⁵, V_in= 0 V, f = 1 MHz

C_IN

-

6

pF

DATA[31:16], ADDR[24:9], PSTCLK, BCLK

SCL, SDA, PST[3:0], DDATA[3:0], TDSO, SDRAS, SDCAS, SDWE, SD_CS0, SDLDQM, SDUDQM, R/W

TOUT0, RTS[1:0], TXD[1:0], SCLK[4:1]

BKPT/TMS, DSI/TDI, DSCLK/TRST

Capacitance C is periodically sampled rather than 100% tested.

IN

SCLK[4:1], SCL0, SCL1, SDA0, SDA1, CRIN, RSTI

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

24

Freescale Semiconductor

Electrical Characteristics

Table 19. Clock Timing Specification

NUM

Characteristic

Min

Units

Max

CRIN Frequency¹

5.00

7.1

40

33.86

—

MHz

nSec

%

C5

C6

C7

C8

PSTCLK cycle time

PSTCLK duty cycle

BCLK cycle time

BCLK duty cycle

60

14.2

45

—

nSec

%

55

Note: There are only three choices for the valid Audio frequencies 11.29 MHz, 16.93 MHz, or

33.86 MHz; no other values are allowed. The System Clock is derived from one of these

crystals via an internal PLL.

CRIN

PSTCLK

C6

C7

BCLK

C8

Figure 2. Clock Timing Definition

NOTE

Signals above are shown in relation to the clock. No relationship between

signals is implied or intended.

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

25

Electrical Characteristics

Table 20. Input AC Timing Specification

Num

Characteristic

Min

Units

Max

B1^1,2

B2¹

Signal Valid to BCLK Rising (setup)

3

2

—

5

nSec

BCLK Rising to signal Invalid (hold)

BCLK to Input High Impedance

B3¹

—

BCLK

cycle

1.

2.

Inputs (rising): DATA[31:16]

AC timing specs assume 40pF load capacitance on BCLK and 50pF load capacitance on

output pins. If this value is different, the input and output timing specifications would need to

be adjusted to match the clock load.

Table 21. Output AC Timing Specification

Num

Characteristic⁵

Units

Min

Max

• B10¹BCLK (8mA) Rising to signal Valid

• B11¹BCLK (8mA) Rising to signal Invalid (hold)

• B10²BCLK (4mA) Rising to signal Valid

• B11²BCLK (4mA) Rising to signal Invalid (hold)

---

3.5

---

4

10

—

11

—

14

nSec

• B12³BCLK to High Impedance

(Three-State)

---

• H1

• H2

HIZ to High Impedance

HIZ to Low Impedance

—

tbd

nSec

1. Outputs (8mA): DATA[31:16], ADDR[25,23:9]

2. Outputs (4mA): SDRAS, SDCAS, SDWE, SD_CS0, SDUDQM, SDLDQM, BCLKE

3. High Impedance (Three-State): DATA[31:16]

4. AC timing specs assume 40pF load capacitance on BCLK and a 50pF load capacitance on output

pins. If this value is different, the input and output timing specifications would need to be adjusted

to match the clock load.

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

26

Freescale Semiconductor

Electrical Characteristics

Figure 3. Input/Output Timing Definition-I

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

27

Electrical Characteristics

B3

B4

BCLK

INPUTS

B13

B14

BCLK

OUTPUTS

H1

H2

HIZ

OUTPUTS

Figure 4. Input/Output Timing Definition-III

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

28

Freescale Semiconductor

Electrical Characteristics

Table 22. Debug AC Timing Specification

Characteristic

Num

Units

Min

Max

D1

D2

PSTCLK to signal Valid (Output valid)

PSTCLK to signal Invalid (Output hold)

Signal Valid to PSTCLK (Input setup)

PSTCLK to signal Invalid (Input hold)

---

1.8

3

6

nSec

—

D3¹

D4

5

1. DSCLK and DSI are internally synchronized. This setup time must be met only if recognition

on a particular clock is required.

2. AC timing specs assume 50pF load capacitance on PSTCLK and output pins. If this value is

different, the input and output timing specifications would need to be adjusted to match the

clock load.

PSTCLK

D4

D3

DSCLK

DSI

D4

D1

PST[3:0]

DDATA[3:0]

DSO

D2

Figure 5. Debug Timing Definition

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

29

Electrical Characteristics

Table 23. Timer Module AC Timing Specification

Characteristic

Num

Units

Min

Max

T1

T2

T3

T4

T5

T6

T7

TIN Cycle time

3T

6

—

10

—

bus clocks

nSec

TIN Valid to BCLK (input setup)

BCLK to TIN Invalid (input hold)

BCLK to TOUT Valid (output valid)

BCLK to TOUT Invalid (output hold)

TIN Pulse Width

0

nSec

—

tbd

1T

nSec

bus clocks

TOUT Pulse Width

BCLK

TIN

T6

T2

T3

T1

TIN

T7

TOUT

T4

T5

Figure 6. Timer Module Timing Definition

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

30

Freescale Semiconductor

Electrical Characteristics

Table 24. UART Module AC Timing Specifications

Characteristic

Num

Units

Min

Max

U1

U2

U3

U4

U5

U6

U7

U8

RXD Valid to BCLK (input setup)

BCLK to RXD Invalid (input hold)

CTS Valid to BCLK (input setup)

BCLK to CTS Invalid (input hold)

BCLK to TXD Valid (output valid)

BCLK to TXD Invalid (output hold)

BCLK to RTS Valid (output valid)

BCLK to RTS Invalid (output hold)

6

0

—

nSec

6

—

0

—

---

3

tbd

—

---

3

tbd

—

BCLK

RXD

U1

U2

U3

CTS

U4

U6

U8

U5

U7

TXD

RTS

Figure 7. UART Timing Definition

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

31

Electrical Characteristics

Table 25. I2C-Bus Input Timing Specifications Between SCL and SDA

Num

Characteristic

Units

Min

Max

M1

M2

M3

Start Condition Hold Time

2

8

—

1

bus clocks

mSec

Clock Low Period

SCL/SDA Rise Time

—

(VIL= 0.5 V to VIH = 2.4 V)

M4

M5

Data Hold Time

0

—

1

nSec

SCL/SDA Fall Time

—

mSec

(VIH= 2.4 V to VIL = 0.5 V)

M6

M7

M8

Clock High time

Data Setup Time

4

0

2

—

bus clocks

nSec

Start Condition Setup Time

bus clocks

(for repeated start condition only)

M9

Stop Condition Setup Time

2

—

bus clocks

Table 26. I2C-Bus Output Timing Specifications Between SCL and SDA

Num

Characteristic

Units

Min

Max

M1¹

M2¹

M3²

Start Condition Hold Time

6

—

bus clocks

mSec

Clock Low Period

10

SCL/SDA Rise Time

note 2 note 2

(V_IL= 0.5 V to V_IH= 2.4 V)

M4¹

M5³

Data Hold Time

7

—

3

bus clocks

nSec

SCL/SDA Fall Time

—

(V_IH= 2.4 V to V_IL= 0.5 V)

M6¹

M7¹

M8¹

Clock High time

Data Setup Time

10

2

—

bus clocks

Start Condition Setup Time

20

(for repeated start condition only)

M9¹

Stop Condition Setup Time

10

—

bus clocks

1. Note: Output numbers are dependent on the value programmed into the MFDR; an MFDR programmed

with the maximum frequency (MFDR = 0x20) will result in minimum output timings as shown in the above

table. The MBUS interface is designed to scale the actual data transition time to move it to the middle of

the SCL low period. The actual position is affected by the prescale and division values programmed into

the MFDR; however, numbers given in the above table are the minimum values.

2. Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the

time required for SCL or SDA to reach a high level depends on external signal capacitance and pull-up

resistor values.

3. Specified at a nominal 20 pF load.

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

32

Freescale Semiconductor

Electrical Characteristics

M2

M6

M5

SCL

SDA

M3

M1

M4

M7

M8

M9

Figure 8. I2C Timing Definition

Table 27. I2C Output Bus Timings

Characteristic

96 MHz

Num

Units

Min

Max

M10³

M11

SCL, SDA Valid to BCLK (input setup)

BCLK to SCL, SDA Invalid (input hold)

BCLK to SCL, SDA Low (output valid)

BCLK to SCL, SDA Invalid (output hold)

2

4.5

—

3

—

10

—

nSec

M12¹

M13²

1.

Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this

specification applies only when SCL or SDA are driven low by the processor. The time required for SCL or

SDA to reach a high level depends on external signal capacitance and pull-up resistor values.

2.

3.

Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this

specification applies only when SCL or SDA are actively being driven or held low by the processor.

SCL and SDA are internally synchronized.This setup time must be met only if recognition on a particular

clock is required.

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

33

Electrical Characteristics

M10

BCLK

SCL, SDA IN

M11

M12

SCL, SDA OUT

M13

Figure 9. I2C and System Clock Timing Relationship

Table 28. General-Purpose I/O Port AC Timing Specifications

Num

Characteristic

Units

Min

Max

P1

P2

P3

P4

GPIO Valid to BCLK (input setup)

BCLK to GPIO Invalid (input hold)

BCLK to GPIO Valid (output valid)

BCLK to GPIO Invalid (output hold)

6

0

—

nSec

—

1

tbd

—

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

34

Freescale Semiconductor

Electrical Characteristics

BCLK

P1

GPIO IN

P2

P4

P3

GPIO OUT

Figure 10. General-Purpose Parallel Port Timing Definition

Table 29. IEEE 1149.1 (JTAG) AC Timing Specifications

Characteristic

Num

Units

Min

Max

-

TCK Frequency of Operation

TCK Cycle Time

0

100

25

—

10

-

MHz

nSec

J1

J2a

J2b

J3a

TCK Clock Pulse High Width

TCK Clock Pulse Low Width

-

TCK Fall Time

5

(V_IH=2.4 V to V_IL=0.5 V)

J3b

TCK Rise Time

—

5

nSec

(V_IL=0.5 v to V_IH=2.4 V)

J4

J5

J6

J7

J8

TDI, TMS to TCK rising (Input Setup)

8

—

nSec

TCK rising to TDI, TMS Invalid (Hold)

10

tbd

12

Boundary Scan Data Valid to TCK (Setup)

TCK to Boundary Scan Data Invalid to rising edge (Hold)

TRST Pulse Width

(asynchronous to clock edges)

J9

TCK falling to TDO Valid

—

15

nSec

(signal from driven or three-state)

J10

J11

TCK falling to TDO High Impedance

—

15

nSec

TCK falling to Boundary Scan Data Valid

(signal from driven or three-state)

tbd

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

35

Electrical Characteristics

Table 29. IEEE 1149.1 (JTAG) AC Timing Specifications (continued)

Num

Characteristic

Units

Min

Max

J12

TCK falling to Boundary Scan

Data High Impedance

—

tbd

nSec

J1

J3A

J2A

J2B

TCK

J3B

J4

TDI, TMS

J5

J6

BOUNDARY

SCAN DATA

INPUT

J7

TRST

TDO

J8

J9

J10

J12

J11

BOUNDARY

SCAN DATA

OUTPUT

Figure 11. JTAG Timing

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

36

Freescale Semiconductor

Electrical Characteristics

5.1 IIS Module AC Timing Specifications

Table 30. SCLK INPUT, SDATAO OUTPUT Timing Specifications

Name

Characteristic

Unit

Min

Max

TU

TD

SCLK fall to SDATAO rise

SCLK fall to SDATAO fall

---

25

ns

SCLK (INPUT)

SDATAO1, 2 (OUTPUT)

TU

TD

Figure 12. SCLK Input, SDATA Output Timing

Table 31. SCLK OUTPUT, SDATA0 OUTPUT Timing Specifications

Characteristic

Name

Unit

Min

Max

TU

TD

SCLK fall to SDATAO rise

SCLK fall to SDATAO fall

---

3

ns

SCLK (OUTPUT)

SDATAO1, 2 (OUTPUT)

TU

TD

Figure 13. SCLK Output, SDATAO Output Timing Diagram

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

37

Pin-Out and Package Information

Table 32. SCLK INPUT, SDATAI INPUT Timing Specifications

Name

Characteristic

Unit

Min

Max

TSU SDATAI IN to SCLKn

TH SCLK rise to SDATAI

-5

3

—

ns

SCLK

(INPUT OR OUTPUT)

SDATA1, 3, 4 (INPUT)

TSU

TH

Figure 14. SCLK Input/Output, SDATAI Input Timing Diagram

6 Pin-Out and Package Information

6.1 Pinning Chart

Table 33. 144 QFP Pin Assignments

144 QFP

Number

Pin State

After Reset

Name

Type

Description

01

02

DATA16

I/O

Data

X

A23/GPO54

SDRAM address / static adr

Out (requires pull

up /down for

boot-up selection)

03

04

05

06

07

08

PAD-VDD

A22

O

SDRAM address / static adr

Out

A21

A20/A24

A19

A18

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

38

Freescale Semiconductor

Pin-Out and Package Information

Table 33. 144 QFP Pin Assignments (continued)

144 QFP

Number

Pin State

After Reset

Name

Type

Description

09

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

PAD-GND

A17

O

SDRAM address / static adr

Out

A16

A15

A14

A13

PAD-VDD

A12

O

SDRAM address / static adr

Out

A11

CORE-VDD

CORE-GND

A10

O

SDRAM address / static adr

PAD-GND

Out

A9

A8

A7

A6

A5

PAD-GND

A4

O

o

SDRAM address / static adr

Out

A3

A2

A1

CS0/CS4

Static chip select 0 / static chip

select 4

32

33

34

RW

OSC PAD VDD

CRIN

o

I

Bus write enable

Out

X

Crystal / external clock input

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

39

Pin-Out and Package Information

144 QFP

Table 33. 144 QFP Pin Assignments (continued)

Pin State

After Reset

Name

Type

Description

Number

35

36

37

38

39

40

41

42

43

44

45

46

47

CROUT

O

Crystal clock output

X

OSC PAD GND

PLL CORE1 VDD

PLL CORE2 VDD

PLL CORE2 GND

PLL CORE1 GND

OE

OSC_PAD_GND

O

Output Enable

Out

IDE-DIOW/GPIO32

IDE-IORDY/GPIO33

IDE-DIOR/GPIO31

BUFENB2/GPIO30

BUFENB1/GPIO29

TA/GPIO12

I/O

IDE DIOW

Out / HIGH

In / LOW

Out / HIGH

IDE interface IORDY

IDE interface DIOR

External buffer 2 enable

External buffer 1 enable

Transfer acknowledge

In (requires

pull-up for normal

operation)

48

WAKE_UP/

GPIO21

I/O

Wake-up input

In (requires

pull-up for normal

operation)

49

50

EBUIN2/SCLK_OUT/

GPIO13

I/O

Audio interfaces EBU in 2 /

FlashMedia Clock

In / LOW

EBUIN3/CMD_SDIO2/

GPIO14

Audio interfaces EBU in 3 /

FlashMedia Command interface

In / LOW

51

52

53

54

55

56

PAD VDD

EBUIN1/GPIO36

I/O

Audio interfaces EBU in 1

Audio interfaces EBU out 1

Audio interfaces X-tal trim

Chip select 1/ QSPI Chip Select 3

In / LOW

EBUOUT1/GPIO37

XTRIM/GPIO0

Out / LOW

Out / clock out

Out / HIGH

Out / LOW

CS1/QSPI_CS3/GPIO28

RCK/

QSPI_DIN/QSPI_DOUT/

GPIO26

Subcode RCK interface /

QSPI Data In / Data Out

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

40

Freescale Semiconductor

Pin-Out and Package Information

Table 33. 144 QFP Pin Assignments (continued)

144 QFP

Number

Pin State

After Reset

Name

Type

Description

57

58

59

60

QSPI_CLK/SUBR/

GPIO25

I/O

QSPI clock pin / subcode interface

Out / LOW

QSPI_DOUT/SFSY/

GPIO27

QSPI Data Output / subcode

interface SFSY

QSPI_CS1/EBUOUT2/

GPIO16

QSPI Chip select 1 output /

audio interface EBU output 2

QSPI_CS0/EBUIN4/

GPIO15

QSPI chip select 0 /

audio interface EBUIN 4

61

62

63

64

PAD GND

SCLK1/GPIO20

LRCK1/GPIO19

I/O

Audio interfaces serial clock 1

Audio interfaces word clock 1

In / LOW

Out / LOW

SDATAO1/TOUT0/

GPIO18

Audio interfaces serial data

output 1 / Timer output 0

65

66

67

68

SDATAI1/GPIO17

CFLG/GPIO5

EF/GPIO6

I

Audio interfaces serial data in 1

CFLG input

In / LOW

Out / LOW

I/O

Error flag input

QSPI_CS2/MCLK2/

GPIO24

QSPI Chip Select output 2 /

audio master clock output 2

69

70

71

72

73

74

75

76

77

78

79

SDATAI3/GPIO8

ADIN0/GPI52

ADIN1/GPI53

ADIN2/GPI54

ADVDD

I/O

A

Audio interfaces serial data input 3

AD input 0

In / LOW

In only

A

AD input 1

A

AD input 2

ADGND

ADIN3/GPI55

ADIN4/GPI56

ADIN5/GPI57

ADREF

A

AD input 3

In only

AD input 4

In only

A

AD input 5

In only

A

ADC reference input

In

ADOUT/SCLK4/

GPIO58

I/O

AD output / SCLK4

(for GPI function in low power

applications)

Out / clock output

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

41

Pin-Out and Package Information

144 QFP

Table 33. 144 QFP Pin Assignments (continued)

Pin State

After Reset

Name

Type

Description

Number

80

LRCK3/GPIO43/

AUDIO_CLOCK

I/O

Audio interface LRCK3 /

Audio master clock input

In / LOW

81

82

SCLK3/GPIO35

I/O

Audio interface SCLK3

In / LOW

SCL0/SDATA1_BS1/

GPIO41

I2C0 clock line / FlashMedia

Data interface

Out / LOW

83

84

SDA0/SDATA3/

GPIO42

I/O

I2C0 data / FlashMedia

data interface

Hi-Z

DDATA0/CTS1/

SDATA0_SDIO1/

GPIO1

Debug / UART1 CTS / FlashMedia

data interface

Out / HIGH

85

DDATA1/RTS1/

SDATA2_BS2/GPIO2

I/O

Debug / UART1 RTS / FlashMedia

data interface

Out / HIGH

86

87

88

DDATA2/CTS0/GPIO3

DDATA3/RTS0/GPIO4

SCL1/TXD1/GPIO10

I/O

Debug / UART0 CTS

Debug / UART0 RTS

Out / HIGH

Out / LOW

I2C1 clock line / second

UART transmit data output

89

90

91

CORE VDD

CORE GND

SDA1/RXD1/GPIO44

I/O

I2C1 data line / second UART

receive data input

Hi-Z

92

93

94

95

PAD VDD

TXD0/GPIO45

RXD0/GPIO46

I/O

First UART transmit data output

First UART receive data input

Debug / interrupt monitor output 1

Out / HIGH

In / LOW

PST3/INTMON1/

GPIO47

Out / HIGH

96

PST2/INTMON2/

GPIO48

I/O

Debug / interrupt monitor output 2

Out / HIGH

97

98

PAD GND

PST1/GPIO49

PST0/GPIO50

PSTCLK/GPIO51

TDO/DSO

I/O

O

Debug

Out / HIGH

Out / clock output

BDM

99

Debug

100

101

Debug

JTAG/debug

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

42

Freescale Semiconductor

Pin-Out and Package Information

Table 33. 144 QFP Pin Assignments (continued)

144 QFP

Number

Pin State

After Reset

Name

Type

Description

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

TDI/DSI

TCK

I

JTAG/debug

JTAG

BDM

X

TMS/BKPT

TRST/DSCLK

RSTI

I

JTAG/debug

I

JTAG/Debug

I

Reset

SCLK2/GPIO22

LRCK2/GPIO23

LINOUT

I/O

A

Audio interfaces serial clock 2

Audio interfaces EBU out 1

Linear regulator output

Linear regulator input

Linear regulator ground

In / LOW

In /LOW

X

LININ

X

LINGND

X

SDATAO2/GPIO34

MCLK1/GPIO11

HI-Z

I/O

Audio interfaces serial data output 2 Out / LOW

I/O

Audio master clock output 1

Out / clock output

I

JTAG

X

TEST2

I

Test

X

TEST1

Test

X

TEST0

I

Test

X

SDWE/GPIO38

SDCAS/GPIO39

PAD VDD

I/O

SDRAM write enable

SDRAM CAS

Out / HIGH

SDRAS/GPIO59

SD_CS0/GPIO60

SDLDQM/GPO52

SDUDQM/GPO53

BCLKE/GPIO63

BCLK/GPIO40

DATA31

I/O

O

SDRAM RAS

Out / HIGH

X

SDRAM chip select out 0

SDRAM LDQM

SDRAM UDQM

SDRAM clock enable output

SDRAM clock output

Data

O

I/O

DATA30

Data

X

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

43

Pin-Out and Package Information

144 QFP

Table 33. 144 QFP Pin Assignments (continued)

Pin State

After Reset

Name

Type

Description

Number

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

PAD GND

DATA29

DATA28

DATA27

DATA26

DATA25

PAD-VDD

DATA24

DATA23

DATA22

DATA21

DATA20

PAD GND

DATA19

DATA18

DATA17

I/O

Data

X

I/O

Data

X

I/O

Data

X

6.2 Package

The SCF5250 is assembled in 144-pin QFP package. Thermal characteristics are not available at this time.

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

44

Freescale Semiconductor

THIS PAGE INTENTIONALLY LEFT BLANK

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

45

THIS PAGE INTENTIONALLY LEFT BLANK

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

46

Freescale Semiconductor

THIS PAGE INTENTIONALLY LEFT BLANK

SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1

Freescale Semiconductor

47

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

support@freescale.com

USA/Europe or Locations Not Listed:

Freescale Semiconductor

Technical Information Center, CH370

1300 N. Alma School Road

Chandler, Arizona 85224

+1-800-521-6274 or +1-480-768-2130

support@freescale.com

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH

Technical Information Center

Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English)

+46 8 52200080 (English)

+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

support@freescale.com

Japan:

Freescale Semiconductor Japan Ltd.

Headquarters

ARCO Tower 15F

1-8-1, Shimo-Meguro, Meguro-ku,

Tokyo 153-0064, Japan

0120 191014 or +81 3 5437 9125

support.japan@freescale.com

Information in this document is provided solely to enable system and

software implementers to use Freescale Semiconductor products. There are

no express or implied copyright licenses granted hereunder to design or

fabricate any integrated circuits or integrated circuits based on the

information in this document.

Freescale Semiconductor reserves the right to make changes without further

notice to any products herein. Freescale Semiconductor makes no warranty,

representation or guarantee regarding the suitability of its products for any

particular purpose, nor does Freescale Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or

incidental damages. “Typical” parameters that may be provided in Freescale

Semiconductor data sheets and/or specifications can and do vary in different

applications and actual performance may vary over time. All operating

parameters, including “Typicals”, must be validated for each customer

application by customer’s technical experts. Freescale Semiconductor does

not convey any license under its patent rights nor the rights of others.

Freescale Semiconductor products are not designed, intended, or authorized

for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other

application in which the failure of the Freescale Semiconductor product could

create a situation where personal injury or death may occur. Should Buyer

purchase or use Freescale Semiconductor products for any such unintended

or unauthorized application, Buyer shall indemnify and hold Freescale

Semiconductor and its officers, employees, subsidiaries, affiliates, and

distributors harmless against all claims, costs, damages, and expenses, and

reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized

use, even if such claim alleges that Freescale Semiconductor was negligent

regarding the design or manufacture of the part.

Asia/Pacific:

Freescale Semiconductor Hong Kong Ltd.

Technical Information Center

2 Dai King Street

Tai Po Industrial Estate

Tai Po, N.T., Hong Kong

+800 2666 8080

support.asia@freescale.com

For Literature Requests Only:

Freescale Semiconductor Literature Distribution Center

P.O. Box 5405

Denver, Colorado 80217

1-800-441-2447 or 303-675-2140

Fax: 303-675-2150

LDCForFreescaleSemiconductor@hibbertgroup.com

Freescale™ and the Freescale logo are trademarks of Freescale

Semiconductor, Inc. All other product or service names are the property

reserved.

Document Number: SCF5250EC

Rev. 1.1

04/2005

型号:	SCF5250CAG120
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Transferred
IHS 制造商：	FREESCALE SEMICONDUCTOR INC
零件包装代码：	QFP
包装说明：	LFQFP, QFP144,.87SQ,20
针数：	144
Reach Compliance Code：	unknown
ECCN代码：	3A991.A.2
HTS代码：	8542.31.00.01
风险等级：	5.36
Is Samacsys：	N
其他特性：	ALSO REQUIRES 3.3V SUPPLY
地址总线宽度：	25
位大小：	32
边界扫描：	YES
最大时钟频率：	33.86 MHz
外部数据总线宽度：	32
格式：	FIXED POINT
集成缓存：	YES
JESD-30 代码：	S-PQFP-G144
JESD-609代码：	e3
长度：	20 mm
低功率模式：	YES
湿度敏感等级：	3
端子数量：	144
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP
封装等效代码：	QFP144,.87SQ,20
封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260
电源：	1.2,3.3 V
认证状态：	Not Qualified
座面最大高度：	1.6 mm
速度：	120 MHz
子类别：	Microprocessors
最大供电电压：	1.32 V
最小供电电压：	1.08 V
标称供电电压：	1.2 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	40
宽度：	20 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR
Base Number Matches：	1

电子百科

产品导航

产品型号SCF5250CAG120的概述

产品型号SCF5250CAG120的Datasheet PDF文件预览

SCF5250CAG120相关产品

SCF5250CAG120相关文章

IC37:专业IC行业平台