SI5335A-B10319-GMR全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

Si5335

WEB-CUSTOMIZABLE, ANY-FREQUENCY, ANY-OUTPUT

QUAD CLOCK GENERATOR/BUFFER

Features



Low power MultiSynth™ technology

enables independent, any-frequency

synthesis of four frequencies

Configurable as a clock generator or

clock buffer device

Three independent, user-assignable,

pin-selectable device configurations

Highly-configurable output drivers with

up to four differential outputs, eight

single-ended clock outputs, or a

combination of both



Single supply core with excellent

PSRR: 1.8, 2.5, 3.3 V

Up to five user-assignable pin

functions simplify system design:

SSENB (spread spectrum control),

RESET, Master OEB or OEB per pin,

and Frequency plan select

(FS1, FS0)

Loss of signal alarm

PCIe-compliant spread spectrum

clocking (SSC):



Ordering Information:

See page 41.



Low phase jitter of 0.7 ps RMS

Flexible input reference:

100 MHz

0.5% down spread

External crystal: 25 or 27 MHz

CMOS input: 10 to 200 MHz

SSTL/HSTL input: 10 to 350 MHz

Differential input: 10 to 350 MHz

Independently configurable outputs

support any frequency or format:

LVPECL/LVDS/CML: 1 to 350 MHz

HCSL: 1 to 250 MHz

31.5 kHz modulation rate

Two selectable loop bandwidth

settings: 1.6 MHz or 475 kHz

Easy to customize with web-based

utility

Small size: 4 x 4 mm, 24-QFN

Low power (core):

45 mA (PLL mode)



Pin Assignments



Top View



24

23

22

21

20

19

CMOS: 1 to 200 MHz

12 mA (Buffer mode)

Wide temperature range: –40 to

+85 °C

1

2

3

4

XA/CLKIN

18

17

16

15

CLK1A

SSTL/HSTL: 1 to 350 MHz

Independent output voltage per driver:

1.5, 1.8, 2.5, or 3.3 V



XB/CLKINB

P3

CLK1B

VDDO1

GND

Pad

GND

VDDO2

CLK2A

CLK2B

Applications

5

6

14

13

P5

P6



Ethernet switch/router

PCI Express 3.0/2.1/1.1

PCIe jitter attenuation

DSL jitter attenuation



Processor and FPGA clocking

MSAN/DSLAM/PON

Fibre Channel, SAN

Telecom line cards

7

8

9

10

12

11



Broadcast video/audio timing

1 GbE and 10 GbE

Description

The Si5335 is a highly flexible clock generator capable of synthesizing four

completely non-integer-related frequencies up to 350 MHz. The device has four

banks of outputs with each bank supporting one differential pair or two single-ended

outputs. Using Silicon Laboratories' patented MultiSynth fractional divider

technology, all outputs are guaranteed to have 0 ppm frequency synthesis error

regardless of configuration, enabling the replacement of multiple clock ICs and

crystal oscillators with a single device. The Si5335 supports up to three independent,

pin-selectable device configurations, enabling one device to replace three separate

clock generators or buffer ICs. To ease system design, up to five user-assignable

and pin-selectable control pins are provided, supporting PCIe-compliant spread

spectrum control, master and/or individual output enables, frequency plan selection,

and device reset. Two selectable PLL loop bandwidths support jitter attenuation in

applications, such as PCIe and DSL. Through its flexible ClockBuilder™

(www.silabs.com/ClockBuilder) web configuration utility, factory-customized, pin-

controlled devices are available in two weeks without minimum order quantity

restrictions.

Rev. 1.2 1/13

Si5335

Functional Block Diagram

Osc

VDDO0

CLK0A

CLK0B

PLL Bypass

÷MultiSynth0

PLL Bypass

XA / CLKIN

XB / CLKINB

PLL

OEB0

OEB1

VDDO1

CLK1A

CLKIN

÷MultiSynth1

PLL Bypass

÷MultiSynth2

PLL Bypass

CLK1B

Programmable

Pin Function

Options:

VDDO2

CLK2A

P1

P2

P3

P5

P6

CLK2B

OEB0/1/2/3

OEB_all

SSENB

Control

OEB2

OEB3

VDDO3

CLK3A

FS[1:0]

RESET

÷MultiSynth3

CLK3B

LOS

2

Rev. 1.2

Si5335

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical PCIe System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.2. MultiSynth Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.3. ClockBuilder Web-Customization Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.4. Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.5. Input and Output Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.6. Multi-Function Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.7. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.8. Frequency Select/Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.9. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

3.10. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

4. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

5. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

6. Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

7. Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

8. Loop Bandwidth Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

9. Applications of the Si5335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

9.1. Free-Running Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

9.2. Synchronous Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

9.3. Configurable Universal Buffer and Level Translator . . . . . . . . . . . . . . . . . . . . . . . . .37

10. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

12. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

13. Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

14. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

14.1. Si5335 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

14.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Rev. 1.2

3

Si5335

1. Electrical Specifications

Table 1. Recommended Operating Conditions

(V_DD= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

–40

2.97

2.25

1.71

1.4

Typ

25

Max

85

Unit

°C

V

Ambient Temperature

T

A

3.3

2.5

1.8

—

3.63

2.75

1.98

3.63

V

Core Supply Voltage

DD

V

Output Buffer Supply

Voltage

V

DDOn

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

Table 2. DC Characteristics

(V_DD= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Symbol

Test Condition

Min

Typ

Max

Unit

Parameter

100 MHz on all outputs,

25 MHz refclk,

clock generator mode

Core Supply Current

(Clock Generator Mode)

I

—

45

60

mA

DDCG

Core Supply Current

(Buffer Mode)

I

50 MHz refclk

—

12

—

mA

DDB

LVPECL, 350 MHz

CML, 350 MHz

—

12

—

30

—

8

mA

LVDS, 350 MHz

HCSL, 250 MHz

2 pF load

—

6

20

19

9

mA

SSTL, 350 MHz

CMOS, 50 MHz

1

Output Buffer Supply Current

I

DDOx

15 pF load

1,2

CMOS, 200 MHz

—

13

10

18

14

mA

3.3 V VDD0

1,2

CMOS, 200 MHz

2.5 V

1,2

CMOS, 200 MHz

—

7

10

19

mA

1.8 V

HSTL, 350 MHz

—

Notes:

1. Single CMOS driver active.

2. Measured into a 5” 50  trace with 2 pF load.

4

Rev. 1.2

Si5335

Table 3. Performance Characteristics

(V_DD= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

PLL Acquisition Time

t

1.6 MHz loop bandwidth

—

25

—

ms

ACQ

475 kHz or 1.6 MHz loop

bandwidth

PLL Tracking Range

PLL Loop Bandwidth

f

5000 20000

ppm

TRACK

f

High bandwidth option

Low bandwidth option

—

0

1.6

475

0

—

1

MHz

kHz

ppb

BW1

BW2

MultiSynth Frequency

Synthesis Resolution

f

Output frequency < Fvco/8

RES

CLKIN Loss of Signal Detect

Time

t

—

2.6

0.2

5

1

µs

LOS

CLKIN Loss of Signal Release

Time

t

0.01

LOSRLS

POR to Output Clock Valid

t

—

2

4

ms

ns

RDY

Input-to-Output Propagation

Delay

t

Buffer Mode

(PLL Bypass)

2.5

PROP

Reset Minimum Pulse Width

t

—

200

100

–0.5

ns

ps

%

RESET

1

F

> 5 MHz

Output-Output Skew

t

DSKEW

OUT

Spread Spectrum PP

SS

F

= 100 MHz

–0.45

DEV

OUT

2

Frequency Deviation

Spread Spectrum Modulation

SS

F

30

31.5

33

kHz

DEV

3

Rate

Notes:

1. Outputs at integer-related frequencies and using the same driver format.

2. Default value is 0.5% down spread.

3. Default value is 31.5 kHz for PCI compliance.

Rev. 1.2

5

Si5335

Table 4. Input and Output Clock Characteristics

(V_DD= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

1

Input Clock (AC Coupled Differential Input Clocks on Pins 1 and 2)

2

Frequency

f

LVDS, LVPECL,

HCSL, CML

10

0.4

—

350

2.4

1.0

60

IN

MHz

Differential Voltage

Swing

V

350 MHz input

PP

V

PP

3

Rise/Fall Time

t /t

20%–80%

ns

R F

DC

(PLL

< 1 ns t /t

40

%

R F

mode)

3

Duty Cycle

DC

(PLL

bypass

mode)

< 1 ns t /t

45

—

55

R F

1

Input Impedance

R

10

—

k

IN

Input Capacitance

C

3.5

pF

IN

Input Clock (AC-Coupled Single-Ended Input Clock on Pin 1)

2

Frequency

f

CMOS, HSTL, SSTL

200 MHz

10

—

200

1.2

MHz

Vpp

IN

CMOS Input Voltage

Swing

V

0.8

I

CMOS Rise/Fall Time t /t

10%–90%

20%–80%

—

4

ns

R F

CMOS Rise/Fall Time t /t

2.3

R F

HSTL/SSTL Input

Voltage

V

I(HSTL/

200 MHz

0.4

—

1.2

1.4

V

PP

SSTL)

HSTL/SSTL Rise/Fall

Time

t /t

10%–90%

ns

R F

Notes:

1. Use an external 100  resistor to provide load termination for a differential clock. See "3.4.2. Differential Input Clocks"

on page 19.

2. Minimum input frequency in clock buffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer

mode, but loss-of-signal (LOS) status is not functional.

3. Applies to differential inputs. For best jitter performance, keep the midpoint peak-to-peak differential input slew rate on

pins 1 and 2 faster than 0.3 V/ns.

4. CML output format requires ac-coupling of the differential outputs to a differential 100  load at the receiver. See

"3.10.6. CML Outputs" on page 31.

5. Includes effect of internal series 22  resistor.

6

Rev. 1.2

Si5335

Table 4. Input and Output Clock Characteristics (Continued)

(V_DD= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

< 1 ns t /t

Min

Typ

Max

Unit

DC

(PLL

40

—

60

%

R F

mode)

Duty Cycle

DC

(PLL

bypass

mode)

< 1 ns t /t

45

—

55

—

%

R F

Input Capacitance

C

3.5

pF

IN

Output Clocks (Differential)

LVPECL, LVDS, CML

HCSL

1

—

350

250

MHz

Frequency

f

OUT

V

–

DDO

V

common mode

—

V

OC

1.45 V

LVPECL

Output Voltage

peak-to-peak single-

ended swing

V

0.55

1.125

0.25

0.8

0.96

1.275

0.45

0.95

0.45

0.400

0.85

—

V

PP

SEPP

V

common mode

1.2

V

OC

LVDS Output Voltage

(2.5/3.3 V)

peak-to-peak single-

ended swing

0.35

V

PP

SEPP

V

common mode

0.875

0.35

V

OC

LVDS Output

Voltage (1.8 V)

peak-to-peak single-

ended swing

0.25

0.35

0.575

—

V

PP

SEPP

V

common mode

0.375

0.725

See Note

0.860

V

OC

HCSL Output Voltage

CML Output Voltage

peak-to-peak single-

ended swing

V

SEPP

PP

4

V

Common Mode

V

OC

Peak-to-Peak Single-

ended Swing

0.67

1.07

V

PP

SEPP

20% to 80%

LVPECL, LVDS,

HCSL, CML

Rise/Fall Time

t /t

—

450

ps

R F

Notes:

1. Use an external 100  resistor to provide load termination for a differential clock. See "3.4.2. Differential Input Clocks"

on page 19.

2. Minimum input frequency in clock buffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer

mode, but loss-of-signal (LOS) status is not functional.

3. Applies to differential inputs. For best jitter performance, keep the midpoint peak-to-peak differential input slew rate on

pins 1 and 2 faster than 0.3 V/ns.

4. CML output format requires ac-coupling of the differential outputs to a differential 100  load at the receiver. See

"3.10.6. CML Outputs" on page 31.

5. Includes effect of internal series 22  resistor.

Rev. 1.2

7

Si5335

Table 4. Input and Output Clock Characteristics (Continued)

(V_DD= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Duty Cycle

Symbol

Test Condition

Min

Typ

Max

Unit

LVPECL, LVDS,

HCSL, CML

DC

45

—

55

%

Output Clocks (Single-Ended)

CMOS

1

—

200

350

MHz

Frequency

f

OUT

SSTL, HSTL

CMOS 20%–80%

Rise/Fall Time

t /t

2 pF load

—

0.45

—

0.85

2.0

ns

R F

CMOS 20%–80%

Rise/Fall Time

t /t

15 pF load

—

R F

V

4 mA load

VDDO – 0.3

—

V

OH

CMOS

Output Voltage

5

V

0.3

—

OL

CMOS

Output Resistance

—

50



5

HSTL, SSTL

20%–80%

t /t

See Figure 16.

0.35

—

ns

R F

Rise/Fall Time

V

0.5xVDDO+0.3

—

0.5xVDDO –0.3

—

V

OH

HSTL Output Voltage

SSTL Output Voltage

VDDO = 1.4 to 1.6 V

V

OL

V

SSTL-3

VDDOx = 2.97 to

3.63 V

0.45xVDDO+0.41

OH

V

—

0.45xVDDO–0.41

V

OL

V

0.5xVDDO+0.41

—

V

OH

SSTL-2 VDDOx =

2.25 to 2.75 V

V

0.5xVDDO–0.41

OL

V

SSTL-18

VDDOx = 1.71 to

1.98 V

0.5xVDDO+0.34

OH

V

—

0.5xVDDO–0.34

V

OL

HSTL, SSTL

Output Resistance

—

45

50

—

55



Duty Cycle

DC

%

Notes:

1. Use an external 100  resistor to provide load termination for a differential clock. See "3.4.2. Differential Input Clocks"

on page 19.

2. Minimum input frequency in clock buffer mode (PLL bypass) is 5 MHz. Operation to 1 MHz is also supported in buffer

mode, but loss-of-signal (LOS) status is not functional.

3. Applies to differential inputs. For best jitter performance, keep the midpoint peak-to-peak differential input slew rate on

pins 1 and 2 faster than 0.3 V/ns.

4. CML output format requires ac-coupling of the differential outputs to a differential 100  load at the receiver. See

"3.10.6. CML Outputs" on page 31.

5. Includes effect of internal series 22  resistor.

8

Rev. 1.2

Si5335

Table 5. Control Pins*

(V_DD= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Input Control Pins (P1, P2, P3, P5*, P6*)

Pins P1, P2, P3

Pins P5 and P6

Pins P1, P2, P3

Pins P5* and P6*

–0.1

—

20

0.3 x V

0.3

V

DD

V

Input Voltage Low

Input Voltage High

IL

0.7 x V

0.85

—

3.73

1.2

V

DD

IH

V

C

4

pF

k

Input Capacitance

IN

R

—

Input Resistance

IN

Output Control Pins (LOS, Pin 8)

V

I

= 3 mA

0

—

0.4

10

V

Output Voltage Low

OL

SINK

t /t

C < 10 pf, pull up  1 k

—

ns

Rise/Fall Time 20–80%

R F

L

*Note: For more information, see "3.6.1. P5 and P6 Input Control" on page 24.

Table 6. Crystal Specifications for 25 MHz

Parameter

Symbol

Min

Typ

Max

Unit

Crystal Frequency

f

—

25

18

—

MHz

pF

XTAL

Load Capacitance (on-chip differential)

Crystal Output Capacitance

Equivalent Series Resistance

Crystal Max Drive Level

c

—

5

L

c

—

pF

O

r

—

100

—



ESR

d

100

µW

L

Table 7. Crystal Specifications for 27 MHz

Parameter

Symbol

Min

Typ

Max

Unit

Crystal Frequency

f

—

27

—

MHz

XTAL

Load Capacitance (on-chip differential)

Crystal Output Capacitance

Equivalent Series Resistance

Crystal Max Drive Level

c

—

18

—

5

pF



L

c

O

r

—

75

—

ESR

d

100

µW

L

Rev. 1.2

9

Si5335

Table 8. Jitter Specifications, Clock Generator Mode (Loop Bandwidth = 1.6 MHz)^1,2,3

(V_DD= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

GbE Random Jitter

(12 kHz–20 MHz)

CLKIN = 25 MHz

All CLKn at 125 MHz

J

—

0.7

1

ps RMS

GbE

4

5

GbE Random Jitter

(1.875–20 MHz)

CLKIN = 25 MHz

All CLKn at 125 MHz

R

—

0.38

0.7

0.79

1

ps RMS

JGbE

CLKIN = 19.44 MHz

All CLKn at

OC-12 Random Jitter

(12 kHz–5 MHz)

J

OC12

5

155.52 MHz

PCI Express 1.1 Common

Clocked (with spread

spectrum)

6

Total Jitter

—

20.1

33.6

ps pk-pk

6

RMS Jitter , 10 kHz to

1.5 MHz

—

0.15

0.58

1.47

0.75

ps RMS

PCI Express 2.1 Common

Clocked (no spread spec-

trum)

6

RMS Jitter , 1.5 MHz to

50 MHz

PCI Express 3.0 Common

Clocked (no spread spec-

trum)

6

RMS Jitter

—

0.15

10

0.45

30

ps RMS

ps pk-pk

7

J

Period Jitter

N = 10,000 cycles

PER

N = 10,000 cycles

Output MultiSynth

operated in integer or

8

J

—

9

29

ps pk

Cycle-Cycle Jitter

CC

7

fractional mode

Output and feedback

MultiSynth in integer or

Random Jitter

(12 kHz–20 MHz)

R

0.7

1.5

ps RMS

J

7

fractional mode

Notes:

1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and

are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.

2. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there

is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration

implements any single-ended output and any output is required to have jitter less than 2 ps rms, contact Silicon Labs

for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS

outputs have little to no effect upon jitter.

3. For best jitter performance, keep the single-ended clock input slew rates at pins 1 and 2 greater that 1.0 V/ns and the

differential clock input slew rates greater than 0.3 V/ns.

4. D_Jfor PCI and GbE is < 5 ps pp

5. Output MultiSynth in Integer mode.

6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.

See AN562 for details. Jitter is mesured with the Intel Clock Jitter Tool, Ver.1.6.4.

7. For any output frequency > 10 MHz.

8. Measured in accordance with JEDEC standard 65.

9. Rj is multiplied by 14; estimate the pp jitter from Rj over 2¹²rising edges.

10

Rev. 1.2

Si5335

Table 8. Jitter Specifications, Clock Generator Mode (Loop Bandwidth = 1.6 MHz)^1,2,3(Continued)

(V_DD= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output MultiSynth

operated in fractional

—

3

15

ps pk-pk

7

mode

D

Deterministic Jitter

J

Output MultiSynth

operated in integer

—

2

10

ps pk-pk

7

mode

Output MultiSynth

—

13

12

36

20

ps pk-pk

operated in fractional

7

mode

T = D +14xR

J

(See Note )

Total Jitter

(12 kHz–20 MHz)

J

9

Output MultiSynth

operated in integer

7

mode

Notes:

1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and

are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.

2. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there

is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration

implements any single-ended output and any output is required to have jitter less than 2 ps rms, contact Silicon Labs

for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS

outputs have little to no effect upon jitter.

3. For best jitter performance, keep the single-ended clock input slew rates at pins 1 and 2 greater that 1.0 V/ns and the

differential clock input slew rates greater than 0.3 V/ns.

4. D_Jfor PCI and GbE is < 5 ps pp

5. Output MultiSynth in Integer mode.

6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.

See AN562 for details. Jitter is mesured with the Intel Clock Jitter Tool, Ver.1.6.4.

7. For any output frequency > 10 MHz.

8. Measured in accordance with JEDEC standard 65.

9. Rj is multiplied by 14; estimate the pp jitter from Rj over 2¹²rising edges.

Rev. 1.2

11

Si5335

Table 9. Jitter Specifications, Clock Generator Mode (Loop Bandwidth = 475 kHz)^1,2

(V_DD= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

CLKIN = 70.656 MHz

All CLKn at

70.656 MHz

DSL Random Jitter

(10 kHz–400 kHz)

R

—

0.8

2

ps RMS

JDSL1

4

CLKIN = 70.656 MHz

All CLKn at

70.656 MHz

DSL Random Jitter

(100 kHz–10 MHz)

R

—

0.9

1.95

20

2

ps RMS

ps pk-pk

JDSL2

4

CLKIN = 70.656 MHz

All CLKn at

DSL Random Jitter

(10 Hz–30 MHz)

R

2.2

34

JDSL3

4

70.656 MHz

PCI Express 1.1

Common Clocked

(with spread spectrum)

5

Total Jitter

5

RMS Jitter , 10 kHz to

—

0.3

0.5

1.0

ps RMS

PCI Express 2.1

Common Clocked

(no spread spectrum)

1.5 MHz

5

RMS Jitter , 1.5 MHz to

50 MHz

PCI Express 3.0

Common Clocked

(no spread spectrum)

5

RMS Jitter

—

0.15

10

0.45

30

ps RMS

ps pk-pk

6

J

Period Jitter

N = 10,000 cycles

PER

N = 10,000 cycles

Output MultiSynth

operated in integer or

7

J

—

9

1

29

ps pk

Cycle-Cycle Jitter

CC

6

fractional mode

Output and feedback

MultiSynth in integer or

Random Jitter

(12 kHz–20 MHz)

R

2.5

ps RMS

J

6

fractional mode

Notes:

1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and

are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.

2. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there

is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration

implements any single-ended output and any output is required to have jitter less than 2 ps rms, contact Silicon Labs

for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS

outputs have little to no effect upon jitter.

3. D_Jfor PCI and GbE is < 5 ps pp

4. Output MultiSynth in Integer mode.

5. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.

See AN562 for details. Jitter is mesured with the Intel Clock Jitter Tool, Ver.1.6.4.

6. For any output frequency > 5 MHz.

7. Measured in accordance with JEDEC standard 65.

8. Rj is multiplied by 14; estimate the pp jitter from Rj over 2¹²rising edges.

12

Rev. 1.2

Si5335

Table 9. Jitter Specifications, Clock Generator Mode (Loop Bandwidth = 475 kHz)^1,2(Continued)

(V_DD= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output MultiSynth

—

3

15

ps pk-pk

operated in fractional

6

mode

D

Deterministic Jitter

J

Output MultiSynth

operated in integer

—

2

10

ps pk-pk

6

mode

Output MultiSynth

—

13

15

36

30

ps pk-pk

operated in fractional

6

mode

T = D +14xR

J

(See Note )

Total Jitter

(12 kHz–20 MHz)

J

8

Output MultiSynth

operated in integer

6

mode

Notes:

1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and

are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.

2. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there

is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration

implements any single-ended output and any output is required to have jitter less than 2 ps rms, contact Silicon Labs

for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS

outputs have little to no effect upon jitter.

3. D_Jfor PCI and GbE is < 5 ps pp

4. Output MultiSynth in Integer mode.

5. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.

See AN562 for details. Jitter is mesured with the Intel Clock Jitter Tool, Ver.1.6.4.

6. For any output frequency > 5 MHz.

7. Measured in accordance with JEDEC standard 65.

8. Rj is multiplied by 14; estimate the pp jitter from Rj over 2¹²rising edges.

Table 10. itter Specifications, Clock Buffer Mode (PLL Bypass)*

(V_DD= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T_A= –40 to 85°C)

Symbol

Test Condition

Min

Typ

Max

Unit

Parameter

0.7 V pk-pk differential input

clock at 350 MHz with

70 ps rise/fall time

Additive Phase Jitter

(12 kHz–20 MHz)

—

0.165

—

ps RMS

t

RPHASE

0.7 V pk-pk differential input

clock at 350 MHz with

70 ps rise/fall time

Additive Phase Jitter

(50 kHz–80 MHz)

—

0.225

—

ps RMS

t

RPHASEWB

*Note: All outputs are in Clock Buffer mode (PLL Bypass).

Rev. 1.2

13

Si5335

Table 11. Typical Phase Noise Performance

Offset

Loop

25 MHz XTAL

27 MHz Ref In 19.44 MHz Ref In 100 MHz Ref In

Units

Frequency Bandwidth to 156.25 MHz to 148.3517 MHz to 155.52 MHz

to 100 MHz

100 Hz

1 kHz

1.6 MHz

475 kHz

1.6 MHz

475 kHz

1.6 MHz

475 kHz

1.6 MHz

475 kHz

1.6 MHz

475 kHz

1.6 MHz

475 kHz

–90

N/A*

–120

N/A*

–126

N/A*

–132

N/A*

–132

N/A*

–145

N/A*

–87

–110

–91

–115

dBc/Hz

–91

–113

–117

–112

–123

–124

–130

–122

–132

–133

–145

–152

–116

–111

–123

–122

–128

–121

–128

–131

–145

–153

–122

–128

–127

–136

–124

–136

–135

–152

10 kHz

100 kHz

1 MHz

10 MHz

*Note: XTAL input mode does not support the 475 kHz loop bandwidth setting.

Table 12. Thermal Characteristics

Parameter

Symbol

Test Condition

Value

Unit

Thermal Resistance

Junction to Ambient



Still Air

37

°C/W

JA

Thermal Resistance

Junction to Case



Still Air

25

°C/W

JC

14

Rev. 1.2

Si5335

Table 13. Absolute Maximum Ratings¹

Parameter

DC Supply Voltage

Input Voltage

Symbol

Test Condition

Value

Unit

V

–0.5 to 3.8

–0.5 to 1.3

DD

V

Pins: XA/CLKIN,

V

IN

XB/CLKINB, P5, P6

Pins: P1, P2, P3

–0.5 to 3.8

–55 to 150

2.5

V

Storage Temperature Range

ESD Tolerance

T

°C

kV

STG

HBM

(100 pF, 1.5 k)

ESD Tolerance

CDM

MM

550

175

V

ESD Tolerance

Latch-up Tolerance

Junction Temperature

JESD78 Compliant

T

150

260

°C

J

2,3

Peak Soldering Reflow Temperature

Notes:

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

2. Refer to JEDEC J-STD-020 standard for more information.

3. 24-QFN package is RoHS-compliant. Moisture sensitivity level is MSL3.

Rev. 1.2

15

Si5335

2. Typical PCIe System Diagram

Peripheral

Board

Main

Board

PCIe

Core

PCIe

Link

FPGA

B

FPGA

PCIe

Link

A

PCIe

Core

PCIe

Switch

125MHz

LVDS

FPGA

C

PCIe

Core

PCIe

Link

Si5335

Clock

Generator

100MHz HCSL

25MHz LVPECL

Peripheral

Board

Figure 1. PCI Express Switching Application Example

Figure 1 shows the Si5335 in a PCI Express application using the common clock topology. The Si5335 provides

reference clocks to the three FPGAs, each of which requires a different clock signaling format (LVDS, LVPECL),

I/O voltage (1.8, 2.5, 3.3 V), or frequency (25, 100, 125 MHz). In addition, the Si5335 provides a PCIe compliant,

100 MHz HCSL reference clock to the PCIe switch.

16

Rev. 1.2

Si5335

3. Functional Description

Osc

VDDO0

CLK0A

CLK0B

PLL Bypass

÷MultiSynth0

PLL Bypass

XA / CLKIN

XB / CLKINB

PLL

OEB0

VDDO1

CLK1A

CLKIN

÷MultiSynth1

PLL Bypass

÷MultiSynth2

PLL Bypass

CLK1B

OEB1

OEB2

OEB3

Programmable

Pin Function

Options:

VDDO2

CLK2A

P1

P2

CLK2B

P3

P5

OEB0/1/2/3

OEB_all

SSENB

FS[1:0]

RESET

Control

P6

VDDO3

CLK3A

÷MultiSynth3

CLK3B

LOS

Figure 2. Si5335 Functional Block Diagram

3.1. Overview

The Si5335 is a high-performance, low-jitter clock generator or buffer capable of synthesizing four independent

user-programmable clock frequencies up to 350 MHz. The device supports free-run operation using an external 25

or 27 MHz crystal, or it can lock to an external clock for generating synchronous clocks. The output drivers support

four differential clocks or eight single-ended clocks or a combination of both. The output drivers are configurable to

support common signal formats, such as LVPECL, LVDS, HCSL, CML, CMOS, HSTL, and SSTL. Separate output

supply pins allow supply voltages of 3.3, 2.5, 1.8, and 1.5 V to support the multi-format output driver. The core

voltage supply accepts 3.3, 2.5, or 1.8 V and is independent from the output supplies. Using its two-stage

synthesis architecture and patented high-resolution MultiSynth technology, the Si5335 can generate four

independent frequencies from a single input frequency. In addition to clock generation, the inputs can bypass the

synthesis stage enabling the Si5335 to be used as a high-performance clock buffer.

Spread spectrum* is available on each of the clock outputs for EMI-sensitive applications, such as PCI Express.

The device includes an interrupt pin that monitors for both loss of PLL lock (LOL) and loss of input signal (LOS)

conditions while configured in clock generator mode. In clock generator mode, the LOS pin is asserted whenever

LOL or LOS is true. In clock buffer mode (i.e., when the PLL is bypassed), the LOS pin is asserted whenever the

input clock is lost. The LOL condition does not apply in clock buffer mode.

*Note: See " Document Change List" on page 45 for more information.

Rev. 1.2

17

Si5335

3.2. MultiSynth Technology

Next-generation timing architectures require a wide range of frequencies which are often non-integer related.

Traditional clock architectures address this by using a combination of single PLL ICs, 4-PLL ICs and discrete XOs,

often at the expense of BOM complexity and power. The Si5335 uses patented MultiSynth technology to

dramatically simplify timing architectures by integrating the frequency synthesis capability of 4 phase-locked loops

(PLLs) in a single device, greatly minimizing size and power requirements versus traditional solutions. Based on a

fractional-N PLL, the heart of the architecture is a low phase noise, high-frequency VCO. The VCO supplies a high

frequency output clock to the MultiSynth block on each of the four independent output paths. Each MultiSynth

operates as a high-speed fractional divider with Silicon Laboratories' proprietary phase error correction to divide

down the VCO clock to the required output frequency with very low jitter.

The first stage of the MultiSynth architecture is a fractional-N divider which switches seamlessly between the two

closest integer divider values to produce the exact output clock frequency with 0 ppm error. To eliminate phase

error generated by this process, MultiSynth calculates the relative phase difference between the clock produced by

the fractional-N divider and the desired output clock and dynamically adjusts the phase to match the ideal clock

waveform. This novel approach makes it possible to generate any output clock frequency without sacrificing jitter

performance. Based on this architecture, the output of each MultiSynth can produce any frequency from 1 to

350 MHz.

MultiSynth

Fractional-N

Divider

Phase

Adjust

f_VCO

f_OUT

Phase Error

Calculator

Divider Select

(DIV1, DIV2)

Figure 3. Silicon Labs' MultiSynth Technology

3.3. ClockBuilder Web-Customization Utility

ClockBuilder is a web-based utility available at www.silabs.com/ClockBuilder that allows hardware designers to

tailor the Si5335’s flexible clock architecture to meet any application-specific requirements and order custom clock

samples. Through a simple point-and-click interface, users can specify any combination of input frequency and

output frequencies and generate a custom part number for each application-specific configuration. There are no

minimum order quantity restrictions.

ClockBuilder enables mass customization of clock generators. This allows a broader range of applications to take

advantage of using application-specific pin controlled clocks, simplifying design while eliminating the firmware

2

development required by traditional I C-programmable clock generators.

Based on Silicon Labs’ patented MultiSynth technology, the device PLL output frequency is constant and all clock

output frequencies are synthesized by the four MultiSynth fractional dividers. All PLL parameters, including divider

settings, VCO frequency, loop bandwidth, charge pump current, and phase margin are internally set by the device

during the configuration process. This ensures optimized jitter performance and loop stability while simplifying

design.

18

Rev. 1.2

Si5335

3.4. Input Configuration

The Si5335 input can be driven from either an external crystal or a reference clock. Reference selection is made

when the device configuration is specified using the ClockBuilder™ web-based utility available at www.silabs.com/

ClockBuilder.

3.4.1. Crystal Input

If the crystal input option is used, the Si5335 operates as a free-running clock generator. In this mode of operation

the device requires a low-cost 25 or 27 MHz fundamental mode crystal connected across XA and XB as shown in

Figure 4. Given the Si5335’s frequency flexibility, the same 25 or 27 MHz crystal can be reused to generate any

combination of output frequencies. Custom frequency crystals are not required. The Si5335 integrates the crystal

load capacitors on-chip to reduce external component count. The crystal should be placed very close to the device

to minimize stray capacitance. To ensure stable oscillation, the recommended crystal specifications provided in

Tables 6 and 7 must be followed. See AN360 for additional details regarding crystal recommendations.

Si5335

XA/CLKIN

XTAL

XB/CLKINB

Figure 4. Connecting an XTAL to the Si5335

3.4.2. Differential Input Clocks

The multi-format differential clock inputs of the Si5335 will interface with today’s most common differential signals,

such as LVDS, LVPECL, CML, and HCSL. The differential inputs are internally self-biased and must be ac-coupled

externally with a 0.1 µF capacitor. The receiver will accept a signal with a voltage swing between 400 mV and

2.4 V differential. Each half of the differential signal must not exceed 1.2 V at the input to the Si5335 or else

PP

the 1.3 V dc voltage limit may be exceeded.

3.4.2.1. LVDS Inputs

When interfacing the Si5335 device to an LVDS signal, a 100  termination is required at the input along with the

required dc blocking capacitors as shown in Figure 5.

Must be ac coupled

Keep termination close to

input pin of the Si5335

0.1 uF

Si5335

50

Pin 1

100

Pin 2

50

LVDS

0.1 uF

Figure 5. LVDS Input Signal

3.4.2.2. LVPECL Input Clocks

Recommended configurations for interfacing an LVPECL input signal to the Si5335 are shown in Figure 6. Typical

values for the bias resistors (Rb) range between 120and 200  depending on the LVPECL driver. The 100 

resistor provides line termination. Because the receiver is internally self-biased, no additional external bias is

required.

Another solution is to terminate the LVPECL driver with a Thevenin configuration as shown in Figure 6b.The

Rev. 1.2

19

Si5335

values for R and R are calculated to provide a 50 termination to V -2V. Given this, the recommended resistor

1

2

DD

values are R = 127 and R = 82.5  for V = 3.3 V, and R = 250 andR = 62.5 for V = 2.5 V.

1

2

DD

1

2

DD

Keep termination close to

input pin of the Si5335

3.3 V, 2.5 V

0.1 uF

Si5335

50

Pin 1

Pin 2

100

LVPECL

0.1 uF

Rb

Must be ac coupled

LVPECL Input Signal with Source Biasing Option

Keep termination close to

input pin of the Si5335

V_DDV_DD

Must be ac coupled

R₁

V_DD

= 3.3 V, 2.5 V

Si5335

0.1 uF

50

Pin 1

Pin 2

LVPECL

R₂

V_T= V_DD– 2 V

R₁// R₂= 50 Ohm

LVPECL Input Signal with Load Biasing Option

Figure 6. Recommended Options for Interfacing to an LVPECL Input Signal

Since the differential receiver of the Si5335 is internally self biased, an LVPECL signal may not be dc-coupled to

the device. Figure 7 shows some common LVPECL connections that should not be used because of the dc levels

they present at the receiver’s input.

V_DDV_DD

DC Coupled with

Thevenin Termination

AC Coupled with

Thevenin Re-Biasing

R₁

50

LVPECL

R₂

Rb

R₂

Rb

Not Recommended

Figure 7. Common LVPECL Connections that May be Destructive to the Si5335 Input

20

Rev. 1.2

Si5335

3.4.2.3. CML Input Clocks

CML signals may be applied to the differential inputs of the Si5335. Since the Si5335 differential inputs are

internally self-biased, a CML signal may not be dc-coupled to the device.

The recommended configurations for interfacing a CML input signal to the Si5335 are shown in Figure 8. The

100  resistor provides line termination, and, since the receiver is internally-biased, no additional external biasing

components are required.

Keep termination close to

input pin of the Si5335

0.1 uF

Si5335

50

Pin 1

100

Pin 2

CML

50

0.1 uF

Must be ac coupled

Figure 8. CML Input Signal

3.4.2.4. HCSL Input Clocks

A typical HCSL driver has an open source output, which requires an external series resistor and a resistor to

ground. The values of these resistors depend on the driver but are typically equal to 33  (Rs) and 50  (Rt). Note

that the HCSL driver in the Si5335 requires neither Rs nor Rt resistors. Other than two ac-coupling capacitors, no

additional external components are necessary when interfacing an HCSL signal to the Si5335.

Must be ac coupled

3.3V, 2.5V, 1.8V

0.1 uF

Rs

Si5335

50

Pin 1

Pin 2

Rs

50

HCSL

0.1 uF

Rt

Figure 9. HCSL Input Signal to Si5335

Rev. 1.2

21

Si5335

3.4.3. Single-Ended CMOS Input Clocks

For synchronous timing applications, the Si5335 can lock to a 10 to 200 MHz CMOS reference clock. A typical

interface circuit is shown in Figure 10. A series termination resistor may be required if the CMOS driver impedance

does not match the trace impedance.

Keep R_seand R_shclose to

the receiver

0.1 uF

R_se

Si5335

CMOS Input Signal

1.8 V CMOS

50

Pin 1

Pin 2

R_sh

3.3 V CMOS

R_se= 249 

R_sh= 464 

R_se= 499 

R_sh= 274 

2.5 V CMOS

0.1 uF

R_se= 402 

R_sh= 357 

Figure 10. Interfacing CMOS Reference Clocks to the Si5335

3.4.4. Single-Ended SSTL and HSTL Input Clocks

HSTL and SSTL single-ended inputs can be input to the differential inputs, pins 1 and 2, of the Si5335 with the

circuit shown in Figure 11.

Some drivers may require a series 25  resistor. If the SSTL/HSTL input is being driven by another Si5335 device,

the 25  series resistor is not required as this is integrated on-chip. The maximum recommended input frequency

in this case is 350 MHz.

Keep termination close to

input pin of the Si5335

V_TT

50

0.1 uF

Si5335

Pin 1

50

0.4 to 1.2 V pk-pk

Differential

Input

V_DD

Pin 2

R₁

R₂

0.1 uF

V_TT

0.1 uF

SSTL_2, SSTL_18, HSTL

R₁= 2.43 k

R₂= 2 k

SSTL_3

R₁= 2.43 k

R₂= 2 k

Figure 11. Single-Ended SSTL/HSTL Input Clocks to the Si5335

22

Rev. 1.2

Si5335

3.4.5. Applying a Single-Ended Clock to the Differential Input Clock Pins

It is possible to interface any single-ended clock signal to the differential input pins (XA/CLKIN, XB/CLKINB). The

recommended interface for a signal that requires a 50  load is shown in Figure 12. On these inputs, it is important

that the signal level be less than 1.2 V SE and greater than 0.4 V SE. The maximum recommended input

PP

frequency in this case is 350 MHz.

Keep termination close to

input pin of the Si5335

0.1 uF

Si5335

Pin 1

50

0.4 to 1.2V pk-pk

50

Pin 2

0.1 uF

Figure 12. Single-Ended Input Signal with 50  Termination

3.5. Input and Output Frequency Configuration

The Si5335 utilizes a single PLL-based architecture, four independent MultiSynth fractional output dividers, and a

MultiSynth fractional feedback divider such that a single device provides the clock generation capability of 4

independent PLLs. Unlike competitive multi-PLL solutions, the Si5335 can generate four unique non-integer

related output frequencies with 0 ppm frequency error for any combination of output frequencies. In addition, any

combination of output frequencies can be generated from a single reference frequency without having to change

the crystal or reference clock frequency between frequency configurations.

The Si5335 frequency configuration is set when the device configuration is specified using the ClockBuilder web-

based utility available at www.silabs.com/ClockBuilder. Any combination of output frequencies ranging from 1 to

350 MHz can be configured on each of the device outputs. Up to three unique device configurations can be

specified in a single device, enabling the Si5335 to replace 3 different clock generators or clock buffers.

3.6. Multi-Function Control Inputs

The Si5335 supports five user-defined input pins (pins 3, 5, 6, 12, 19) that are customizable to support the

functions listed below. The pinout of each device is customized using the ClockBuilder utility. This enables the

device to be custom tailored to a specific application. Each of the different functions is described in further detail

below.

Table 14. Multi-Function Control Inputs

Pin Function

Description

Assignable Pin Name

OEB_all

Output Enable All.

P1, P2, P3, P5*, P6*

All outputs enabled when low.

Output Enable Bank 0.

CLK0A/0B enabled when low.

Output Enable Bank 1.

CLK1A/1B enabled when low.

Output Enable Bank 2.

CLK2A/2B enabled when low.

Output Enable Bank 3.

OEB0

OEB1

OEB2

OEB3

P1, P2, P3, P5*, P6*

CLK3A/3B enabled when low.

Rev. 1.2

23

Si5335

FS0

Table 14. Multi-Function Control Inputs (Continued)

Frequency Select.

P1

Selects active device frequency plan from factory-configured

profiles. See “3.8. Frequency Select/Device Reset” for more

information.

FS1

Frequency Select.

P1 (for 2-plan devices)

P2 (for 3-plan devices)

Selects active device frequency plan from factory-configured

profiles. See “3.8. Frequency Select/Device Reset” for more

information.

RESET

SSENB

Reset.

P1, P2, P3

Asserting this pin (driving high) is required to change

FS1,FS0 pin setting. Reset is not required if FS1,FS0 pins are

unassigned.

Spread Spectrum Enable.

P1, P2, P3, P5*, P6*

Enables PCI-compliant spread spectrum clocking on all 100

MHz clock outputs when low.

*Note: See “3.6.1. P5 and P6 Input Control” for recommended termination circuits for these pins.

3.6.1. P5 and P6 Input Control

Control input signals to P5 and P6 cannot exceed 1.2 V. When these inputs are driven from CMOS sources, a

resistive attenuator is required for pins 5 and 6, as shown in Figure 13.

Keep R_seand R_shclose to pin 5 and pin 6

Si5335

R_se

Pin 5, Pin 6

CMOS input signal

50

R_sh

1.8 V CMOS

R_se= 1 k

R_sh= 1.58 k

2.5 V CMOS

1.96 k

1.58 k

3.3 V CMOS

3.09 k

1.58 k

Figure 13. P5, P6 Control Pin Termination

3.7. Output Enable

Each of the device’s four banks of clock outputs can be individually disabled using OEB0, OEB1, OEB2 and OEB3,

respectively. Alternatively, all clock outputs can be disabled using the master output enable OEB_all. When a

Si5335 clock output bank is disabled, the output disable state is determined by the configuration specified in the

ClockBuilder web utility. When one or more banks of clock outputs are enabled or disabled, clock start and stop

transitions are handled glitchlessly.

3.8. Frequency Select/Device Reset

The device frequency plan is customized using the ClockBuilder web utility. The Si5335 optionally supports up to

three unique, pin-selectable configurations per device, enabling one device to replace up to three separate clock

ICs. To select a particular frequency plan, set the FS pins as outlined below:

For custom Si5335 devices configured to support two frequency plans, the FS1 pin should be set as follows:

FS1

Profile

24

Rev. 1.2

Si5335

0

1

2

For custom Si5335 devices configured to support three frequency plans, the FS1 and FS0 pins should be set as

follows:

FS1

0

FS0

0

Profile

Reserved

0

1

2

3

1

0

1

If a change is made to the FS pin settings, the device reset pin (RESET) must be held high for the minimum pulse

width specified in Table 3 on page 5 to change the device configuration. The output clocks will be momentarily

squelched until the device begins operation with the new frequency plan.

If the RESET pin is not selected in ClockBuilder as one of the five programmable pins, a power-on reset must be

applied for an FS pin change to take effect.

3.9. Loss-of-Signal Alarm

The Si5335 supports a loss of signal (LOS) output indicator for monitoring the condition of the crystal/clock

reference input. The LOS condition occurs when there is no input clock to the device or the PLL has lost lock (in

clock generator mode). When an input clock is removed, the LOS pin will assert and the output clocks may drift up

to 5% (in clock generator mode). When the input clock with an appropriate frequency is reapplied, the LOS pin will

deassert. In clock buffer mode, LOS is driven high when the input clock is lost.

LOS Output State

Description

0

Input clock present and

PLL is locked

1

Input clock not present and

PLL is not locked

Rev. 1.2

25

Si5335

3.10. Output Stage

The output stage consists of programmable output drivers as shown in Figure 14.

Output

Stage

VDDO0

CLK0A

CLK0B

VDDO1

CLK1A

CLK1B

VDDO2

CLK2A

CLK2B

VDDO3

CLK3A

CLK3B

Figure 14. Output Stage

The Si5335 devices provide four outputs that can be differential or single-ended. When configured as single-

ended, the driver generates two signals that can be configured as in-phase or complementary. Each of the outputs

has its own output supply pin, allowing the device to be used in mixed supply applications without the need for

external level translators. The CML output driver generates a similar output swing as the LVPECL driver but

consumes half the current. CML outputs must be ac-coupled.

3.10.1. CMOS/LVTTL Outputs

The CMOS output driver has a controlled impedance of about 50 , which includes an internal series resistor of

approximately 22 . For this reason, an external Rs series resistor is not recommended when driving 50  traces.

If the trace impedance is higher than 50 , a series resistor, Rs, should be used. A typical configuration is shown in

Figure 15. A CMOS output driver can be configured with ClockBuilder as a single- or dual-output driver. Dual

otuput configurations support in-phase or complementary outputs. The output supports 3.3, 2.5, and 1.8 V CMOS

signal levels when the appropriate voltage is supplied to the external VDDO pin and the device is configured

accordingly.

3.3, 2.5, or 1.8 V

V_DDOx

LVTTL/

Si5335

CMOS

CLKxA

CLKxB

50

CMOS

Figure 15. Interfacing to a CMOS Receiver

26

Rev. 1.2

Si5335

3.10.2. SSTL and HSTL Outputs

The Si5335 supports both SSTL and HSTL outputs, which can be single-ended or differential. The recommended

termination scheme for SSTL is shown in Figure 16. The V supply can be generated using a simple voltage

TT

divider as shown below (note that Rt = 50 ).

SSTL (3.3, 2.5, or 1.8 V)

V_TT

HSTL (1.5 V)

V_DDOx

SSTL_3

SSTL_2

SSTL_18

HSTL

Rt

Si5335

50

CLKxA

CLKxB

SSTL

or

HSTL

V_DDO

R₁

R₂

V_TT

SSTL_3

SSTL_2, SSTL_18, HSTL

0.1 µF

R₁= 2.43 k

R₂= 2 k

R₁= 2 k

R₂= 2 k

Figure 16. Interfacing the Si5335 to an SSTL or HSTL Receiver

3.10.3. LVPECL Outputs

The LVPECL driver is configurable in both 3.3 V or 2.5 V standard LVPECL modes. The output driver can be ac-

coupled or dc-coupled to the receiver.

3.10.3.1. DC-Coupled LVPECL Outputs

The standard LVPECL driver supports two commonly used dc-coupled configurations. Both of these are shown in

Figure 17a and Figure 17b. LVPECL drivers were designed to be terminated with 50  to VDD–2 V, which is

illustrated in Figure 17a. V can be supplied with a simple voltage divider as shown.

TT

An alternative method of terminating LVPECL is shown in Figure 17b, which is the Thevenin equivalent to the

termination in Figure 17a. It provides a 50  load terminated to V –2.0 V. For 3.3 V LVPECL, use R = 127 and

DD

1

R = 82.5 ; for 2.5 V LVPECL, use R = 250 and R = 62.5 The only disadvantage to this type of termination

2

1

2

is that the Thevenin circuit consumes additional power from the V

supply.

DDO

Rev. 1.2

27

Si5335

Keep termination close to

the receiver

3.3 V, 2.5 V

V_DDOx

50

3.3 V LVPECL

2.5 V LVPECL

Si5335

50

CLKxA

CLKxB

LVPECL

V_TT= V_DDO– 2.0

50

a. DC-Coupled Termination of 50  to V_DDO– 2.0 V

V_DDOV_DDO

Keep termination close to

3.3 V, 2.5 V

V_DDOx

the receiver

R₁

3.3 V LVPECL

2.5 V LVPECL

Si5335

50

CLKxA

CLKxB

LVPECL

3.3 V LVPECL

R₁= 127 

R₂= 82.5 

V_T= V_DDO– 2.0 V

R₂

R₁// R₂= 50 

2.5 V LVPECL

R₁= 250 

R₂= 62.5 

b. DC-Coupled with Thevenin Termination

Figure 17. Interfacing the Si5335 to an LVPECL Receiver Using DC Coupling

28

Rev. 1.2

Si5335

3.10.3.2. AC Coupled LVPECL Outputs

AC coupling is necessary when a receiver and a driver have compatible voltage swings but different common-

mode voltages. AC coupling works well for dc-balanced signals, such as for 50% duty cycle clocks. Figure 18

describes two methods for ac coupling the standard LVPECL driver. The Thevenin termination shown in Figure 18a

is a convenient and common approach when a V (V

– 1.3 V) supply is not available; however, it does

BB

DD

consume additional power. The termination method shown in Figure 18b consumes less power. A V supply can

BB

be generated from a simple voltage divider circuit as shown in Figure 18b.

V_DDOV_DDO

Keep termination close to

the receiver

3.3 V, 2.5 V

V_DDOx

R₁

3.3 V LVPECL

2.5 V LVPECL

0.1 µF

Si5335

50

CLKxA

CLKxB

LVPECL

V_DDO– 1.3 V

R₁// R₂= 50 

3.3 V LVPECL

R₁= 82.5 

R₂= 127 

R₂

Rb

2.5 V LVPECL

Rb = 130  (2.5 V LVPECL)

Rb = 200 ꢀ(3.3 V LVPECL)

R₁= 62.5 

R₂= 250 

a. AC-Coupled with Thevenin Termination

Keep termination close to

3.3 V, 2.5 V

V_DDOx

the receiver

0.1 µF

50

3.3 V LVPECL

2.5 V LVPECL

Si5335

50

CLKxA

CLKxB

V_BB

LVPECL

0.1 µF

50

V_DDO

V

_DDO– 1.3 V

Rb

R₁

Rb = 130  (2.5 V LVPECL)

Rb = 200  (3.3 V LVPECL)

V_BB

R₂

0.1 µF

b. AC Coupled with 100  Termination

Figure 18. Interfacing to an LVPECL Receiver Using AC Coupling

Rev. 1.2

29

Si5335

3.10.4. LVDS Outputs

The LVDS output option provides a very simple and power-efficient interface that requires no external biasing when

connected to an LVDS receiver. An ac-coupled LVDS driver is often useful as a CML driver. The LVDS driver may

be dc-coupled or ac-coupled to the receiver in 3.3 V or 2.5 V output mode.

3.10.4.1. AC-Coupled LVDS Outputs

The Si5335 LVDS output can drive an ac-coupled load. The ac coupling capacitors may be placed at either the

driver or receiver end, as long as they are placed prior to the 100  termination resistor. Keep the 100 

termination resistor as close to the receiver as possible, as shown in Figure 19. When a 1.8 V output supply

voltage is used, the LVDS output of the Si5335 produces a common-mode voltage of ~0.875 V, which does not

support the LVDS standard. In this case, it is best to ac-couple the output to the load.

Keep termination close to

the receiver

3.3 V or 2.5 V

V_DDO

x

Si5335

50

LVDS

CLKxA

CLKxB

LVDS

100 

DC-Coupled LVDS Output

Keep termination close to

the receiver

3.3 V, 2.5 V, or 1.8 V

V_DDO

x

0.1 µF

100 

0.1 µF

Si5335

50

CLKxA

CLKxB

LVDS

AC-Coupled LVDS Output

Figure 19. Interfacing to an LVDS Receiver

30

Rev. 1.2

Si5335

3.10.5. HCSL Outputs

Host clock signal level (HCSL) outputs are commonly used in PCI Express applications. A typical HCSL driver has

an open source output that requires an external series resistor and a resistor to ground. The Si5335 HCSL driver

has integrated these resistors to simplify the interface to an HCSL receiver. No external components are necessary

when connecting the Si5335 HCSL driver to an HCSL receiver.

3.3, 2.5, or 1.8 V

V_DDOx

Rs

50

HCSL

CLKxA

CLKxB

HCSL

Rt

Si5335

Figure 20. Interfacing the Si5335 to an HCSL Receiver

3.10.6. CML Outputs

Current mode logic (CML) is transmitted differentially and terminated to 50  to Vcc as shown in Figure 20. A CML

receiver can be driven with either an LVPECL, CML, or LVDS output. To drive a CML receiver, an Si5335 output

configured in LVPECL or CML mode generates a single-ended output swing of 550 mV to 960 mV. However, to

reduce power consumption by approximately 15 mA per output driver pair (compared to an LVPECL-configured

output), the Si5335's CML output mode can be selected without affecting the output voltage swing. For even lower

power consumption, depending on the input signal swing required, CML receivers can be driven with an Si5335

output configured in LVDS mode. CML output format is not available when the Si5335 is in PLL bypass (clock

buffer) mode.

Driving a CML Receiver Using the LVPECL Output

550 mV to 960 mVp-p

Si5335

CML

Receiver

0.1 µF

50

Vcc

50

LVPECL

50

Rb

Rb = 130 ꢀ(2.5 V LVPECL)

Rb = 200 ꢀ(3.3 V LVPECL)

Driving a CML Receiver Using the CML or LVDS Output

CML

Receiver

670 mV to 1070 mVp-p (CML)

250 mV to 450 mVp-p (LVDS)

Si5335

0.1 µF

50

Vcc

50

CML or

LVDS

50

Figure 21. Terminating an LVPECL or an LVDS Output to a CML Receiver

Rev. 1.2

31

Si5335

4. Power Consumption

In clock generator mode, the Si5335 Power consumption is a function of the following:

 Supply voltage

 Frequency of output Clocks

 Number of output Clocks

 Format of output Clocks

Because of internal voltage regulation, the current from the core V is independent of the V voltage and hence

DD

the plot shown in Figure 5 can be used to estimate the V core (pins 7 and 24) current.

DD

The current from the output supply voltages can be estimated from the values provided in Table 2, “DC

Characteristics,” on page 4. To get the most accurate value for V

Desktop software should be used.

currents, the Si5338-EVB with ClockBuilder

DD

To do this, go to the “Power” tab of ClockBuilder Desktop and press “Measure”. In this manner, a specific

configuration can be implemented on the EVB and the actual current for each supply voltage measured. When

doing this it is critical that the output drivers have the proper load impedance for the selected format.

When testing for output driver current with HSTL and SSTL, it is required to have load circuitry as shown in "3.10.2.

SSTL and HSTL Outputs" on page 27. The Si5338 EVB has layout pads that can be used for this purpose. When

testing for output driver current with LVPECL the same layout pads can be used to implement the LVPECL bias

resistor of 130  (2.5 V VDDx) or 200  (3.3 V VDDx). See the schematic in the Si5338-EVB data sheet and

AN408 for additional information.

80

4 Active Outputs, Fractional Output MS

4 Active Outputs, Integer Output MS

3 Active Outputs, Fractional Output MS

3 Active Outputs, Integer Output MS

2 Active Outputs, Fractional Output MS

2 Active Outputs, Integer Output MS

1 Active Output, Fractional Output MS

1 Active Output, Integer Output MS

75

70

65

60

55

50

45

40

35

30

0

50

100

150

200

250

300

350

400

Output Frequency (MHz)

Figure 22. Core VDD Supply Average Current vs Output Frequency

32

Rev. 1.2

Si5335

5. Spread Spectrum

To help reduce electromagnetic interference (EMI), the Si5335 supports spread spectrum modulation in clock

generator mode only. The output clock frequencies can be modulated to spread energy across a broader range of

frequencies, lowering system EMI. Spread spectrum modulation is generated digitally in the output MultiSynth

dividers, which means that the spread spectrum parameters are virtually independent of process, voltage, and

temperature variations.

If the SSENB function is assigned to a pin in ClockBuilder and asserted (driven low), PCIe-compliant spread

spectrum is applied to all 100 MHz output clocks with a default spreading rate of 31.5 kHz and 0.5% down spread.

If no 100 MHz output clocks are defined but the SSENB is assigned and asserted, none of the output clocks will

have spread spectrum clocking applied. Some custom spread-spectrum clocking profiles are available. If the

Si5335's default PCIe spread spectrum profile is not suitable for your application, submit your custom spread

spectrum requirements for review by visiting the Silicon Labs Technical Support web page at https://

www.silabs.com/support/pages/contacttechnicalsupport.aspx, or contact your local Silicon Labs sales

representative for more information.

Clock with

SSC Off

Reduced

Amplitude and

EMI

Clock with

SSC On

(downspread)

Carrier Frequency

f

Figure 23. Spread Spectrum Clocking Impact on Output Power Spectrum

Rev. 1.2

33

Si5335

6. Jitter Performance

The Si5335 provides consistently low jitter for any combination of output frequencies. The device leverages a low

phase noise single PLL architecture and Silicon Laboratories’ patented MultiSynth fractional output divider

technology to deliver period jitter of 10 ps pk-pk (typ). The Si5335 provides superior performance to conventional

multi-PLL solutions which may suffer from degraded jitter performance depending on frequency plan and the

number of active PLLs.

7. Power Supply Considerations

The Si5335 has 2 core supply voltage pins (V ) and 4 clock output bank supply voltage pins (V

–V

),

DDO3

DD

DDO0

enabling the device to be used in mixed supply applications. The Si5335 does not typically require ferrite beads for

power supply filtering. The device has extensive on-chip power supply regulation to minimize the impact of power

supply noise on output jitter. Figure 24 shows that the additive jitter created when a significant amount of noise is

applied to the device power supply is very low.

10

VDDO

VDD

9

8

7

6

5

4

3

2

1

0

0.0001

0.001

0.01

0.1

1

Modulation Frequency (MHz)

Figure 24. Peak-to-Peak Additive Jitter from 100 mV Sine Wave on Supply

34

Rev. 1.2

Si5335

8. Loop Bandwidth Considerations

For synchronous reference clock applications, two user-selectable loop bandwidth settings (1.6 MHz and 475 kHz)

are available to allow designers to optimize their timing system to support jitter attenuation of the reference clock.

In general, the 1.6 MHz setting provides the lowest output jitter and should be selected for most applications. The

1.6 MHz option provides faster PLL tracking of the input clock but less jitter attenuation of the input clock than the

475 kHz loop bandwidth option. The 1.6 MHz loop bandwidth option must be selected for all applications which use

a crystal reference input on the XA/XB pins (pins 1 and 2) and for all applications which provide a low jitter input

clock reference to the Si5335.

The 475 kHz setting reduces the clock generator's loop bandwidth, which has the benefit of attenuating some of

jitter that would normally pass through the 1.6 MHz setting. As the PLL loop bandwidth decreases, the intrinsic jitter

of the device increases and is reflected in higher jitter generation specifications, but total output jitter is the best

measure of system performance. Total output jitter includes both the generated jitter as well as the transferred jitter.

This lower loop bandwidth option can be useful in some applications, such as PCIe, DSL or other systems which

may utilize backplane distributed reference clocks. In these systems, the input clock may have appreciable low

frequency jitter (e.g., < 1.6 MHz). The source of the reference clock jitter can arise from suboptimal PCB trace

layouts, impedance mismatches and connectors. Input clock jitter may also be generated from an IC which has

poor power supply rejection performance, resulting in switching power supply noise and jitter coupling onto the

clock input of the Si5335. In these applications, designers may opt to use the 475 kHz loop bandwidth to help

attenuate the input clock jitter. Proper selection of PLL loop bandwidth involves a number of application-specific

considerations. Refer to “AN513: Jitter Attenuation—Choosing the Right Phase-Locked Loop Bandwidth” for more

information.

Please also refer to “AN624: Si5335 Solves Timing Challenges in PCI Express, Computing, Communications and

FPGA-Based Systems”.

Rev. 1.2

35

Si5335

9. Applications of the Si5335

Because of its flexible architecture, the Si5335 can be configured to serve several functions in the timing path. The

following sections describe some common applications.

9.1. Free-Running Clock Generator

Using the internal oscillator (Osc) and an inexpensive external crystal (XTAL), the Si5335 can be configured as a

free-running clock generator for replacing high-end and long-lead-time crystal oscillators found on many printed

circuit boards (PCBs). Replacing several crystal oscillators with a single IC solution helps consolidate the bill of

materials (BOM), reduces the number of suppliers, and reduces the number of long-lead-time components on the

PCB. In addition, since crystal oscillators tend to be the least reliable aspect of many systems, the overall failure-in-

time (FIT) rate improves with the elimination of each oscillator.

Up to four independent clock frequencies can be generated at any rate within its supported frequency range and

with any of supported output types. Figure 25 shows the Si5335 configured as a free-running clock generator.

ref

Osc

PLL

XTAL

MS0

MS1

MS2

MS3

F₀

F₁

F₂

F₃

Si5335

Figure 25. Si5335 as a Free-Running Clock Generator

9.2. Synchronous Frequency Translation

In other cases, it is useful to generate an output frequency that is synchronous (or phase-locked) to another clock

frequency. The Si5335 is the ideal choice for generating up to four clocks with different frequencies with a fixed

phase relationship to an input reference. Because of its highly precise frequency synthesis, the Si5335 can

generate all four output frequencies with 0 ppm error to the input reference. The Si5335 is an ideal choice for

applications that have traditionally required multiple stages of frequency synthesis to achieve complex frequency

translations. Examples are in broadcast video (e.g., 148.5 MHz to 148.3516483 MHz), WAN/LAN applications (e.g.

155.52 MHz to 156.25 MHz), and Forward Error Correction (FEC) applications (e.g., 156.25 MHz to

161.1328125 MHz). Figure 26 shows the Si5335 configured as a synchronous clock generator. Frequencies may

be entered into the ClockBuilder Web utility with up to seven decimal points to ensure that the exact frequencies

can be achieved.

Si5335

MS0

MS1

MS2

MS3

F₀

F₁

F₂

F₃

CLKIN

PLL

Figure 26. Si5335 as a Synchronous Clock Generator or Frequency Translator

36

Rev. 1.2

Si5335

9.3. Configurable Universal Buffer and Level Translator

Using the ClockBuilder web utility, the synthesis stage can be entirely bypassed allowing the Si5335 to act as a

configurable clock buffer with level translation. Because of its highly selectable configuration, virtually any output

format and I/O voltage combination is possible. The configurable output drivers allow four differential outputs, eight

single-ended outputs, or a combination of both. Figure 27 shows the Si5335 configured as a flexible clock buffer

supporting mixed I/O supplies.

Si5335

3.3 V LVDS

2.5 V CMOS

CLKIN

1.8 V LVPECL

3.3 V HCSL

Figure 27. Si5335 as a Configurable Clock Buffer with Level Translation

Rev. 1.2

37

Si5335

10. Pin Descriptions

Top View

24

23

22

21

20

19

1

2

3

4

XA/CLKIN

18

17

16

15

CLK1A

XB/CLKINB

P3

CLK1B

VDDO1

GND

Pad

GND

VDDO2

CLK2A

CLK2B

5

6

14

13

P5

P6

7

8

9

10

12

11

Note: Center pad must be tied to GND for normal operation.

Table 15. Si5335 Pin Descriptions

Pin #

Pin Name

I/O

Signal Type

Description

XA/CLKIN, XB/CLKINB.

These pins are used as the main differential or single-ended clock

input or as the XTAL input. See "3.4. Input Configuration" on page

19 and Figures 10, 11, and 12 for connection details. Clock inputs

to these pins must be ac-coupled. Keep the traces from pins 1,2 to

the crystal as short as possible and keep other signals and radiat-

ing sources away from the crystal. The single-ended input voltage

swing must be limited to 1.2 Vpp.

XA/CLKIN,

XB/CLKINB

1,2

I

Multi

Multi-Function Input. 3.3 V tolerant.

This pin functions as a multi-function input pin. The pin function

(OEB_all, OEB0, OEB1, OEB2, OEB3, SSENB, or RESET) is

user-selectable at time of configuration using the ClockBuilder web

configuration utility.

3

4

P3

I

Multi

GND

Ground.

GND

Must be connected to system ground for proper device operation.

Multi-Function Input.

These pins function as multi-function input pins. The pin functions

(OEB_all, OEB0, OEB1, OEB2, OEB3, or SSENB) are user-

selectable at time of configuration using the ClockBuilder configu-

ration utility. A resistor voltage divider is required when driven by a

signal greater than 1.2 V. See "3.6.1. P5 and P6 Input Control" on

page 24 for details.

5,6

P5, P6

VDD

I

Multi

Core Supply Voltage.

This is the core supply voltage, which can operate from a 1.8, 2.5,

or 3.3 V supply. A 0.1 µF bypass capacitor should be located very

close to this pin.

7

VDD

Supply

38

Rev. 1.2

Si5335

Table 15. Si5335 Pin Descriptions (Continued)

Pin #

Pin Name

I/O

Signal Type

Description

Loss of Signal.

A typical pullup resistor of 1–4 k is used on this pin. This pin can

be pulled up to a supply voltage as high as 3.6 V regardless of the

other supply voltages on pins 7, 11, 15, 16, 20, and 24. The LOS

condition allows the pull up resistor to pull the output up to the

supply voltage. See "3.9. Loss-of-Signal Alarm" on page 25.

8

LOS

O

Open Drain

This pin functions as an input clock loss-of-signal and PLL lock

status pin in clock generator mode:

0 = Input clock present and PLL locked.

1 = Input clock not present or PLL not locked.

In clock buffer mode, LOS is asserted when the input clock is not

present.

Output Clock B for Channel 3.

May be a single-ended output or half of a differential output with

CLK3A being the other differential half. If unused, leave this pin

floating.

9

CLK3B

CLK3A

VDDO3

O

Multi

Output Clock A for Channel 3.

May be a single-ended output or half of a differential output with

CLK3B being the other differential half. If unused, leave this pin

floating.

10

11

Output Clock Supply Voltage.

Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK3A,B. A 0.1 µF

capacitor must be located very close to this pin. If CLK3 is not

used, this pin must be tied to VDD (pin 7, 24).

VDD

Supply

Multi-Function Input. 3.3 V tolerant.

This pin functions as a multi-function input pin. The pin function

(OEB_all, OEB0, OEB1, OEB2, OEB3, SSENB, FS0, FS1, or

RESET) is user-selectable at time of configuration using the Clock-

Builder web configuration utility

12

P1

I

Multi

Output Clock B for Channel 2.

May be a single-ended output or half of a differential output with

CLK2A being the other differential half. If unused, leave this pin

floating.

13

14

15

16

CLK2B

CLK2A

VDDO2

VDDO1

O

Multi

Output Clock A for Channel 2.

May be a single-ended output or half of a differential output with

CLK2B being the other differential half. If unused, leave this pin

floating.

O

Output Clock Supply Voltage.

Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK2A,B.

A 0.1 µF capacitor must be located very close to this pin. If CLK2 is

not used, this pin must be tied to VDD (pin 7, 24).

VDD

Supply

Output Clock Supply Voltage.

Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK1A,B.

A 0.1 µF capacitor must be located very close to this pin. If CLK1 is

not used, this pin must be tied to VDD (pin 7, 24).

Rev. 1.2

39

Si5335

Table 15. Si5335 Pin Descriptions (Continued)

Pin #

Pin Name

I/O

Signal Type

Description

Output Clock B for Channel 1.

May be a single-ended output or half of a differential output with

CLK1A being the other differential half. If unused, leave this pin

floating.

17

CLK1B

CLK1A

O

Multi

Output Clock A for Channel 1.

May be a single-ended output or half of a differential output with

CLK1B being the other differential half. If unused, leave this pin

floating.

18

19

O

I

Multi

Multi-Function Input. 3.3 V tolerant.

This pin functions as a multi-function input pin. The pin function

(OEB_all, OEB0, OEB1, OEB2, OEB3, SSENB, FS1, or RESET)

is user-selectable at time of configuration using the ClockBuilder

web configuration utility.

P2

Output Clock Supply Voltage.

Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK0A,B.

A 0.1 µF capacitor must be located very close to this pin. If CLK0 is

not used, this pin must be tied to VDD (pin 7, 24).

20

21

VDDO0

CLK0B

VDD

O

Supply

Multi

Output Clock B for Channel 0.

May be a single-ended output or half of a differential output with

CLK0A being the other differential half. If unused, leave this pin

floating.

22

CLK0A

O

Multi

Output Clock A for Channel 0.

May be a single-ended output or half of a differential output with

CLK0B being the other differential half. If unused, leave this pin

floating.

23

24

RSVD_GND GND

GND

Supply

GND

Ground.

Must be connected to system ground. Minimize the ground path

impedance for optimal performance of this device.

VDD

GND

VDD

GND

Core Supply Voltage.

The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 µF

bypass capacitor should be located very close to this pin.

GND

PAD

Ground Pad.

This is the large pad in the center of the package. The device will

not function unless the ground pad is properly connected to a

ground plane on the PCB. See Table 17, “PCB Land Pattern,” on

page 43 for ground via requirements.

40

Rev. 1.2

Si5335

11. Ordering Information

GMR

Si5335X

BXXXXX

Operating Temp Range: -40 to +85 °C

Package: 4 x 4 mm QFN, RoHS6, Pb-free

R = Tape & Reel (ordering option)

Non Tape & Reel shipment media is trays

B = Product Revision B

XXXXX = NVM code.

Custom NVM configuration code. A unique 5-digit ordering code

will be assigned by the ClockBuilder web utility.

Frequency/Configuration:

Si5335A - 1 MHz to 350 MHz output with XTAL input

Si5335B - 1 MHz to 200 MHz output with XTAL input

Si5335C - 1 MHz to 350 MHz output with Differential/Single-ended input clock

Si5335D - 1 MHz to 200 MHz output with Differential/Single-ended input clock

Evaluation Boards

Si5335 Evaluation Board

Si5338

EVB

The Si5338-EVB with ClockBuilder Desktop software includes the ability to evaluate Si5335 output

frequency and format configurations. The EVB does not currently include the ability to control the

programmable function pins (P1, P2, P3, P5, and P6).

Rev. 1.2

41

Si5335

12. Package Outline: 24-Lead QFN

Figure 28. 24-Lead Quad Flat No-lead (QFN)

Table 16. Package Dimensions

Dimension

Min

0.80

0.00

0.18

Nom

0.85

Max

0.90

0.05

0.30

A

A1

b

0.02

0.25

D

4.00 BSC.

2.50

D2

e

2.35

2.65

0.50 BSC.

4.00 BSC.

2.50

E

E2

L

2.35

0.30

2.65

0.50

0.40

aaa

bbb

ccc

ddd

eee

0.10

0.08

0.10

0.05

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body

Components.

5. J-STD-020 MSL rating: MSL3.

6. Terminal base alloy: Cu

7. Terminal plating/grid array material: Au/NiPd.

8. Visit www.silabs.com/support/quality/pages/RoHSInformation.aspx for more information.

42

Rev. 1.2

Si5335

13. Recommended PCB Land Pattern

Table 17. PCB Land Pattern

Dimension

Min

Nom

Max

2.60

0.30

0.85

P1

P2

X1

Y1

C1

C2

E

2.50

0.20

0.75

2.55

0.25

0.80

3.90

0.50

Notes

General:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

4. Connect the center ground pad to a ground plane with no less than five vias. These 5 vias should have a length of no

more than 20 mils to the ground plane. Via drill size should be no smaller than 10 mils. A longer distance to the ground

plane is allowed if more vias are used to keep the inductance from increasing.

Solder Mask Design:

5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to

be 60 µm minimum, all the way around the pad.

Stencil Design:

6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder

paste release.

7. The stencil thickness should be 0.125 mm (5 mils).

8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.

9. A 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad.

Card Assembly:

10. A No-Clean, Type-3 solder paste is recommended.

11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

Rev. 1.2

43

Si5335

14. Top Marking

14.1. Si5335 Top Marking

Si5335

Xxxxxx

RTTTTT

YYWW

14.2. Top Marking Explanation

Line

Characters

Description

Line 1

Si5335

Base part number.

X = Frequency and configuration code. See "11. Ordering Information"

on page 41 for more information.

xxxxx = NVM code assigned by ClockBuilder web utility.

See "11. Ordering Information" on page 41.

Line 2

Line 3

Xxxxxx

R = Product revision.

TTTTT = Manufacturing trace code.

RTTTTT

Circle with 0.5 mm diameter;

left-justified

Pin 1 indicator.

YY = Year.

Line 4

WW = Work week.

YYWW

Characters correspond to the year and work week of package assem-

bly.

44

Rev. 1.2

Si5335

Revision 1.0 to Revision 1.1

DOCUMENT CHANGE LIST

Revision 0.4 to Revision 0.9

 Updated Table 8 on page 10 and Table 9 on

page 12.

 Updated Table 2, “DC Characteristics,” on page 4.

Added core power supply specification in buffer mode.

 Updated Table 3, “Performance Characteristics,” on

page 5.

Updated typical specifications for total jitter for PCI

Express 1.1 Common clocked topology.

Updated typical specifications for RMS jitter for PCI

Express 2.1 Common clocked topology.

 Updated Table 10 on page 13.

Added T

specification.

RESET

Updated typical additive jitter (12 kHz–20MHz) from

 Updated Table 4, “Input and Output Clock

0.150 to 0.165 ps RMS.

Characteristics,” on page 6.

 Added " Document Change List" on page 45.

Corrected V on pin 1 to 1.3 V (max).

I

Revision 1.1 to Revision 1.2

Updated CML output voltage specification to 0.86 Vpp.

 Updated Table 6, “Crystal Specifications for

25 MHz,” on page 9.

 Removed down spread spectrum errata that has

been corrected in revision B.

Corrected CL to 18 pF (typical).

 Updated ordering information to refer to revision B

 Updated Table 7, “Crystal Specifications for

27 MHz,” on page 9.

silicon.

 Updated top marking explanation in Section 14.2.

Corrected CL to 18 pF (typical).

 Updated "3.4. Input Configuration" on page 19.

Revised text in Section 3.4.2.

 Updated "3.6.1. P5 and P6 Input Control" on page

24.

Added Figure 13 to replace Table 15.

 Updated Figure 21 on page 31.

 Updated Table 14 on page 23.

Corrected Assignable Pin Name column entries.

 Updated "3.10. Output Stage" on page 26.

Revised throughout and included termination circuit

diagrams and text.

 Removed references to P4 as a programmable pin

option throughout document. Pin 4 is now a ground

pin.

Revision 0.9 to Revision 1.0

 Updated Table 9 on page 12.

DSL random jitter from 2.1 ps RMS (typ) to 1.95 ps RMS

(typ) and from "—" (max) to 2.2 ps RMS (max).

 Corrected text in “9.2. Synchronous Frequency

Translation” to match the capabilities of the

ClockBuilder web utility.

Rev. 1.2

45

Si5335

CONTACT INFORMATION

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Please visit the Silicon Labs Technical Support web page:

https://www.silabs.com/support/pages/contacttechnicalsupport.aspx

and register to submit a technical support request.

Patent Notice

Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-

intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features

or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-

resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-

quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to

support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-

sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-

plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

46

Rev. 1.2

型号:	SI5335B-B01250-GM
是否Rohs认证：	符合
生命周期：	Active
包装说明：	HVQCCN,
Reach Compliance Code：	unknown
风险等级：	5.8
其他特性：	ALSO OPERATES WITH 2.5V AND 3.3V NOMINAL SUPPLY
JESD-30 代码：	S-XQCC-N24
JESD-609代码：	e4
长度：	4 mm
湿度敏感等级：	3
端子数量：	24
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出时钟频率：	200 MHz
封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN
封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260
主时钟/晶体标称频率：	350 MHz
座面最大高度：	0.9 mm
最大供电电压：	1.98 V
最小供电电压：	1.71 V
标称供电电压：	1.8 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Gold (Au)
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

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