Si5338
management, etc.) or in applications where frequency
3.9. Reset Options
margining (e.g., f
±5%) is necessary for design
out
There are two types of resets on the Si5338, POR and
soft reset. A POR reset automatically occurs whenever
the supply voltage on the VDD is applied.
verification and manufacturing test. Frequency
increment or decrement can be applied as fast as
2
1.5 MHz when it is done by pin control. When under I C
The soft reset is forced by writing 0x02 to register 246.
This bit is not self-clearing, and thus it may read back as
a 1 or a 0. A soft reset will not download any pre-
programmed NVM and will not change any register
values in RAM.
control, the frequency increment and decrement update
rate is limited by the I C bus speed. The magnitude of
the frequency step has 0 ppm error. Frequency steps
are seamless and glitchless.
2
If a frequency increment/decrement command causes
the MultiSynth output frequency to exceed the
maximum/minimum limits, then a glitch on the output is
likely to occur. The max frequency of a MultiSynth
output that is using frequency increment/decrement is
Fvco/8, and the minimum frequency is 5 MHz.
The soft reset performs the following sequence:
1. All outputs turn off except if programmed to be
always on.
2. Internal calibrations are done and MultiSynths are
initialized.
3.10.2. Output Phase Increment/Decrement
a. Outputs that are synchronous are phase
aligned (if Rn = 1).
The Si5338 has a digitally-controlled glitchless phase
increment and decrement feature that allows adjusting
the phase of each output clock in relation to the other
output clocks. The phase of each output clock can be
adjusted with an accuracy of 20 ps over a range of
±45 ns. Setting of the step size and control of the phase
increment or decrement is accomplished through the
3. 25 ms is allowed for the PLL to lock (no delay occurs
when FCAL_OVRD_EN = 1).
4. Turn on all outputs that were turned off in step 1.
3.10. Features of the Si5338
The Si5338 offers several features and functions that
are useful in many timing applications. The following
paragraphs describe in detail the main features and
typical applications. All of these features can be easily
configured using the ClockBuilder Desktop. See "3.1.1.
ClockBuilder™ Desktop Software" on page 18.
2
I C interface. Alternatively, the Si5338 can be ordered
with optional phase increment (PINC) and phase
decrement (PDEC) pins for pin-controlled applications.
In pin controlled applications the phase increment and
2
decrement update rate is as fast as 1.5 MHz. In I C
applications, the maximum update rate is limited by the
2
3.10.1. Frequency Increment/Decrement
speed of the I C. See Table 17 for ordering information
Each of the output clock frequencies can be of pin-controlled devices. When phase is decremented,
independently stepped up or down in predefined steps the MultiSynth output clock edge will happen sooner,
as low as 1 ppm per step and with a resolution of which will create a single half cycle that is shorter than
1 ppm. Setting of the step size and control of the expected for the MultiSynth output clock frequency.
frequency increment or decrement is accomplished Care must be taken to insure that a single phase
2
through the I C interface. Alternatively, the Si5338 can decrement does not produce a half cycle that is less
be ordered with optional frequency increment (FINC) than 4/fvco or an unwanted glitch in the MultiSynth
and frequency decrement (FDEC) pins for pin- output may occur.
controlled applications. Note that FINC and FDEC pins
The phase increment and decrement feature provides a
only affect CLK0. Frequency increment and decrement
useful method for fine tuning setup and hold timing
2
of all other channels must be performed by I C writes to
margins or adjusting for mismatched PCB trace lengths.
the appropriate registers. See Table 17 on page 37 for
3.10.3. Programmable Initial Phase Offset
ordering information of pin-controlled devices. When
Each output clock can be set for its initial phase offset
phase is decremented, the MultiSynth output clock edge
up to ±45 ns. In order for the initial phase offset to be
will happen sooner which will create a single half cycle
applied correctly at power up, the VDDOx output supply
that is shorter than expected for the MultiSynth output
voltage must cross 1.2 V before the VDD (pins 7,24)
clock frequency. Care must be taken to insure that a
core power supply voltage crosses 1.45 V. This applies
single phase decrement does not produce a half cycle
to the each driver output individually. A soft_reset will
that is less than 4/fvco or an unwanted glitch in the
also guarantee that the programmed Initial Phase Offset
MultiSynth output may occur.
is applied correctly. The initial phase offset only works
on outputs that have their R divider set to 1.
The frequency increment and decrement feature is
useful in applications requiring a variable clock
frequency (e.g., CPU speed control, FIFO overflow
Rev. 1.6
27
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