SI5356B-A00322-GMR全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

Si5356B

I²C PROGRAMMABLE, ANY-FREQUENCY 1–200 MHZ,

QUAD FREQUENCY 8-OUTPUT CLOCK GENERATOR

Features



Generates any frequency from 1 to

200 MHz on each of the 4 output banks

Eight CMOS clock outputs

Programmable frequency configuration

0 ppm frequency synthesis error for any

combination of frequencies



OEB pin disables all outputs or per

bank OEB control via I²C

Low jitter: 1.5 ps rms phase jitter

Excellent PSRR performance

eliminates need for external power

supply filtering



19 to 30 MHz xtal or 5–200 MHz input clk

Easy to use programming software

Configurable “triple A” spread spectrum:

any clock, any frequency, and with any

spread amount

Programmable output phase adjustment

with <20 ps error

Interrupt pin indicates LOS or LOL



Low power: 45 mA (core)

Core VDD: 1.8, 2.5, or 3.3 V

Separate VDDO for each bank of

outputs: 1.8, 2.5, or 3.3 V

Small size: 4x4 mm 24-QFN

Pb-free, RoHS-6 compliant

Industrial temperature range:

–40 to +85 °C

Ordering Information:



See page 25.



Pin Assignments

Applications



Printers



Storage

Switches/routers

Computing

Servers

OC-3/OC-12 line cards

Audio/video

Networking

Communications

Description

The Si5356B is a highly flexible, I²C programmable clock generator capable of

synthesizing four completely non-integer related frequencies up to 200 MHz. The

device has four banks of outputs with each bank supporting two CMOS outputs at

the same frequency. Using Silicon Laboratories' patented MultiSynth fractional

divider technology, all outputs have 0 ppm frequency synthesis error regardless of

configuration, enabling the replacement of multiple clock ICs and crystal

oscillators with a single device. Each output bank is independently configurable to

support 1.8, 2.5, or 3.3 V. The device is programmable via an I²C/SMBus-

compatible serial interface and supports operation from a 1.8, 2.5, or 3.3 V core

supply.

Functional Block Diagram

Si5356B

*Refer to Ordering Guide for custom part numbers.

Rev. 1.4

Si5356B

2

Rev. 1.4

Si5356B

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.1. Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.2. MultiSynth Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.3. Input and Output Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.4. Configuring the Si5356B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

™

3.5. ClockBuilder Desktop Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.6. Output Phase Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.7. CMOS Output Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.8. Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.9. Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.10. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.11. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.12. Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.1. Custom Device Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

6. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

7. Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

8.1. Custom Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

9.1. Si5356B Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

10. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Rev. 1.4

3

Si5356B

1. Electrical Specifications

Table 1. Recommended Operating Conditions

(V_DD= 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Ambient Temperature

Core Supply Voltage

Symbol

Test Condition

Min

–40

Typ

—

Max

85

Unit

o

T

C

A

V

2.97

2.25

1.71

3.3

2.5

1.8

—

3.63

2.75

1.98

3.63

V

DD

V

Output Buffer Supply Voltage

DDO

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating

conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless

otherwise noted.

Table 2. DC Characteristics

(V_DD= 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

I

100 MHz on all outputs,

25 MHz refclk

—

45

60

mA

Core Current Consumption

DD

I

CMOS, 50 MHz 15 pF

—

6

13

10

7

9

mA

Output Buffer Supply Current

DDOX

1

load

1,2

CMOS, 200 MHz

3.3 V

,

18

14

10

1,2

CMOS, 200 MHz

2.5 V

1,2

CMOS, 200 MHz

1.8 V

V

CLKIN, I2C_LSB

SSC_DIS, OEB

CLKIN, I2C_LSB

SSC_DIS, OEB

Pins: CLK0-7

0.8 x V

0.85

–0.2

—

3.63

1.2

V

High Level Input Voltage

Low Level Input Voltage

IH

DD

V

0.2 x V

0.3

IL

DD

V

– 0.3

DDO

—

Clock Output High Level

Output Voltage

OH

I

= –4 mA

OH

V

Pins: CLK0-7

—

20

0.3

0.4

—

V

Clock Output Low Level

Output Voltage

OL

I

= +4 mA

OH

V

Pin: LOS

= +3 mA

0

INTR Low Level Output

Voltage

OLINTR

I

OH

R

—

k

SSC_DIS, OEB Input

Resistance

IN

Notes:

1. Single CMOS driver active.

2. Measured into a 5”, 50 trace with a 2 pF load.

4

Rev. 1.4

Si5356B

Table 3. AC Characteristics

(V_DD= 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Input Clock

Symbol

Test Condition

Min

Typ

Max

Unit

F

5

—

2

200

2.3

60

MHz

ns

Clock Input Frequency

Clock Input Rise/Fall Time

Clock Input Duty Cycle

Clock Input Capacitance

Output Clocks

IN

T /T

20 to 80% V

—

40

—

R

F

DD

DC

< 2 ns tr/tf

%

C

—

pF

IN

F

1

—

200

1

MHz

ppb

Clock Output Frequency

O

F

See "3.3. Input and Output

Frequency Configuration"

on page 11

—

Clock Output Frequency Synthesis

Resolution

RES

C

—

15

pF

ns

Output Load Capacitance

Clock Output Rise/Fall Time

L

T /T

20 to 80% V

,

2.0

R

F

DD

C = 15 pF

L

T /T

20 to 80% V

DD

—

0.45

0.85

ns

Clock Output Rise/Fall Time

R

F

C = 2 pF

L

DC

T

Measured at V /2

45

—

50

—

55

2

%

ms

μs

ps

Clock Output Duty Cycle

Powerup Time

DD

POR to output clock valid

PU

OE

T

—

10

Output Enable Time

Output-Output Skew

T

Outputs at same

–150

+150

SKEW

frequency, f

> 5 MHz

OUT

J

10000 cycles

—

50

40

75

70

—

ps pk-pk

ps pk

Period Jitter

PPKPK

1

J

Cycle-Cycle Jitter

CCPK

2

J

MultiSynth in integer

mode, 5 kHz to 1 MHz

1.5

ps rms

Phase Jitter

PH

F

—

1.6

—

MHz

PLL Loop Bandwidth

BW

Interrupt Status Timing

t

—

2.6

0.2

5

1

μs

CLKIN Loss of Signal Assert Time

LOS

t

0.01

CLKIN Loss of Signal Deassert

Time

LOS_b

Notes:

1. Measured in accordance to JEDEC standard 65.

2. Phase Jitter only guaranteed for Multisynth0.

Rev. 1.4

5

Si5356B

Table 4. Crystal Specifications for 19 to 26 MHz

Parameter

Crystal Frequency

Symbol

Min

Typ

Max

Unit

f

19

25

26

MHz

XTAL

c (supported)*

11

12

13

pF

L

Load Capacitance (on-chip differential)

c (recommended)

17

—

18

—

19

5

pF



L

Crystal Output Capacitance

Equivalent Series Resistance

Crystal Max Drive Level

c

O

r

—

100

—

ESR

d

100

μW

L

*Note: See “AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices” for how to adjust the registers to

accommodate a 12 pF crystal C_L.

Table 5. Crystal Specifications for 26 to 30 MHz

Parameter

Crystal Frequency

Symbol

Min

Typ

Max

Unit

f

26

27

30

MHz

XTAL

c (supported)*

11

12

13

pF

L

Load Capacitance (on-chip differential)

c (recommended)

17

—

18

—

19

5

pF



L

Crystal Output Capacitance

Equivalent Series Resistance

Crystal Max Drive Level

c

O

r

—

75

—

ESR

d

100

μW

L

*Note: See “AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices” for how to adjust the registers to

accommodate a 12 pF crystal C_L.

6

Rev. 1.4

Si5356B

2

1

Table 6. I C Specifications (SCL,SDA)

Parameter

Symbol

Test Condition

Standard Mode

Fast Mode

Max

0.3 x V

DDI2C

Unit

Min

Max

Min

2

LOW Level

Input Voltage

V

–0.5

0.3 x V

–0.5

V

ILI2C

DDI2

C

2

HIGH Level

Input Voltage

V

0.7 x V

3.63

N/A

0.7 x V

3.63

—

IHI2C

DDI2

DDI2C

C

Hysteresis of

Schmitt Trigger

Inputs

V

N/A

0.1

HYS

2

LOW Level Out- V

put Voltage

(open drain or

open collector)

at 3 mA Sink

Current

V

= 2.5/3.3 V

0

0.4

0

0.4

V

OLI2C

DDI2C

2

V

= 1.8 V

N/A

0.2 x V

DDI2C

Input Current

I

–10

—

10

4

–10

—

10

4

μA

II2C

Capacitance for

each I/O Pin

C

V

= –0.1 to V

DDI2C

pF

II2C

IN

2

I C Bus Time-

Timeout Enabled

25

35

25

35

ms

out

Data rate

100

400

kbps

Notes:

1. Refer to NXP’s UM10204 I²C-bus specification and user manual, Revision 03, for further details:

www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf.

2. Only I²C pullup voltages (VDDI2C) of 1.71 to 3.63 V are supported. Must write register 27[7] = 1 if the I²C bus voltage

is less than 2.5 V to maintain compatibility with the I²C bus standard.

Rev. 1.4

7

Si5356B

Table 7. Thermal Characteristics

Parameter

Symbol

Test Condition

Value

Unit

Thermal Resistance

Junction to Ambient



Still Air

37

°C/W

JA

Thermal Resistance

Junction to Case



Still Air

25

°C/W

JC

1,2,3,4

Table 8. Absolute Maximum Ratings

Parameter

Symbol

Rating

Unit

V

Supply Voltage Range

V

–0.5 to +3.8

–0.5 to 3.8

–0.5 to 1.3

DD

Input Voltage Range (all pins except pins 1,2,5,6)

Input Voltage Range (pins 1,2,5,6)

Output Voltage Range

V

I

V

I2

O

V

–0.5 to V + 0.3

V

DD

o

Junction Temperature

T

–55 to +150

2.5

C

J

ESD Tolerance

HBM

CDM

MM

kV

V

550

175

V

Latch-up Tolerance

LU

JESD78 Compliant

4

o

Soldering Temperature (Pb-free profile)

T

260

C

PEAK

T

20–40

sec

Soldering Temperature Time at T

(Pb-free profile)

P

PEAK

4

Notes:

1. Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operational sections of this data sheet. Exposure to maximum rating

conditions for extended periods may affect device reliability.

2. 24-QFN package is RoHS compliant.

3. For more packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx.

4. The device is compliant with JEDEC J-STD-020.

8

Rev. 1.4

Si5356B

2. Typical Application Circuits

Rev. 1.4

9

Si5356B

Suggested standard 1% resistor values for R

and

SE

3. Functional Description

R

, when using a CMOS source, are given below.

SH

3.1. Input Configuration

CMOS Level

R

()

R

()

SE

SH

The Si5356B input can be driven from either an external

crystal or a reference clock. If the crystal input option is

used, the Si5356B operates as a free-running clock

generator. In this mode of operation the device requires

a low cost fundamental mode crystal connected across

XA and XB as shown in Figure 1. The crystal must meet

the minimum requirements specified in section “1.

1.8 V

2.5 V

3.3 V

1000

1960

3090

1580

3.2. MultiSynth Technology

Electrical Specifications”

.

Given the Si5356B’s

Modern timing architectures require a wide range of

frequencies which are often non-integer related.

Traditional clock architectures address this by using a

combination of single PLL ICs, 4-PLL ICs and discrete

XOs, often at the expense of BOM complexity and

power. The Si5356B uses patented MultiSynth

technology to dramatically simplify timing architectures

by integrating the frequency synthesis capability of 4

phase-locked loops (PLLs) in a single device, greatly

minimizing size and power requirements versus

traditional solutions. Based on a fractional-N PLL, the

heart of the architecture is a low phase noise, high-

frequency VCO. The VCO supplies a high frequency

output clock to the MultiSynth block on each of the four

independent output paths. Each MultiSynth operates as

a high-speed fractional divider with Silicon Laboratories'

proprietary phase error correction to divide down the

VCO clock to the required output frequency with very

low jitter.

frequency flexibility, the same crystal can be reused to

generate any combination of output frequencies.

Custom frequency crystals are not required. The

Si5356B integrates the crystal load capacitors on-chip

to reduce external component count. The crystal should

be placed very close to the device to minimize stray

capacitance. To ensure a stable and accurate output

frequency, the recommended crystal specifications

provided in Table 4 on page 6 must be followed. See

AN360 for additional details regarding crystal

recommendations.

Figure 1. Connecting an XTAL to the Si5356B

The first stage of the MultiSynth architecture is a

fractional-N divider which switches seamlessly between

the two closest integer divider values to produce the

exact output clock frequency with 0 ppm error. To

eliminate phase error generated by this process,

MultiSynth calculates the relative phase difference

between the clock produced by the fractional-N divider

and the desired output clock and dynamically adjusts

the phase to match the ideal clock waveform. This novel

approach makes it possible to generate any output

clock frequency without sacrificing jitter performance.

Based on this architecture, each clock output can

produce any frequency from 1 to 200 MHz.

For synchronous timing applications, the Si5356B can

lock to a 5 to 200 MHz CMOS reference clock. A typical

interface circuit is shown in Figure 2. A series

termination resistor matching the driver’s output

impedance to the impedance of the transmission line is

recommended to reduce reflections.

Figure 2. Interfacing CMOS Reference Clocks

to the Si5356B

Control input signals to SSC_DIS and OEB cannot

exceed 1.2 V yet also need to meet the V and V

IH

IL

specifications outlined in Table 2 on page 4. When

these inputs are driven from CMOS sources, a resistive

attenuator as shown in the Typical Application Circuits

must be used.

10

Rev. 1.4

Si5356B

Figure 3. Silicon Labs' MultiSynth Technology

3.3. Input and Output Frequency Configu- 3.4. Configuring the Si5356B

ration

Refer to the Si5356B Programming Guidelines for

details on how to configure/program the device.

The Si5356B utilizes a single PLL-based architecture,

four independent MultiSynth fractional output dividers,

and a MultiSynth fractional feedback divider such that a

single device provides the clock generation capability of

4 independent PLLs. Unlike competitive multi-PLL

solutions, the Si5356B can generate four unique non-

integer related output frequencies with 0 ppm frequency

error for practically any combination of output

frequencies. In addition, any combination of output

frequencies can be generated from a single reference

frequency without having to change the crystal or

reference clock frequency between frequency

configurations.

3.5. ClockBuilder^™Desktop Software

To simplify device configuration, Silicon Labs provides

ClockBuilder Desktop software, which can operate

standalone or in conjunction with an evaluation board

1

(EVB) . When the software is connected to the EVB,

ClockBuilder will control both the core and I/O buffer

supply voltages to the Si5356B, as well as the entire

clock path within the Si5356B. Clockbuilder Desktop

can also measure the current delivered by the EVB

regulators to each supply voltage of the Si5356B. An

Si5356B configuration can be written to a text file to be

2

used by any system to configure the Si5356B via I C.

Frequency configurations are fully programmable by

writing to device registers using the I C interface. Any

combination of output frequencies ranging from 1 to

200 MHz can be configured on each of the device

outputs.

2

ClockBuilder Desktop can be downloaded from

www.silabs.com/ClockBuilder and runs on Windows XP,

2

Windows Vista, and Windows 7 .

Notes:

1. An Si5338-EVB (evaluation board) is used as the

hardware platform for the Si5356B device. Contact

your local Silicon Labs sales representative to order

this evaluation platform for use with the Si5356B

devices, or submit a request to www.silabs.com/

support/Pages/contacttechnicalsupport.aspx.

2. For Si5356B evaluations, a custom ClockBuilder

configuration file must be installed for proper operation

of the Si5338-EVB. Contact Silicon Labs for access to

the Si5356BClockBuilder configuration file, or submit a

request to www.silabs.com/support/Pages/

contacttechnicalsupport.aspx.

The following equation governs how the output

frequency is calculated.

f_IN N

f_OUT= -----------------

P  M_i

where f is the reference frequency, N is the MultiSynth

IN

feedback divider value, P is the reference divider value,

M is the MultiSynth output divider value and f

is the

i

OUT

resulting output frequency. The MultiSynth output and

feedback dividers are fractional dividers expressed in

terms of an integer and a fraction. The integer portion

has 10-bit resolution and the fractional portion has 30-

bit resolution in both the numerator and denominator,

meaning that any output frequency can be defined

exactly from the input frequency with exact (0 ppm)

frequency synthesis error.

Rev. 1.4

11

Si5356B

inverted. This feature enables each output pair to

operate as a differential CMOS clock. Each of the

output banks can operate from a different VDDO supply

(1.8 V, 2.5 V, 3.3 V), simplifying usage in mixed supply

applications. All clock outputs between 5 and 200 MHz

are in-phase with minimal output-output skew.

3.6. Output Phase Adjustment

The Si5356B has

a

digitally-controlled phase

adjustment feature that allows the user to adjust the

phase of each output clock in relation to the other output

clocks. The phase of each output clock can be adjusted

with an error of <20 ps over a range of ±45 ns. This

feature is available on any clock output that does not

have Spread Spectrum enabled.

The CMOS output driver has a controlled impedance of

about 50 which includes an internal 22  series

resistor. An external series resistor is not needed when

driving 50  traces. If higher impedance traces are used

then a series resistor may be added. A typical

configuration is shown in Figure 4.

3.7. CMOS Output Drivers

The Si5356B has 4 banks of outputs with each bank

comprised of 2 clocks for a total of 8 CMOS outputs per

device. By default, each bank of CMOS output clocks

are in-phase. Alternatively, each output clock can be

Figure 4. CMOS Output Driver Configuration

12

Rev. 1.4

Si5356B

3.8. Jitter Performance

3.9. Status Indicators

The Si5356B provides consistently low jitter for any A logic-high interrupt pin (INTR) is available to indicate

combination of output frequencies. The device a loss of signal (LOS) condition, a PLL loss of lock

leverages a low phase noise single PLL architecture (PLL_LOL) condition, or that the PLL is in process of

and Silicon Laboratories’ patented MultiSynth fractional acquiring lock (SYS_CAL). PLL_LOL is held high when

output divider technology to deliver excellent jitter the input frequency drifts beyond the PLL lock range

performance for any frequency configuration. This level (approximately 5000 ppm). It is held low during all other

of jitter performance is guaranteed across process, times and during a POR or soft reset. SYS_CAL is held

temperature and voltage. The Si5356B provides high during a POR or SOFT reset so that no chattering

superior performance to conventional multi-PLL occurs during the locking process. As shown in

solutions which may suffer from degraded jitter Figure 5, a status register at address 218 is available to

performance depending on frequency plan and the help identify the exact event that caused the interrupt

number of active PLLs.

pin to become active.

Note: It is highly recommended that VDDO0 = 3.3 V when

phase jitter on CLK0 is critical.

Figure 5. Status Register

2

Figure 6 shows a typical connection with the required

pull-up resistor to VDD.

3.9.2. Using the INTR Pin in Systems without I C

The INTR pin also provides a useful function in systems

that require a pin-controlled fault indicator. Pre-setting

the interrupt mask register allows the INTR pin to

become an indicator for a specific event, such as LOS

and/or LOL. Therefore, the INTR pin can be used to

indicate a single fault event or even multiple events.

2

3.9.1. Using the INTR Pin in Systems with I C

The INTR output pin is not latched and should not be a

polled input to an MCU but an edge-triggered interrupt.

An MCU can process an interrupt event by reading the

status register at address 218, and it can be cleared by

writing zeros to the bits that were set. Individual

interrupt bits can be masked by register 6[4:0].

Figure 6. INTR Pin with Required Pull-Up

Rev. 1.4

13

Si5356B

3.10. Output Enable

2

There are two methods of enabling and disabling the output drivers: Pin control, and I C control.

3.10.1. Enabling Outputs Using Pin Control

The Si5356B device provides an Output Enable pin (OEB) as shown in Figure 7. Pulling this pin high will turn all

outputs off. The state of the individual drivers when turned off is controllable. If an individual output is set to always

on, then the OEB pin will not have an effect on that driver. Drive state options and always on are explained in

2

“3.10.2. Enabling Outputs through the I C Interface” .

Figure 7. Output Enable Pin

2

3.10.2. Enabling Outputs through the I C Interface

2

Output enable can be controlled through the I C interface. As shown in Figure 8, register 230[3:0] allows control of

each individual output driver. Register 230[4] controls all drivers at once. When register 230[4] is set to disable all

outputs, the individual output enables will have no effect. Registers 110[7:6], 114[7:6], 118[7:6], and 112[7:6] control

the output disabled state as tri-state, low, high, or always on. If always on is set, that output will always be on

regardless of any other register or chip state.

Figure 8. Output Enable Control Registers

14

Rev. 1.4

Si5356B

3.11. Spread Spectrum

To help reduce electromagnetic interference (EMI), the Si5356B supports spread spectrum modulation. The output

clock frequencies can be modulated to spread energy across a broader range of frequencies, lowering system

EMI. The Si5356B implements spread spectrum using its patented MultiSynth technology to achieve previously

2

unattainable precision in both modulation rate and spreading magnitude as shown in Figure 9. Through I C control,

the Spread Spectrum can be applied to any output clock, any clock frequency, and any spread amount from ±0.1%

to ±2.5% center spread and –0.1% to –5% down spread.

The spreading rate is limited to 30 to 63 kHz.

The Spread Spectrum is generated digitally in the output MultiSynths which means that the Spread Spectrum

parameters are virtually independent of process, voltage and temperature variations. Since the Spread Spectrum

2

is created in the output MultiSynths, through I C each output channel can have independent Spread Spectrum

2

parameters. Without the use of I C (NVM download only) the only supported Spread Spectrum parameters are for

PCI Express compliance composing 100 MHz clock, 31.5 kHz spreading frequency with the choice of the

spreading.

Rev A devices provide native support for both down and center spread. Center spread is supported in rev B

devices by up-shifting the nominal frequency and using down-spread register parameters.

Note: If you currently use center spread on a Revision A and would like to migrate to a Revision B device, you must generate

a new register map using ClockBuilder Desktop. Center spread configurations for Revisions A and B are not compatible.

Figure 9. Configurable Spread Spectrum

Rev. 1.4

15

Si5356B

3.12. Power Supply Considerations

The Si5356B has two core supply voltage pins (V ) and four clock output bank supply voltage pins (V

–

DDOA

DD

V

), enabling the device to be used in mixed supply applications. The Si5356B does not typically require ferrite

DDOD

beads for power supply filtering. The device has extensive on-chip power supply regulation to minimize the impact

of power supply noise on output jitter. Figure 10 shows that the additive phase jitter created when a significant

amount of noise is applied to the device power supply is very small.

Figure 10. Peak-to-Peak Additive Jitter from 100 mV Sine Wave on Supply

16

Rev. 1.4

Si5356B

4. I²C Interface

2

Configuration and operation of the Si5356B is controlled by reading and writing to the RAM space using the I C

interface. The device operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps)

or Fast-Mode (400 kbps) and supports burst data transfer with auto address increments.

2

The I C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 11.

Both the SDA and SCL pins must be connected to the VDD supply via an external pull-up as recommended by the

2

I C specification.

2

Figure 11. I C and Control Signals

The 7-bit device (slave) address of the Si5356B consists of a 6-bit fixed address plus a user-selectable LSB bit as

shown in Figure 12. The LSB bit is selectable using the optional I2C_LSB pin which is available as an

2

programming option for applications that require more than one Si5356B on a single I C bus. Devices without the

2

I2C_LSB pin option have a fixed 7-bit address of 70h (111 0000) as shown in Figure 12. Other custom I C

addresses are also possible.

2

Figure 12. Si5356B I C Slave Address

2

Data is transferred MSB first in 8-bit words as specified by the I C specification. A write command consists of a 7-

bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 13. A write

burst operation is also shown where every additional data word is written using an auto-incremented address.

Rev. 1.4

17

Si5356B

2

Figure 13. I C Write Operation

A read operation is performed in two stages. A data write is used to set the register address, then a data read is

performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in

Figure 14.

2

Figure 14. I C Read Operation

18

Rev. 1.4

Si5356B

AC and DC electrical specifications for the SCL and SDA pins are shown in Table 6. The timing specifications and

2

timing diagram for the I C bus are compatible with the I C-Bus Standard. SDA timeout is supported for

compatibility with SMBus interfaces.

2

The I C bus can be operated at a bus voltage of 1.71 to 3.63 V and is 3.3 V tolerant. If a bus voltage of less than

2

2.5 V is used, register 27[7] = 1 must be written to maintain compatibility with the I C bus standard.

4.1. Custom Device Configurations

2

The Si5356B is fully configurable by writing to internal registers through the I C interface. After each power cycle

the register settings are restored to their factory default values. For applications that require a custom configuration

at power-up, the Si5356B is orderable with a custom default register setting. See "8. Ordering Guide" on page 25

more for details.

Rev. 1.4

19

Si5356B

5. Pin Descriptions

Note: Center pad must be tied to GND for normal operation.

Table 9. Si5356B Pin Descriptions

Pin # Pin Name I/O

Description

1

2

3

XA

I

External Crystal.

If a crystal is used as the device frequency reference, connect it across XA and XB. If

no input clock is used, this pin should be tied to GND.

XB

External Crystal.

If a crystal is used as the device frequency reference, connect it across XA and XB. If

no input clock is used, this pin should be tied to GND.

2

I2C_LSB

I C LSB Address Bit

2

This pin is the least significant bit of the Si5356B I C address allowing up to two

Si5356B devices to occupy the same I C bus.

2

4

CLKIN

I

Single-Ended Input Clock.

If a single-ended clock is used as the device frequency reference, connect it to this pin.

This pin functions as a high-impedance input for CMOS clock signals. The input should

be dc coupled. If a crystal is used as the device frequency reference, this pin should be

tied to GND.

20

Rev. 1.4

Si5356B

Table 9. Si5356B Pin Descriptions (Continued)

Spread Spectrum Disable.

5

6

SSC_DIS

I

This pin allows disabling of the spread spectrum feature on the output clocks. Connect

to 1.2 V to disable spread spectrum on all outputs. Connect to GND to enable spread

spectrum. Note that the maximum voltage level on this pin must not exceed 1.2 V. A

resistor voltage divider is recommended when controlled by a signal greater than 1.2 V.

See the Typical Application Circuit for details.

OEB

Output Enable (Active Low)

This pin allows disabling the output clocks. Connect to 1.2 V to disable all outputs.

Connect to GND to enable all outputs. Note that the maximum voltage level on this pin

must not exceed 1.2 V. A resistor voltage divider is recommended when controlled by a

signal greater than 1.2 V. See the Typical Application Circuit for details.

7

8

VDD

VDD Core Supply Voltage.

The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 ꢀF bypass capacitor should

be located very close to this pin.

INTR

O

Interrupt

This pin functions as an maskable interrupt output.

0 = No interrupt

1 = Interrupt present

This pin is open drain and requires an external >1 k pullup resistor.

9

CLK7

CLK6

O

Output Clock 7.

CMOS output clock. If unused, this pin must be left floating.

10

11

Output Clock 6.

CMOS output clock. If unused, this pin must be left floating.

VDDOD VDD Clock Output Bank D Supply Voltage.

Power supply for clock outputs 6 and 7. May be operated from a 1.8, 2.5, or 3.3 V sup-

ply. A 0.1 ꢀF bypass capacitor should be located very close to this pin. If CLK6/7 are not

used, this pin must be tied to pin 7 and/or pin 24.

2

12

13

SCL

I

I C Serial Clock Input.

CLK5

O

Output Clock 5.

CMOS output clock. If unused, this pin must be left floating.

14

15

CLK4

O

Output Clock 4.

CMOS output clock. If unused, this pin must be left floating.

VDDOC VDD Clock Output Bank C Supply Voltage.

Power supply for clock outputs 4 and 5. May be operated from a 1.8, 2.5 or 3.3 V sup-

ply. A 0.1 ꢀF bypass capacitor should be located very close to this pin. If CLK4/5 are not

used, this pin must be tied to pin 7 and/or pin 24.

16

VDDOB VDD Clock Output Bank B Supply Voltage.

Power supply for clock outputs 2 and 3. May be operated from a 1.8, 2.5, or 3.3 V sup-

ply. A 0.1 ꢀF bypass capacitor should be located very close to this pin. If CLK2/3 are not

used, this pin must be tied to pin 7 and/or pin 24.

17

18

CLK3

CLK2

O

Output Clock 3.

CMOS output clock. If unused, this pin must be left floating.

Output Clock 2.

CMOS output clock. If unused, this pin must be left floating.

Rev. 1.4

21

Si5356B

Table 9. Si5356B Pin Descriptions (Continued)

2

19

20

SDA

VDDOA VDD Clock Output Bank A Supply Voltage.

Power supply for clock outputs 0 and 1. May be operated from a 1.8, 2.5, or 3.3 V sup-

I/O

I C Serial Data.

ply. A 0.1 ꢀF bypass capacitor should be located very close to this pin. If CLK0/1 are not

used, this pin must be tied to pin 7 and/or pin 24.

21

22

23

CLK1

CLK0

GND

O

Output Clock 1.

CMOS output clock. If unused, this pin must be left floating.

Output Clock 0.

CMOS output clock. If unused, this pin must be left floating.

GND Ground.

Must be connected to system ground. Minimize the ground path impedance for optimal

performance of the device.

24

VDD

GND

VDD Core Supply Voltage.

The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 ꢀF bypass capacitor should

be located very close to this pin.

GND

PAD

GND Ground Pad.

This is the large pad in the center of the package. The device will not function unless the

ground pad is properly connected to a ground plane on the PCB. See "7. Recom-

mended PCB Land Pattern" on page 24 for the PCB pad sizes and ground via require-

ments.

22

Rev. 1.4

Si5356B

6. Package Outline: 24-Lead QFN

Figure 15. 24-Lead Quad Flat No-Lead (QFN)

Table 10. Package Dimensions

Dimension

Min

Nom

Max

A

A1

b

0.80

0.00

0.18

0.85

0.02

0.90

0.05

0.30

0.25

D

4.00 BSC.

2.50

D2

e

2.35

2.65

0.50 BSC.

4.00 BSC.

2.50

E

E2

L

2.35

0.30

2.65

0.50

0.40

aaa

bbb

ccc

ddd

eee

0.10

0.08

0.10

0.05

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body

Components.

5. For more packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx.

Rev. 1.4

23

Si5356B

7. Recommended PCB Land Pattern

Table 11. PCB Land Pattern

Dimension

Min

Nom

Max

2.60

0.30

0.85

P1

P2

X1

Y1

C1

C2

E

2.50

0.20

0.75

2.55

0.25

0.80

3.90

0.50

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

4. Connect the center ground pad to a ground plane with no less than five vias. These 5 vias should have a length of no more

than 20 mils to the ground plane. Via drill size should be no smaller than 10 mils. A longer distance to the ground plane is

allowed if more vias are used to keep the inductance from increasing.

Solder Mask Design

5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60

μm minimum, all the way around the pad.

Stencil Design

6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste

release.

7. The stencil thickness should be 0.125 mm (5 mils).

8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.

9. A 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad.

Card Assembly

10. A No-Clean, Type-3 solder paste is recommended.

11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

24

Rev. 1.4

Si5356B

8. Ordering Guide

8.1. Custom Part Numbers

The Si5356B includes the following part numbers with start-up configurations as listed inTable 12. Refer to the

Si5365B Programming Guidelines document for additional Si5365B part numbers and validated configurations.

Table 12. Customer Part Numbers

Custom Part

Number

Input

CLK0 CLK1

CLK2

CLK3 CLK4 CLK5

CLK6

CLK7

Si5356B-B00322-GM 25 MHz 25 MHz 25 MHz 33.333 MHz Unused 48 MHz Unused 27.648 MHz Unused

XTAL

2.5 V

3.3 V

CMOS

50 MHz

3.3 V

XA/XB CMOS CMOS

CMOS

Si5356B-B01139-GM 25 MHz 50 MHz Unused

Unused 48 MHz Unused 27.648 MHz Unused

XTAL

3.3 V

XA/XB CMOS

CMOS

Rev. 1.4

25

Si5356B

9. Top Marking

9.1. Si5356B Top Marking

9.2. Top Marking Explanation

Line

Line 1

Line 2

Characters

Description

Si5356

Bxxxxx

Base part number.

2

B = 200 MHz, CMOS, I C programmable clock generator series.

xxxxx = Optional NVM code for custom factory-programmed devices.

These 5 characters are not included for standard, factory default config-

ured devices. IBM NVM configuration code #1=00322.

See Section “8.1. Custom Part Numbers” for configuration details.

Line 3

Line 4

RTTTTT

R = Product revision.

TTTTT = Manufacturing trace code.

Circle with 0.5 mm

Pin 1 indicator.

diameter; left-justified

YYWW

YY = Year.

WW = Work week

Characters correspond to the year and work week of package assembly.

26

Rev. 1.4

Si5356B

10. Device Errata

Please visit www.silabs.com to access the device errata document.

Rev. 1.4

27

Si5356B

Revision 1.0 to Revision 1.1

DOCUMENT CHANGE LIST

Revision 0.1 to Revision 0.2

 Removed down spectrum errata that has been

corrected in revision B.

 Updated crystal specifications to include crystal

 Updated ordering information to refer to revision B

frequencies of 19 to 30 MHz.

silicon.

 Updated section “3.4. Configuring the Si5356B” .

 Removed section 3.10 Reset Options.

 Updated top marking explanation in Section 9.1.

 Added further explanation to describe revision-

specific behavior of center spread spectrum in

Section 3.11.

 Moved section 4.2 Spread Spectrum to section

“3.11. Spread Spectrum” .

 Moved section 4.3 Power Supply Considerations to

section

Revision 1.1 to Revision 1.2

 Added link to errata document.

“3.12. Power Supply Considerations” .

 Added section “9. Top Marking” .

Revision 1.3 to Revision 1.4

 Removed MSL rating.

Revision 0.2 to Revision 0.3

 Added Si5356B-A01139-GM to Section 8.1 as a new

validated part number conforming to data sheet

specifications.

 Corrected CMOS output clock t /t time (20 to 80%,

R F

15 pF load) from 1.7 ns (max) to 2.0 ns (max) to

better reflect characterization data.

 Clarified crystal specifications in Tables 6 and 7 and

added reference to AN360.

 Corrected Figure 5. Status Registers to show the

correct position of LOS_XTAL and LOS_CLK..

 Removed reference to the Si5338K/L/M in the output

enable control section.

 Updated application circuits to make reference to the

Si5356B.

Revision 0.3 to Revision 1.0

 Updated Table 2, “DC Characteristics,” on page 4.

Corrected I_DDOXfrom "—" (typ) to 6 mA (typ), and

28 mA (max) to 9 mA (max).

Corrected R_INfrom 20 k (min) to 20 k (typ).

 Updated Table 3, “AC Characteristics,” on page 5.

Input clock T_R/T_Ffrom 2 ns (max) to 2.3 ns (max).

Corrected C_Lfrom 15 pF (typ) to 15 pF (max).

Corrected F_RESfrom 0 ppm (max) to 1 ppb (max).

Added Interrupt Status Timing.

 Added soldering temperature time T

to Table 8.

PEAK

 Corrected references to V and V in Section 3.1.

IH

IL

 Removed output-output skew reference from text of

Section 3.7 (see Table 3—AC Characteristics).

 Clarified status alarm register info in Section 3.9.1.

 Removed erroneous reference to ZDB mode.

28

Rev. 1.4

ClockBuilder Pro

One-click access to Timing tools,

documentation, software, source

code libraries & more. Available for

Windows and iOS (CBGo only).

www.silabs.com/CBPro

Timing Portfolio

www.silabs.com/timing

SW/HW

www.silabs.com/CBPro

Quality

www.silabs.com/quality

Support and Community

community.silabs.com

Disclaimer

Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or

intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"

parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes

without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included

information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted

hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of

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型号:	SI5356B-A01139-GM
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Obsolete
IHS 制造商：	SILICON LABORATORIES INC
零件包装代码：	QFN
包装说明：	4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24
针数：	24
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.71
其他特性：	ALSO OPERATES 2.5 V AT 25 MHZ
JESD-30 代码：	S-XQCC-N24
长度：	4 mm
端子数量：	24
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出时钟频率：	200 MHz
封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN
封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED
主时钟/晶体标称频率：	200 MHz
座面最大高度：	0.9 mm
最大供电电压：	3.63 V
最小供电电压：	2.97 V
标称供电电压：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

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