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产品型号SN65HVD21DR的概述

芯片SN65HVD21DR的概述 SN65HVD21DR是一款由德州仪器(Texas Instruments,TI)设计和生产的高性能、低功耗的CAN(Controller Area Network)收发器。由于其优良的电气特性和稳定的性能,SN65HVD21DR广泛应用于工业控制、汽车电子、智能通信等领域。 在汽车及工业网络中,CAN总线是一种重要的通信协议,旨在实现不同控制器之间的高效、可靠通信。SN65HVD21DR具有较高的抗干扰能力,适合在噪声较大的环境中运行,其设计符合ISO 11898标准,适合长距离、高速的数据传输。 芯片SN65HVD21DR的详细参数 SN65HVD21DR具备多项重要参数: - 工作电压范围:4.5V到5.5V - 静态电流:最大值为1 mA(典型值) - 传输速率:最大可达1 Mbps - 输入电压范围:-0.3V到5.5V - CAN总线电压范...

产品型号SN65HVD21DR的Datasheet PDF文件预览

ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢀꢁꢂ ꢃꢄ ꢅꢆ ꢇꢊ  
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢇ ꢉ ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢋ ꢉ ꢀꢁꢂ ꢃꢄ ꢅꢆ ꢇꢌ  
www.ti.com  
SLLS552D − DECEMBER 2002 − REVISED APRIL 2005  
FEATURES  
DESCRIPTION  
D
D
Common-Mode Voltage Range (−20 V to 25 V)  
More Than Doubles TIA/EIA-485 Requirement  
The transceivers in the HVD2x family offer performance  
far exceeding typical RS−485 devices. In addition to  
meeting all requirements of the TIA/EIA−485−A standard,  
the HVD2x family operates over an extended range of  
common-mode voltage, and has features such as high  
ESD protection, wide receiver hysteresis, and failsafe  
operation. This family of devices is ideally suited for  
long-cable networks, and other applications where the  
environment is too harsh for ordinary transceivers.  
Receiver Equalization Extends Cable Length,  
Signaling Rate (HVD23, HVD24)  
D
D
D
Reduced Unit-Load for up to 256 Nodes  
Bus I/O Protection to Over 16-kV HBM  
Failsafe Receiver for Open-Circuit,  
Short-Circuit and Idle-Bus Conditions  
D
Low Standby Supply Current 1-µA Max  
These devices are designed for bidirectional data  
transmission on multipoint twisted-pair cables. Example  
applications are digital motor controllers, remote sensors  
and terminals, industrial process control, security stations,  
and environmental control systems.  
D
More Than 100 mV Receiver Hysteresis  
APPLICATIONS  
D
Long Cable Solutions  
Factory Automation  
Security Networks  
Building HVAC  
These devices combine a 3-state differential driver and a  
differential receiver, which operate from a single 5-V power  
supply. The driver differential outputs and the receiver  
differential inputs are connected internally to form a  
differential bus port that offers minimum loading to the bus.  
This port features an extended common-mode voltage  
range making the device suitable for multipoint  
applications over long cable runs.  
D
Severe Electrical Environments  
Electrical Power Inverters  
Industrial Drives  
Avionics  
HVD2x APPLICATION SPACE  
HVD2x Devices Operate Over a Wider Common-Mode Voltage Range  
100  
−20 V  
+25 V  
HVD23  
HVD20  
SUPER−485  
RS−485  
10  
HVD24  
HVD21  
1
−7 V  
−20 V −15 V −10 V −5 V  
+12 V  
15 V  
HVD22  
0
5 V  
10 V  
20 V  
25 V  
0.1  
10  
100  
Cable Length − m  
1000  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢘꢔ ꢑ ꢆꢙ ꢐ ꢏꢗ ꢑꢁ ꢆ ꢖꢏꢖ ꢚꢛ ꢜꢝ ꢞ ꢟꢠ ꢡꢚꢝꢛ ꢚꢢ ꢣꢤ ꢞ ꢞ ꢥꢛꢡ ꢠꢢ ꢝꢜ ꢦꢤꢧ ꢨꢚꢣ ꢠꢡꢚ ꢝꢛ ꢩꢠ ꢡꢥꢪ ꢘꢞ ꢝꢩꢤ ꢣꢡꢢ  
ꢣ ꢝꢛ ꢜꢝꢞ ꢟ ꢡꢝ ꢢ ꢦꢥ ꢣ ꢚ ꢜꢚ ꢣ ꢠ ꢡꢚ ꢝꢛꢢ ꢦ ꢥꢞ ꢡꢫꢥ ꢡꢥ ꢞ ꢟꢢ ꢝꢜ ꢏꢥꢬ ꢠꢢ ꢗꢛꢢ ꢡꢞ ꢤꢟ ꢥꢛꢡ ꢢ ꢢꢡ ꢠꢛꢩ ꢠꢞ ꢩ ꢭ ꢠꢞ ꢞ ꢠ ꢛꢡꢮꢪ  
ꢘꢞ ꢝ ꢩꢤꢣ ꢡ ꢚꢝ ꢛ ꢦꢞ ꢝ ꢣ ꢥ ꢢ ꢢ ꢚꢛ ꢯ ꢩꢝ ꢥ ꢢ ꢛꢝꢡ ꢛꢥ ꢣꢥ ꢢꢢ ꢠꢞ ꢚꢨ ꢮ ꢚꢛꢣ ꢨꢤꢩ ꢥ ꢡꢥ ꢢꢡꢚ ꢛꢯ ꢝꢜ ꢠꢨ ꢨ ꢦꢠ ꢞ ꢠꢟ ꢥꢡꢥ ꢞ ꢢꢪ  
Copyright 2002 − 2003, Texas Instruments Incorporated  
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢊ  
ꢇꢉ  
www.ti.com  
SLLS552D − DECEMBER 2002 − REVISED APRIL 2005  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during  
storage or handling to prevent electrostatic damage to the MOS gates.  
DESCRIPTION (continued)  
The ‘HVD20 provides high signaling rate (up to 25 Mbps) for interconnecting networks of up to 64 nodes.  
The ‘HVD21 allows up to 256 connected nodes at moderate data rates (up to 5 Mbps). The driver output slew rate is  
controlled to provide reliable switching with shaped transitions which reduce high-frequency noise emissions.  
The ‘HVD22 has controlled driver output slew rate for low radiated noise in emission-sensitive applications and for  
improved signal quality with long stubs. Up to 256 ‘HVD22 nodes can be connected at signaling rates up to 500 kbps.  
The ‘HVD23 implements receiver equalization technology for improved jitter performance on differential bus applications  
with data rates up to 25 Mbps at cable lengths up to 160 meters.  
The ‘HVD24 implements receiver equalization technology for improved jitter performance on differential bus applications  
with data rates in the range of 1 Mbps to 10 Mbps at cable lengths up to 1000 meters.  
The receivers also include a failsafe circuit that provides a high-level output within 250 microseconds after loss of the input  
signal. The most common causes of signal loss are disconnected cables, shorted lines, or the absence of any active  
transmitters on the bus. This feature prevents noise from being received as valid data under these fault conditions. This  
feature may also be used for Wired-Or bus signaling.  
The SN65HVD2X devices are characterized for operation over the temperature range of −40°C to 85°C.  
PRODUCT SELECTION GUIDE  
(1)  
PART NUMBERS  
CABLE LENGTH AND SIGNALING RATE  
NODES  
MARKING  
D: VP20  
SN65HVD20  
Up to 50 m at 25 Mbps  
Up to 64  
P: 65HVD20  
D: VP21  
P: 65HVD21  
SN65HVD21  
SN65HVD22  
SN65HVD23  
SN65HVD24  
Up to 150 m at 5 Mbps (with slew rate limit)  
Up to1200 m at 500 kbps (with slew rate limit)  
Up to 160 m at 25 Mbps (with receiver equalization)  
Up to 500 m at 3 Mbps (with receiver equalization)  
Up to 256  
Up to 256  
Up to 64  
D: VP22  
P: 65HVD22  
D: VP23  
P: 65HVD23  
D: VP24  
P: 65HVD24  
Up to 256  
(1)  
Distance and signaling rate predictions based upon Belden 3105A cable and 15% eye pattern jitter.  
AVAILABLE OPTIONS  
(1)  
PLASTIC THROUGH-HOLE  
P−PACKAGE  
PLASTIC SMALL-OUTLINE  
D−PACKAGE  
(JEDEC MS-001)  
(JEDEC MS-012)  
SN65HVD20P  
SN65HVD21P  
SN65HVD22P  
SN65HVD23P  
SN65HVD24P  
SN65HVD20D  
SN65HVD21D  
SN65HVD22D  
SN65HVD23D  
SN65HVD24D  
(1)  
Add R suffix for taped and reeled carriers.  
2
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005  
DRIVER FUNCTION TABLE  
HVD20, HVD21, HVD22  
HVD23, HVD24  
INPUT  
ENABLE  
OUTPUTS  
INPUT  
ENABLE  
OUTPUTS  
D
DE  
A
B
L
D
DE  
A
B
L
H
H
H
L
H
H
H
L
Z
Z
L
L
X
H
L
H
Z
Z
L
L
X
H
L
H
Z
Z
H
Z
Z
H
X
OPEN  
H
X
OPEN  
H
OPEN  
OPEN  
H = high level, L= low level, X = don’t care, Z = high impedance (off), ? = indeterminate  
RECEIVER FUNCTION TABLE  
DIFFERENTIAL INPUT  
= (V – V )  
ENABLE  
OUTPUT  
V
RE  
R
ID  
A
B
0.2 V V  
L
H
ID  
−0.2 V < V < 0.2 V  
L
H (see Note A)  
ID  
V
ID  
−0.2 V  
L
L
Z
X
X
H
OPEN  
Z
Open circuit  
Short Circuit  
L
L
L
H
H
H
Idle (terminated) bus  
H = high level, L= low level, Z = high impedance (off)  
NOTE A: If the differential input V remains within the transition range for  
ID  
more than 250 µs, the integrated failsafe circuitry detects a bus  
fault, and set the receiver output to a high state. See Figure 15.  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range unless otherwise noted  
(1)  
SN65HVD2X  
−0.5 V to 7 V  
−27 V to 27 V  
−60 V to 60 V  
(2)  
Supply voltage , V  
CC  
Voltage at any bus I/O terminal  
Voltage input, transient pulse, A and B, (through 100 , see Figure 16)  
Voltage input at any D, DE or RE terminal  
−0.5 V to V + 0.5 V  
CC  
Receiver output current, I  
−10 mA to 10 mA  
O
A, B, GND  
All pins  
16 kV  
(3)  
Human Body Model  
5 kV  
Electrostatic discharge  
(4)  
Charged-Device Model  
All pins  
1.5 kV  
(5)  
Machine Model  
All pins  
200 V  
See Power Dissipation Rating Table  
150°C  
Continuous total power dissipation  
Junction temperature, T  
J
(1)  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.  
Tested in accordance with JEDEC Standard 22, Test Method A114-A.  
(2)  
(3)  
(4)  
(5)  
Tested in accordance with JEDEC Standard 22, Test Method C101.  
Tested in accordance with JEDEC Standard 22, Test Method A115-A.  
3
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POWER DISSIPATION RATINGS  
(3)  
DERATING FACTOR  
CIRCUIT BOARD  
T
A
25°C  
T
= 70°C  
T = 85°C  
A
POWER RATING  
A
PACKAGE  
MODEL  
POWER RATING  
ABOVE T = 25°C  
POWER RATING  
A
(1)  
Low-K  
577 mW  
4.62 mW/°C  
7.3 mW/°C  
7.87 mW/°C  
10.8 mW/°C  
369 mW  
300 mW  
D
P
(2)  
High-K  
913 mW  
584 mW  
474 mW  
(1)  
Low-K  
984 mW  
630 mW  
512 mW  
(2)  
High-K  
1344 mW  
860 mW  
700 mW  
(1)  
(2)  
(3)  
In accordance with the Low-K thermal metric definitions of EIA/JESD51−3.  
In accordance with the High-K thermal metric definitions of EIA/JESD51−7.  
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.  
THERMAL CHARACTERISTICS  
PARAMETER  
TEST CONDITIONS  
VALUE UNITS  
D
86.2  
56  
θ
θ
Junction-to-board thermal resistance  
Junction-to-case thermal resistance  
JB  
P
°C/W  
D
47.1  
JC  
P
54  
HVD20  
HVD21  
HVD22  
HVD23  
HVD24  
HVD20  
HVD21  
HVD22  
HVD23  
HVD24  
25 Mbps  
5 Mbps  
295  
260  
233  
302  
267  
V
R
C
= 5 V, T = 25°C,  
CC  
L
L
J
= 54 , C = 50 pF (driver),  
L
= 15 pF (receiver),  
500 kbps  
25 Mbps  
5 Mbps  
Typical  
50% Duty cycle square-wave signal,  
Driver and receiver enabled  
P
D
Device power dissipation  
mW  
25 Mbps  
5 Mbps  
408  
V
C
= 5.5 V, T = 125°C,R = 54 ,  
J L  
342  
300  
417  
352  
CC  
= 50 pF, C = 15 pF (receiver),  
L
L
500 kbps  
25 Mbps  
5 Mbps  
Worst case  
50% Duty cycle square-wave signal,  
Driver and receiver enabled  
T
SD  
Thermal shut-down junction temperature  
170  
°C  
RECOMMENDED OPERATING CONDITIONS  
MIN NOM  
MAX UNIT  
Supply voltage, V  
CC  
4.5  
−20  
2
5
5.5  
25  
V
V
Voltage at any bus I/O terminal  
A, B  
High-level input voltage, V  
V
IH  
CC  
0.8  
D, DE, RE  
V
V
Low-level input voltage, V  
0
IL  
Differential input voltage, V  
A with respect to B  
Driver  
−25  
−110  
−8  
25  
ID  
110  
8
Output current  
mA  
Receiver  
(1)  
Operating free-air temperature, T  
−40  
−40  
85  
°C  
°C  
A
Junction temperature, T  
130  
J
(1)  
Maximum free-air temperature operation is allowed as long as the device recommended junction temperature is not exceeded.  
4
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005  
DRIVER ELECTRICAL CHARACTERISTICS  
over recommended operating conditions (unless otherwise noted)  
(1)  
(1)  
MIN TYP  
PARAMETER  
TEST CONDITIONS  
I = −18 mA  
MAX  
UNIT  
V
V
IK  
Input clamp voltage  
−1.5  
0
0.75  
I
V
O
Open-circuit output voltage  
A or B, No load  
V
CC  
V
CC  
V
No load (open circuit)  
3.3  
1.8  
1.8  
4.2  
2.5  
Steady-state differential output voltage  
magnitude  
R = 54 ,  
L
See Figure 1  
V  
OD(SS)  
V
With common-mode loading, See Figure 2  
See Figure 1 and Figure 3  
See Figure 1  
Change in steady-state differential output  
voltage between logic states  
∆|V  
|
−0.1  
2.1  
0.1  
2.9  
0.1  
V
V
V
OD(SS)  
V
Steady-state common-mode output voltage  
Change in steady-state common-mode output  
2.5  
OC(SS)  
V  
OC(SS)  
See Figure 1 and Figure 4  
−0.1  
voltage, V  
OC(H)  
– V  
OC(L)  
Peak-to-peak common-mode output voltage,  
– V  
R = 54 , C = 50 pF,  
L L  
See Figure 1 and Figure 4  
V
0.35  
V
OC(PP)  
V
OC(MAX)  
OC(MIN)  
V
Differential output voltage over and under shoot R = 54 , C = 50 pF, See Figure 5  
10%  
100  
OD(RING)  
L
L
I
I
Input current  
D, DE  
−100  
µA  
I
Output current with power off  
High impedance state output current  
Short-circuit output current  
Differential output capacitance  
V
< = 2.5 V  
O(OFF)  
CC  
DE at 0 V  
See receiver line input  
current  
I
OZ  
I
V
O
= −20 V to 25 V,  
See Figure 9  
−250  
See receiver C  
250  
mA  
OS  
C
OD  
(1)  
I
All typical values are at V  
CC  
= 5 V and 25°C.  
DRIVER SWITCHING CHARACTERISTICS  
over recommended operating conditions (unless otherwise noted)  
(1)  
PARAMETER  
TEST CONDITIONS  
MIN TYP  
MAX  
20  
UNIT  
HVD20, HVD23  
HVD21, HVD24  
HVD22  
6
10  
32  
R = 54 ,  
C = 50 pF,  
See Figure 3  
t
t
t
t
t
t
t
t
Differential output propagation delay, low-to- high  
Differential output propagation delay, high-to-low  
Differential output rise time  
L
L
PLH  
PHL  
r
20  
60  
ns  
160  
2
280  
6
500  
12  
HVD20, HVD23  
HVD21, HVD24  
HVD22  
R = 54 ,  
C = 50 pF,  
See Figure 3  
L
L
20  
40  
60  
ns  
ns  
ns  
Differential output fall time  
f
200  
400  
600  
40  
HVD20, HVD23  
HVD21, HVD24  
HVD22  
Propagation delay time, high-impedance-to-high-level output  
Propagation delay time, high-level-output-to-high-impedance  
Propagation delay time, high-impedance-to-low-level output  
Propagation delay time, low-level-output-to-high-impedance  
PZH  
PHZ  
PZL  
PLZ  
RE at 0 V,  
See Figure 6  
100  
300  
40  
HVD20, HVD23  
HVD21, HVD24  
HVD22  
RE at 0 V,  
See Figure 7  
100  
300  
2
t
t
Time from an active differential output to standby  
µs  
µs  
d(standby)  
d(wake)  
RE at V , See Figure 8  
CC  
Wake-up time from standby to an active differential output  
8
HVD20, HVD23  
HVD21, HVD24  
HVD22  
2
t
Pulse skew | t  
– t  
|
6
ns  
sk(p)  
PLH PHL  
50  
(1)  
All typical values are at V  
CC  
= 5 V and 25°C.  
5
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RECEIVER ELECTRICAL CHARACTERISTICS  
over recommended operating conditions  
(1)  
PARAMETER  
TEST CONDITIONS  
= 2.4 V, I = −8 mA  
MIN TYP  
MAX  
UNIT  
V
IT(+)  
Positive-going differential input voltage threshold  
Negative-going differential input voltage threshold  
V
O
60  
200  
O
See Figure 10  
mV  
mV  
mV  
V
IT(−)  
V
O
= 0.4 V, I = 8 mA  
−200  
100  
40  
−60  
130  
O
V
HYS  
Hysteresis voltage (V  
IT+  
− V )  
IT−  
V
CM  
V
CM  
V
CM  
V
CM  
= −7 V to 12 V  
= −20 V to 25 V  
= −7 V to 12 V  
= −20 V to 25 V  
120  
200  
250  
−40  
Positive-going differential input failsafe voltage  
threshold  
V
IT(F+)  
See Figure 15  
See Figure 15  
120  
−200  
−250  
−1.5  
4
−120  
−120  
Negative-going differential input failsafe voltage  
threshold  
V
IT(F−)  
mV  
V
IK  
Input clamp voltage  
I = −18 mA  
I
V
V
V
V
OH  
High-level output voltage  
Low-level output voltage  
V
ID  
= 200 mV, I = −8 mA, See Figure 11  
OH  
V
OL  
V
= −200 mV, I  
= 8 mA, See Figure 11  
HVD20, HVD23  
0.4  
500  
ID OL  
−400  
−100  
−800  
V = −7 to 12 V,  
I
Other input = 0 V  
HVD21, HVD22, HVD24  
HVD20, HVD23  
125  
I
Bus input current (power on or power off)  
µA  
I(BUS)  
1000  
250  
V = −20 to 25 V,  
I
Other input = 0 V  
HVD21, HVD22, HVD24 −200  
I
Input current  
RE  
−100  
24  
100  
µA  
kΩ  
pF  
I
HVD20, 23  
HVD21, 22, 24  
R
Input resistance  
I
96  
6
C
Differential input capacitance  
V
ID  
= 0.5 + 0.4 sine (2π x 1.5 x 10 t)  
20  
ID  
(1)  
All typical values are at 25°C.  
RECEIVER SWITCHING CHARACTERISTICS  
over recommended operating conditions  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
16  
MAX  
35  
UNIT  
t
Propagation delay time, low-to-high level output  
Propagation delay time, high-to-low level output  
Receiver output rise time  
HVD20, HVD23  
See Figure 11  
PLH  
ns  
t
t
t
t
t
t
t
t
HVD21, HVD22, HVD24  
25  
50  
PHL  
r
See Figure 11  
See Figure 12  
See Figure 13  
2
4
ns  
ns  
ns  
Receiver output fall time  
f
Receiver output enable time to high level  
Receiver output disable time from high level  
Receiver output enable time to low level  
Receiver output disable time from low level  
Time from an active receiver output to standby  
90  
16  
90  
16  
120  
35  
120  
35  
2
PZH  
PHZ  
PZL  
PLZ  
r(standby)  
Wake-up time from standby to an active receiver  
output  
See Figure 14, DE at 0 V  
µs  
t
8
r(wake)  
t
t
t
Pulse skew | t  
– t  
|
5
350  
50  
ns  
µs  
ns  
sk(p)  
PLH PHL  
Delay time, bus fail to failsafe set  
250  
p(set)  
p(reset)  
See Figure 15, pulse rate = 1 kHz  
Delay time, bus recovery to failsafe reset  
6
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005  
(1)  
RECEIVER EQUALIZATION CHARACTERISTICS  
over recommended operating conditions  
(2)  
PARAMETER  
TEST CONDITIONS  
MIN TYP  
MAX  
UNIT  
0 m  
HVD23  
HVD20  
HVD23  
HVD20  
HVD23  
HVD20  
HVD23  
HVD20  
HVD23  
HVD20  
HVD23  
HVD20  
HVD23  
HVD21  
HVD24  
HVD20  
HVD21  
HVD23  
HVD24  
HVD21  
HVD24  
2
6
100 m  
150 m  
200 m  
200 m  
3
15  
4
25 Mbps  
27  
8
22  
8
34  
15  
49  
27  
Pseudo-random NRZ code with a bit  
pattern length of 2 − 1 ,  
Beldon 3105A cable, See Figure 27  
10 Mbps 250 m  
300 m  
Peak-to-peak  
eye-pattern jitter  
16  
t
ns  
j(pp)  
128  
18  
5 Mbps  
3 Mbps  
1 Mbps  
500 m  
500 m  
93  
103  
90  
16  
216  
62  
1000 m  
(1)  
(2)  
The HVD20 and HVD21 do not have receiver equalization, but are specified for comparison.  
All typical values are at V = 5 V, and temperature = 25°C.  
CC  
SUPPLY CURRENT  
over recommended operating conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
9
UNIT  
HVD20  
HVD21  
HVD22  
HVD23  
HVD24  
HVD20  
HVD21  
HVD22  
HVD23  
HVD24  
HVD20  
HVD21  
HVD22  
HVD23  
HVD24  
6
8
12  
9
Driver enabled (DE at V ), Receiver enabled (RE at 0 V)  
CC  
6
mA  
No load, V = 0 V or V  
I
CC  
7
11  
14  
8
10  
5
7
11  
8
Driver enabled (DE at V ), Receiver disabled (RE at V  
)
CC CC  
5
mA  
No load, V = 0 V or V  
CC  
I
I
Supply current  
5
9
CC  
8
12  
7
4
5
8
Driver disabled (DE at 0 V), Receiver enabled (RE at 0 V)  
No load  
4
7
mA  
4.5  
5.5  
9
10  
Driver disabled (DE at 0 V), Receiver disabled (RE at V  
D open  
)
All  
HVD2x  
CC  
1
µA  
7
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005  
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS  
RE Inputs  
D Inputs (HVD20, 21, 22)  
DE Input  
D Inputs (HVD23, 24)  
V
CC  
V
CC  
100 kΩ  
1 kΩ  
1 kΩ  
Input  
Input  
100 kΩ  
9 V  
9 V  
A Input  
B Input  
V
CC  
V
CC  
R1  
R1  
R3  
R3  
Input  
Input  
29 V  
29 V  
R2  
R2  
29 V  
A and B Outputs  
R Output  
V
CC  
V
CC  
5 Ω  
Output  
9 V  
Output  
29 V  
R1/R2  
R3  
9 kΩ  
36 kΩ  
45 kΩ  
180 kΩ  
HVD20, 23  
HVD21, 22, 24  
8
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005  
PARAMETER MEASUREMENT INFORMATION  
NOTES:  
Test load capacitance includes probe and jig capacitance (unless otherwise specified).  
Signal generator characteristics: rise and fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle, Z = 50 (unless otherwise specified)  
o
I
O
O
27 Ω  
27 Ω  
I
I
V
OD  
50 pF  
0 V or 3 V  
I
V
OC  
Figure 1. Driver Test Circuit, V  
and V  
Without Common-Mode Loading  
OC  
OD  
375 Ω  
I
I
O
V
= −20 V to 25 V  
TEST  
V
OD  
60 Ω  
375 Ω  
0 V or 3 V  
O
V
TEST  
Figure 2. Driver Test Circuit, V  
With Common-Mode Loading  
OD  
3 V  
0 V  
INPUT  
t
1.5 V  
1.5 V  
V
OD  
R
L
= 54 Ω  
t
PLH  
PHL  
C
L
= 50 pF  
V
OD(H)  
OD(L)  
Signal  
Generator  
90%  
10%  
50 Ω  
0 V  
OUTPUT  
V
t
r
t
f
Figure 3. Driver Switching Test Circuit and Waveforms  
27 Ω  
A
B
V
A
3.25 V  
1.75 V  
D
27 Ω  
V
B
Signal  
Generator  
50 Ω  
V
V
OC  
V  
OC(PP)  
OC(SS)  
50 pF  
V
OC  
Figure 4. Driver V  
OC  
Test Circuit and Waveforms  
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005  
V
OD(SS)  
V
OD(RING)  
V
OD(PP)  
0 V Differential  
V
OD(RING)  
V
OD(SS)  
:
NOTE  
V
V
is measured at four points on the output waveform, corresponding to overshoot and undershoot from the  
OD(RING)  
and V  
steady state values.  
OD(H)  
OD(L)  
Figure 5. V  
Waveform and Definitions  
OD(RING)  
A
S1  
3 V  
0 V  
Output  
D
0 V or 3 V  
1.5 V 1.5 V  
B
DE  
t
3 V if Testing A Output  
0 V if Testing B Output  
0.5 V  
C
= 50 pF  
L
PZH  
R
= 110 Ω  
L
DE  
V
OH  
Output  
Signal  
Generator  
2.5 V  
50 Ω  
V
Off  
0
t
PHZ  
Figure 6. Driver Enable/Disable Test, High Output  
5 V  
R
L
= 110 Ω  
S1  
3 V  
D
Output  
0 V or 3 V  
1.5 V 1.5 V  
DE  
t
0 V if Testing A Output  
3 V if Testing B Output  
0 V  
5 V  
C
L
= 50 pF  
PZL  
t
DE  
PLZ  
Output  
Signal  
Generator  
2.5 V  
V
OL  
50 Ω  
0.5 V  
Figure 7. Driver Enable/Disable Test, Low Output  
3 V  
1.5 V  
DE  
A
B
0 V  
D
C
L
= 50 pF  
V
OD  
R
L
= 54 Ω  
0 V or 3 V  
t
d(Wake)  
t
d(Standby)  
1.5 V  
V  
OD  
DE  
0.2 V  
Signal  
Generator  
50 Ω  
Figure 8. Driver Standby/Wake Test Circuit and Waveforms  
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005  
I
OS  
V
O
Voltage  
Source  
Figure 9. Driver Short-Circuit Test  
I
O
V
ID  
V
O
Figure 10. Receiver DC Parameter Definitions  
Signal  
Generator  
50 Ω  
Input B  
V
ID  
1.5 V  
0 V  
A
B
50%  
I
O
Input A  
t
R
t
PHL  
PLH  
V
C
= 15 pF  
O
V
OH  
Signal  
Generator  
L
90%  
50 Ω  
Output  
1.5 V  
10%  
V
OL  
t
r
t
f
Figure 11. Receiver Switching Test Circuit and Waveforms  
D
V
V
CC  
DE  
CC  
A
54 Ω  
B
3 V  
0 V  
1 kΩ  
R
RE  
1.5 V  
0 V  
C
L
= 15 pF  
RE  
t
t
PHZ  
PZH  
Signal  
Generator  
V
OH  
−0.5 V  
50 Ω  
V
OH  
1.5 V  
R
GND  
Figure 12. Receiver Enable Test Circuit and Waveforms, Data Output High  
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005  
D
0 V  
DE  
V
CC  
A
54 Ω  
B
3 V  
0 V  
1 kΩ  
= 15 pF  
R
RE  
1.5 V  
PZL  
5 V  
C
L
RE  
t
t
PLZ  
Signal  
Generator  
V
CC  
50 Ω  
1.5 V  
R
V
OL  
+0.5 V  
V
OL  
Figure 13. Receiver Enable Test Circuit and Waveforms, Data Output Low  
V
CC  
Switch Down for V  
= 1.5 V,  
(A)  
= −1.5 V  
Switch Up for V  
(A)  
A
B
1.5 V or  
−1.5 V  
R
3 V  
1 kΩ  
1.5 V  
RE  
t
C
L
= 15 pF  
0 V  
r(Standby)  
RE  
t
r(Wake)  
Signal  
Generator  
50 Ω  
5 V  
V
OH  
OL  
V
V
−0.5 V  
+0.5 V  
OH  
OL  
R
1.5 V  
V
0 V  
Figure 14. Receiver Standby and Wake Test Circuit and Waveforms  
Bus Data Valid Region  
200 mV  
Bus Data  
−40 mV  
−200 mV  
Transition Region  
V
ID  
Bus Data Valid Region  
−1.5 V  
t
t
p(RESET)  
p(SET)  
V
OH  
1.5 V  
R
V
OL  
Figure 15. Receiver Active Failsafe Definitions and Waveforms  
V
TEST  
100 Ω  
0 V  
Pulse Generator,  
15 µs Duration,  
1% Duty Cycle  
1.5 ms  
15 µs  
−V  
TEST  
Figure 16. Test Circuit and Waveforms, Transient Overvoltage Test  
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005  
PIN ASSIGNMENTS  
D or P PACKAGE  
(TOP VIEW)  
R
RE  
DE  
D
V
CC  
B
A
1
2
3
4
8
7
6
5
GND  
LOGIC DIAGRAM  
POSITIVE LOGIC  
1
R
6
A
2
3
RE  
7
B
DE  
4
D
TYPICAL CHARACTERISTICS  
HVD20, HVD23  
BUS PIN CURRENT  
vs  
HVD21, HVD22, HVD24  
BUS PIN CURRENT  
vs  
BUS PIN VOLTAGE  
BUS PIN VOLTAGE  
150  
100  
600  
400  
DE = 0 V  
DE = 0 V  
200  
50  
0
V
CC  
= 0 V  
V
CC  
= 0 V  
0
V
CC  
= 5 V  
V
CC  
= 5 V  
−50  
−200  
−100  
−150  
−400  
−600  
−30  
−20  
−10  
0
10  
20  
30  
−30  
−20  
−10  
0
10  
20  
30  
Bus Pin Voltage − V  
Bus Pin Voltage − V  
Figure 17  
Figure 18  
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SUPPLY CURRENT  
vs  
SIGNALING RATE  
DRIVER DIFFERENTIAL OUTPUT VOLTAGE  
vs  
DRIVER LOAD CURRENT  
75  
70  
65  
60  
55  
50  
45  
40  
5
V
= 5 V,  
HVD20  
CC  
DE = RE = V  
CC  
LOAD = 54 , 50 pF  
,
4.5  
V
= 5.5 V  
CC  
4
3.5  
V
CC  
= 5 V  
HVD21  
HVD22  
3
2.5  
2
V
= 4.5 V  
CC  
1.5  
1
0.5  
0
0.1  
1
10  
100  
0
10  
20  
30  
40  
50  
60  
70  
80  
Signaling Rate − Mbps  
I
− Driver Load Current − mA  
L
Figure 19  
Figure 20  
HVD20, HVD23  
RECEIVER OUTPUT VOLTAGE  
vs  
DIFFERENTAL INPUT VOLATGE  
PEAK-TO-PEAK JITTER  
vs  
CABLE LENGTH  
6
5
4
3
2
1
30  
25  
20  
15  
V
= 5 V,  
= 25°C,  
= 2.5 V,  
CC  
V
V
IT(+)  
IT(−)  
T
A
V
IC  
Cable: Belden 3105A  
V
= 25 V  
= 0 V  
CM  
V
= 25 V  
CM  
HVD20 = 25 Mbps  
V
CM  
V
= 0 V  
CM  
V
= −20 V  
CM  
V
= −20 V  
CM  
10  
5
HVD23 = 25 Mbps  
0
−1  
−0.2  
0
100  
−0.1  
0
0.1  
0.2  
120  
140  
160  
180  
200  
V
ID  
− Differential Input Voltage − V  
Cable Length − m  
Figure 22  
Figure 21  
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005  
HVD20, HVD21, HVD23, HVD24  
PEAK-TO-PEAK JITTER  
vs  
HVD20, HVD23  
PEAK-TO-PEAK JITTER  
vs  
CABLE LENGTH  
SIGNALING RATE  
70  
130  
110  
90  
V
= 5 V,  
HVD21: 500 m Cable  
CC  
= 25°C,  
T
A
HVD21 = 10 Mbps  
60  
50  
40  
30  
20  
V
= 2.5 V,  
IC  
Cable: Belden 3105A  
V
= 5 V,  
CC  
= 25°C,  
T
A
V
IC  
= 2.5 V,  
70  
HVD20 = 10 Mbps  
HVD23 = 10 Mbps  
Cable: Belden 3105A  
50  
30  
10  
10  
0
HVD24: 500 m Cable  
4.5  
HVD24 = 10 Mbps  
260 280  
200  
220  
240  
300  
3
3.5  
4
5
Cable Length − m  
Signaling Rate − Mbps  
Figure 23  
Figure 24  
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APPLICATION INFORMATION  
THEORY OF OPERATION  
The HVD2x family of devices integrates a differential receiver and differential driver with additional features for  
improved performance in electrically-noisy, long-cable, or other fault-intolerant applications.  
The receiver hysteresis (typically 130 mV) is much larger than found in typical RS-485 transceivers. This helps  
reject spurious noise signals which would otherwise cause false changes in the receiver output state.  
Slew rate limiting on the driver outputs (SN65HVD21, 22, and 24) reduces the high-frequency content of signal  
edges. This decreases reflections from bus discontinuities, and allows longer stub lengths between nodes and  
the main bus line. Designers should consider the maximum signaling rate and cable length required for a  
specific application, and choose the transceiver best matching those requirements.  
When DE is low, the differential driver is disabled, and the A and B outputs are in high-impedance states. When  
DE is high, the differential driver is enabled, and drives the A and B outputs according to the state of the D input.  
When RE is high, the differential receiver output buffer is disabled, and the R output is in a high-impedance state.  
When RE is low, the differential receiver is enabled, and the R output reflects the state of the differential bus  
inputs on the A and B pins.  
If both the driver and receiver are disabled, (DE low and RE high) then all nonessential circuitry, including  
auxiliary functions such as failsafe and receiver equalization is placed in a low-power standby state. This  
reduces power consumption to less than 5 µW. When either enable input is asserted, the circuitry again  
becomes active.  
In addition to the primary differential receiver, these devices incorporate a set of comparators and logic to  
implement an active receiver failsafe feature. These components determine whether the differential bus signal  
is valid. Whenever the differential signal is close to zero volts (neither high nor low), a timer initiates, If the  
differential input remains within the transition range for more than 250 microseconds, the timer expires and set  
the receiver output to the high state. If a valid bus input (high or low) is received at any time, the receiver output  
reflects the valid bus state, and the timer is reset.  
+
(V −V ) : Not High  
A
B
120 mV  
Bus Input  
Invalid  
(V −V ) : Not Low  
+
A
B
Timer  
250  
120 mV  
ms  
1
Active  
Filters  
R
2
3
RE  
DE  
STANDBY  
6
A
B
Slew  
Rate  
4
D
7
Control  
Figure 25. Function Block Diagram  
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005  
Figure 26. HVD22 Receiver Operation With 20-V Offset on Input Signal  
k0  
(DC  
loss)  
k p  
2 2  
ǒs ) p2Ǔ  
k p  
3 3  
ǒs ) p3Ǔ  
k p  
1 1  
ǒs ) p1Ǔ  
p1  
(MHz)  
p2  
(MHz)  
p3  
(MHz)  
ǒ1–k Ǔ)  
ǒ1–k Ǔ)  
ǒ1–k Ǔ)  
3
k1  
k2  
k3  
H(s) + k  
ƪ ƫ  
ƪ ƫƪ ƫ  
0
1
2
Similar to 160m of Belden 3105A  
Similar to 250m of Belden 3105A  
Similar to 500m of Belden 3105A  
Similar to 1000m of Belden 3105A  
0.95  
0.9  
0.8  
0.6  
0.25  
0.25  
0.25  
0.3  
0.3  
0.4  
0.6  
1
3.5  
3.5  
2.2  
3
0.5  
0.7  
1
15  
12  
8
1
1
1
1
1
6
Signal  
Generator  
H(s)  
Figure 27. Cable Attenuation Model for Jitter Measurements  
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INTEGRATED RECEIVER EQUALIZATION USING THE HVD23  
Figure 28 illustrates the benefits of integrated receiver equalization as implemented in the HVD23 transceiver.  
In this test setup, a differential signal generator applied a signal voltage at one end of the cable, which was  
Belden 3105A twisted-pair shielded cable. The test signal was a pseudo-random bit stream (PRBS) of  
nonreturn-to-zero (NRZ) data. Channel 1 (top) shows the eye-pattern of the differential voltage at the receiver  
inputs (after the cable attenuation). Channel 2 (bottom) shows the output of the receiver.  
Figure 28. HVD23 Receiver Performance at 25 Mbps Over 150 Meter Cable  
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005  
INTEGRATED RECEIVER EQUALIZATION USING THE HVD24  
Figure 29 illustrates the benefits of integrated receiver equalization as implemented in the HVD24 transceiver.  
In this test setup, a differential signal generator applied a signal voltage at one end of the cable, which was  
Belden 3105A twisted-pair shielded cable. The test signal was a pseudo-random bit stream (PRBS) of  
nonreturn-to-zero (NRZ) data. Channel 1 (top) shows the eye-pattern of the bit stream. Channel 2 (middle)  
shows the eye-pattern of the differential voltage at the receiver inputs (after the cable attenuation). Channel  
3 (bottom) shows the output of the receiver.  
Figure 29. HVD24 Receiver Performance at 5 Mbps Over 500 Meter Cable  
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NOISE CONSIDERATIONS FOR EQUALIZED RECEIVERS  
The simplest way of overcoming the effects of cable losses is to increase the sensitivity of the receiver. If the  
maximum attenuation of frequencies of interest is 20 dB, increasing the receiver gain by a factor of ten  
compensates for the cable. However, this means that both signal and noise are amplified. Therefore, the  
receiver with higher gain is more sensitive to noise and it is important to minimize differential noise coupling  
to the equalized receiver.  
Differential noise is crated when conducted or radiated noise energy generates more voltage on one line of the  
differential pair than the other. For this to occur from conducted or electric far-field noise, the impedance to  
ground of the lines must differ.  
For noise frequency out to 50 MHz, the input traces can be treated as a lumped capacitance if the receiver is  
approximately 10 inches or less from the connector. Therefore, matching impedance of the lines is  
accomplished by matching the lumped capacitance of each.  
The primary factors that affect the capacitance of a trace are in length, thickness, width, dielectric material,  
distance from the signal return path, stray capacitance, and proximity to other conductors. It is difficult to match  
each of the variables for each line of the differential pair exactly, but a reasonable effort to do so keeps the lines  
balanced and less susceptible to differential noise coupling.  
Another source of differential noise is from near-field coupling. In this situation, an assumption of equal  
noise-source impedance cannot be made as in the far-field. Familiarly known as crosstalk, more energy from  
a nearby signal is coupled to one line of the differential pair. Minimization of this differential noise is  
accomplished by keeping the signal pair close together and physical separation from high-voltage, high-current,  
or high-frequency signals.  
In summary, follow these guidelines in board layout for keeping differential noise to a minimum.  
D
D
D
D
D
Keep the differential input traces short.  
Match the length, physical dimensions, and routing of each line of the pair.  
Keep the lines close together.  
Match components connected to each line.  
Separate the inputs from high-voltage, high-frequency, or high-current signals.  
20  
PACKAGE OPTION ADDENDUM  
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4-Nov-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
SOIC  
SOIC  
PDIP  
Drawing  
SN65HVD20D  
SN65HVD20DR  
SN65HVD20P  
ACTIVE  
ACTIVE  
ACTIVE  
D
D
P
8
8
8
75  
2500  
50  
TBD  
TBD  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-NC-NC-NC  
Pb-Free  
(RoHS)  
SN65HVD21D  
SN65HVD21DR  
SN65HVD21P  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
PDIP  
D
D
P
8
8
8
75  
2500  
50  
TBD  
TBD  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-NC-NC-NC  
Pb-Free  
(RoHS)  
SN65HVD22D  
SN65HVD22DR  
SN65HVD22P  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
PDIP  
D
D
P
8
8
8
75  
2500  
50  
TBD  
TBD  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-NC-NC-NC  
Pb-Free  
(RoHS)  
SN65HVD22PE4  
ACTIVE  
PDIP  
P
8
50  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
SN65HVD23D  
SN65HVD23DR  
SN65HVD23P  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
PDIP  
D
D
P
8
8
8
75  
2500  
50  
TBD  
TBD  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-NC-NC-NC  
Pb-Free  
(RoHS)  
SN65HVD23PE4  
ACTIVE  
PDIP  
P
8
50  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
SN65HVD24D  
SN65HVD24DR  
SN65HVD24P  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
PDIP  
D
D
P
8
8
8
75  
2500  
50  
TBD  
TBD  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-1-220C-UNLIM  
CU NIPDAU Level-NC-NC-NC  
Pb-Free  
(RoHS)  
SN65HVD24PE4  
ACTIVE  
PDIP  
P
8
50  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
4-Nov-2005  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
MECHANICAL DATA  
MPDI001A – JANUARY 1995 – REVISED JUNE 1999  
P (R-PDIP-T8)  
PLASTIC DUAL-IN-LINE  
0.400 (10,60)  
0.355 (9,02)  
8
5
0.260 (6,60)  
0.240 (6,10)  
1
4
0.070 (1,78) MAX  
0.325 (8,26)  
0.300 (7,62)  
0.020 (0,51) MIN  
0.015 (0,38)  
Gage Plane  
0.200 (5,08) MAX  
Seating Plane  
0.010 (0,25) NOM  
0.125 (3,18) MIN  
0.100 (2,54)  
0.021 (0,53)  
0.430 (10,92)  
MAX  
0.010 (0,25)  
M
0.015 (0,38)  
4040082/D 05/98  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-001  
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that  
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Following are URLs where you can obtain information on other Texas Instruments products and application  
solutions:  
Products  
Applications  
Audio  
Amplifiers  
amplifier.ti.com  
www.ti.com/audio  
Data Converters  
dataconverter.ti.com  
Automotive  
www.ti.com/automotive  
DSP  
dsp.ti.com  
Broadband  
Digital Control  
Military  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
Logic  
interface.ti.com  
logic.ti.com  
Power Mgmt  
Microcontrollers  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
Telephony  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address:  
Texas Instruments  
Post Office Box 655303 Dallas, Texas 75265  
Copyright 2005, Texas Instruments Incorporated  
配单直通车
SN65HVD21DR产品参数
型号:SN65HVD21DR
Brand Name:Texas Instruments
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
IHS 制造商:TEXAS INSTRUMENTS INC
零件包装代码:SOIC
包装说明:SOIC-8
针数:8
Reach Compliance Code:compliant
ECCN代码:5A991.B
HTS代码:8542.39.00.01
Factory Lead Time:6 weeks
风险等级:1.35
Is Samacsys:N
差分输出:YES
驱动器位数:1
高电平输入电流最大值:0.0001 A
输入特性:DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型:LINE TRANSCEIVER
接口标准:EIA-485-A; TIA-485-A
JESD-30 代码:R-PDSO-G8
JESD-609代码:e4
长度:4.9 mm
湿度敏感等级:1
功能数量:1
端子数量:8
最高工作温度:85 °C
最低工作温度:-40 °C
最小输出摆幅:1.8 V
输出特性:3-STATE
最大输出低电流:0.0001 A
输出极性:TRUE
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装等效代码:SOP8,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260
电源:5 V
认证状态:Not Qualified
最大接收延迟:50 ns
接收器位数:1
座面最大高度:1.75 mm
子类别:Line Driver or Receivers
最大压摆率:12 mA
最大供电电压:5.5 V
最小供电电压:4.5 V
标称供电电压:5 V
电源电压1-最大:5.5 V
电源电压1-分钟:4.5 V
电源电压1-Nom:5 V
表面贴装:YES
技术:BICMOS
温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
最大传输延迟:60 ns
宽度:3.9 mm
Base Number Matches:1
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