SN74ACT7811
1024 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996
Terminal Functions
†
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Almost-full/almost-emptyflag. The AF/AE boundary isdefinedbythealmost-full/almost-emptyoffset
value (X). This value can beprogrammedduringresetorthedefaultvalueof256canbeused. AF/AE
is high when the FIFO contains (X + 1) or less words or (1025 – X) or more words. AF/AE is low when
the FIFO contains between (X +2) and (1024 - X) words.
Programming procedure for AF/AE – The almost-full/almost-empty flag is programmed during each
reset cycle. The almost-full/almost-empty offset value (X) is either a user-defined value or the default
of X = 256. Instructions to program AF/AE using both methods are as follows:
User-defined X
AF/AE
33
O
Step 1: Take DAF from high to low.
Step 2: If RESET is not already low, take RESET low.
Step 3: With DAF held low, take RESET high. This defines the AF/AE using X.
Step 4: To retain the current offset for the next reset, keep DAF low.
Default X
To redefine AF/AE using the default value of X = 256, hold DAF high during the reset cycle.
Define almost full. The high-to-low transition of DAF stores the binary value of data inputs as the
almost-full/almost-empty offset value (X). With DAF held low, a low pulse on RESET defines the
AF/AE flag using X.
DAF
27
I
Data inputs for 18-bit-wide data to be stored in the memory. Data lines D0–D8 also carry the
almost-full/almost-empty offset value (X) on a high-to-low transition of the DAF.
D0–D17
HF
26–19, 17, 15–7
36
I
Half-full flag. HF is high when the FIFO contains 513 or more words and is low when it contains 512
or less words.
O
Input-ready flag. IR is high when the FIFO is not full and low when the device is full. During reset, IR
isdrivenlowontherisingedgeofthesecondWRTCLKpulse. IRisthendrivenhighontherisingedge
of the second WRTCLK pulse after RESET goes high. After the FIFO is filled and IR is driven low,
IR is driven high on the second WRTCLK pulse after the first valid read.
IR
35
2
O
I
Output enable. The data-out (Q0–Q17) outputs are in the high-impedance state when OE is low. OE
must be high before the rising edge of RDCLK to read a word from memory.
OE
OR
Output-ready flag. OR is high when the FIFO is not empty and low when it is empty. During reset,
OR is set low on the rising edge of the third RDCLK pulse. OR is set high on the rising edge of the
third RDCLK pulse to occur after the first word is written into the FIFO. OR is set low on the rising
edge of the first RDCLK pulse after the last word is read.
66
O
38–39, 41–42, 44,
46–47, 49–50,
52–53, 55–56,
Data outputs. The first data word to be loaded into the FIFO is moved to Q0–Q17 on the rising edge
of the third RDCLK pulse to occur after the first valid write. The RDEN1 and RDEN2 inputs do not
affect this operation. Following data is unloaded on the rising edge of RDCLK when RDEN1, RDEN2,
OE, and the OR are high.
Q0–Q17
RDCLK
O
58–59, 61, 63–64
Read clock. Data is read out of memory on a low-to-high transition RDCLK if OR, OE, and RDEN1
and RDEN2 control inputs are high. RDCLK is a free-running clock and functions as the
synchronizing clock for all data transfers out of the FIFO. OR is also driven synchronously with
respect to RDCLK.
5
I
I
RDEN1,
RDEN2
4
3
Read enable. RDEN1 and RDEN2 must be high before a rising edge on RDCLK to read a word out
of memory. RDEN1 and RDEN2 are not used to read the first word stored in memory.
A reset is accomplished by taking RESET low and generating a minimum of four RDCLK and
WRTCLK cycles. This ensures that the internal read and write pointers are reset and OR, HF, and
IR are low and AF/AE is high. The FIFO must be reset upon power up. With DAF at a low level, a low
pulse on RESET defines the AF/AE status flag using the almost-full/almost-empty offset value (X),
where X is the value previously stored. With DAF at a high level, a low-level pulse on RESET defines
the AF/AE flag using the default value of X = 256.
RESET
1
I
†
Terminals listed are for the FN package.
5
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