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SN74AUP3G17

www.ti.com

SCES765A –DECEMBER 2009–REVISED DECEMBER 2009

LOW-POWER TRIPLE SCHMITT-TRIGGER BUFFER

Check for Samples: SN74AUP3G17

FEATURES

•

Available in the Texas Instruments NanoStar™

Package

•

Optimized for 3.3-V Operation

3.6-V I/O Tolerant to Support Mixed-Mode

Signal Operation

Low Static-Power Consumption

(I_CC= 0.9 μA Maximum)

•

t_pd= 5.1 ns Maximum at 3.3 V

Low Dynamic-Power Consumption

(C_pd= 4.3 pF Typ at 3.3 V)

Suitable for Point-to-Point Applications

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

Low Input Capacitance (C_i= 1.5 pF Typical)

Low Noise – Overshoot and Undershoot

<10% of V_CC

•

ESD Performance Tested Per JESD 22

–

2000-V Human-Body Model

(A114-B, Class II)

•

I_offSupports Partial-Power-Down Mode

Operation

–

1000-V Charged-Device Model (C101)

Wide Operating V_CCRange of 0.8 V to 3.6 V

DCU PACKAGE

(TOP VIEW)

DQE PACKAGE

(TOP VIEW)

RSE PACKAGE

(TOP VIEW)

YFP PACKAGE

(TOP VIEW)

V_CC

1 8

2 7

3 6

4 5

V_CC

GND

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION

The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable

applications. This family ensures a very low static- and dynamic-power consumption across the entire V_CCrange

of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal

integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

Static-Power Consumption

(µA)

Dynamic-Power Consumption

(pF)

Switching Characteristics

at 25 MHz^(A)

100%

80%

60%

40%

20%

100%

80%

60%

40%

20%

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-0.5

Input

Output

3.3-V

Logic^(A)

3.3-V

Logic^(A)

AUP

(A)

Time (ns)

10 15

35 40 45

Single, dual, and triple gates

^(A)SN74AUP3Gxx data at C = 15 pF.

Figure 1. AUP – The Lowest-Power Family

Figure 2. Excellent Signal Integrity

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

SN74AUP3G17

SCES765A –DECEMBER 2009–REVISED DECEMBER 2009

www.ti.com

The SN74LVC3G17 contains three buffers and performs the Boolean function Y = A. The device functions as

three independent buffers but, because of Schmitt action, it may have different input threshold levels for

positive-going (V_T+) and negative-going (V_T–) signals.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

This device is fully specified for partial-power-down applications using I_off. The I_offcircuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION⁽¹⁾

ORDERABLE

PART NUMBER

TOP-SIDE

T_A

PACKAGE⁽²⁾

MARKING⁽³⁾

NanoStar™ – WCSP (DSBGA)

0.23-mm Large Bump – YFP (Pb-free)

uQFN – DQE

Reel of 3000

SN74AUP3G17YFPR

_ _ H 7 _

Reel of 5000

Reel of 3000

SN74AUP3G17DQER

SN74AUP3G17RSER

SN74AUP3G17DCUR

–40°C to 85°C

QFN – RSE

PREVIEW

H17_

SSOP – DCU

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.

YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

FUNCTION TABLE

INPUT

OUTPUT

LOGIC DIAGRAM (POSITIVE LOGIC)

Pin numbers shown are for the DCU and DQE packages.

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SCES765A –DECEMBER 2009–REVISED DECEMBER 2009

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.5

MAX

4.6

UNIT

V_CC

V_I

Supply voltage range

Input voltage range⁽²⁾

Voltage range applied to any output in the high-impedance or power-off state⁽²⁾

Output voltage range in the high or low state⁽²⁾

4.6

V_O

I_IK

4.6

–0.5 V_CC+ 0.5

Input clamp current

V_I< 0

–50

±20

±50

220

261

253

132

I_OK

I_O

Output clamp current

V_O< 0

Continuous output current

Continuous current through V_CCor GND

DCU package

DQE package

RSE package

YFP package

θ_JA

Package thermal impedance⁽³⁾

°C/W

T_stg

Storage temperature range

–65

150

°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The package thermal impedance is calculated in accordance with JESD 51-7.

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SCES765A –DECEMBER 2009–REVISED DECEMBER 2009

www.ti.com

RECOMMENDED OPERATING CONDITIONS⁽¹⁾

MIN

0.8

MAX UNIT

V_CC

V_I

Supply voltage

Input voltage

Output voltage

3.6

V_CC

–20

–1.1

–1.7

–1.9

–3.1

–4

V_O

V_CC= 0.8 V

V_CC= 1.1 V

V_CC= 1.4 V

V_CC= 1.65

μA

I_OH

High-level output current

μA

V_CC= 2.3 V

V_CC= 3 V

V_CC= 0.8 V

V_CC= 1.1 V

V_CC= 1.4 V

V_CC= 1.65 V

V_CC= 2.3 V

V_CC= 3 V

1.1

1.7

1.9

3.1

I_OL

Low-level output current

Δt/Δv

Input transition rise or fall rate

Operating free-air temperature

V_CC= 0.8 V to 3.6 V

200

ns/V

°C

T_A

–40

(1) All unused inputs of the device must be held at V_CCor GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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SCES765A –DECEMBER 2009–REVISED DECEMBER 2009

ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range (unless otherwise noted)

T_A= 25°C

T_A= –40°C to 85°C

PARAMETER

TEST CONDITIONS

V_CC

UNIT

MIN TYP

0.3

MAX

0.6

MIN

0.3

MAX

0.8 V

1.1 V

0.6

0.9

0.53

0.74

0.91

1.37

1.88

0.1

0.9

0.53

V_T+

1.4 V

1.11

1.29

1.77

2.29

0.6

0.74

1.11

1.29

1.77

2.29

0.6

Positive-going

input threshold

voltage

1.65 V

2.3 V

0.91

1.37

3 V

1.88

0.8 V

0.1

1.1 V

0.26

0.39

0.47

0.69

0.88

0.07

0.08

0.18

0.27

0.53

0.79

0.65

0.75

0.84

1.04

1.24

0.5

0.26

0.65

0.75

0.84

1.04

1.24

0.5

V_T–

1.4 V

0.39

Negative-going

input threshold

voltage

1.65 V

2.3 V

0.47

0.69

3 V

0.88

0.8 V

0.07

1.1 V

0.46

0.56

0.66

0.92

1.31

0.08

0.46

0.56

0.66

0.92

1.31

ΔV_T

Hysteresis

(V_T+– V_T–

1.4 V

0.18

1.65 V

2.3 V

0.27

)

0.53

3 V

0.79

I_OH= –20 μA

0.8 V to 3.6 V

1.1 V

V_CC– 0.1

0.7 × V_CC

1.03

I_OH= –1.1 mA

I_OH= –1.7 mA

I_OH= –1.9 mA

I_OH= –2.3 mA

I_OH= –3.1 mA

I_OH= –2.7 mA

I_OH= –4 mA

I_OL= 20 μA

0.75 × V_CC

1.11

1.4 V

1.65 V

1.32

1.3

V_OH

2.05

1.97

2.3 V

3 V

1.9

1.85

2.72

2.67

2.6

2.55

0.8 V to 3.6 V

1.1 V

0.1

0.3 × V_CC

0.31

0.1

0.3 × V_CC

0.37

I_OL= 1.1 mA

I_OL= 1.7 mA

I_OL= 1.9 mA

I_OL= 2.3 mA

I_OL= 3.1 mA

I_OL= 2.7 mA

I_OL= 4 mA

1.4 V

1.65 V

0.31

0.35

V_OL

0.31

0.33

2.3 V

3 V

0.44

0.45

0.31

0.33

0.44

0.45

I_I

A or B input V_I= GND to 3.6 V

V_Ior V_O= 0 V to 3.6 V

0 V to 3.6 V

0 V

0.1

0.5

μA

I_off

ΔI_off

0.2

0.6

V_Ior V_O= 0 V to 3.6 V

0 V to 0.2 V

0.2

0.6

V_I= GND or

(V_CCto 3.6 V),

I_O= 0

V_I= V_CC– 0.6 V⁽¹⁾

I_O= 0

I_CC

0.8 V to 3.6 V

0.5

0.9

μA

ΔI_CC

3.3 V

0 V

3.6 V

0 V

1.5

C_i

V_I= V_CCor GND

V_O= GND

C_o

(1) One input at V_CC– 0.6 V, other input at V_CCor GND

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SCES765A –DECEMBER 2009–REVISED DECEMBER 2009

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SWITCHING CHARACTERISTICS

over recommended operating free-air temperature range, C_L= 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)

T_A= 25°C

MIN TYP MAX

T_A= –40°C to 85°C

FROM

(INPUT)

(OUTPUT)

PARAMETER

V_CC

UNIT

M IN

MAX

0.8 V

22.7

1.2 V ± 0.1 V

1.5 V ± 0.1 V

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

6.3

4.6

3.9

3.1

2.7

12.8

8.4

7.2

5.1

4.4

3.9

2.8

2.4

14.6

5.8

4.8

3.6

t_pd

8.1

6.1

5.1

1.9

SWITCHING CHARACTERISTICS

over recommended operating free-air temperature range, C_L= 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)

T_A= 25°C

MIN TYP MAX

25.1

9.1 13.8

T_A= –40°C to 85°C

FROM

(INPUT)

(OUTPUT)

PARAMETER

V_CC

UNIT

MIN

MAX

0.8 V

1.2 V ± 0.1 V

1.5 V ± 0.1 V

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

7.1

5.2

4.5

3.5

3.1

4.7

3.4

2.9

2.4

2.2

15.6

6.5

5.4

4.2

3.5

9.4

t_pd

5.7

4.9

6.8

5.7

SWITCHING CHARACTERISTICS

over recommended operating free-air temperature range, C_L= 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)

T_A= 25°C

MIN TYP MAX

T_A= –40°C to 85°C

FROM

(INPUT)

(OUTPUT)

PARAMETER

V_CC

UNIT

MIN

MAX

0.8 V

27.6

1.2 V ± 0.1 V

1.5 V ± 0.1 V

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

7.8

5.8

10.1 14.8

7.4 10.3

5.3

3.9

3.4

2.8

2.6

16.7

t_pd

6.1

4.7

4.1

8.8

6.4

5.4

7.5

6.2

3.5

SWITCHING CHARACTERISTICS

over recommended operating free-air temperature range, C_L= 30 pF (unless otherwise noted) (see Figure 3 and Figure 4)

T_A= 25°C

TYP

35.1

13.1

9.6

T_A= –40°C to 85°C

FROM

(INPUT)

(OUTPUT)

PARAMETER

V_CC

UNIT

MIN

MAX

MIN

MAX

0.8 V

1.2 V ± 0.1 V

1.5 V ± 0.1 V

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

7.4

6.4

5.2

4.6

18.1

12.9

7.5

5.6

4.8

19.8

14.9

12.4

9.3

t_pd

7.9

6.1

8.1

5.3

6.9

3.6

7.7

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SCES765A –DECEMBER 2009–REVISED DECEMBER 2009

OPERATING CHARACTERISTICS

T_A= 25°C

PARAMETER

TEST CONDITIONS

V_CC

TYP UNIT

0.8 V

1.2 V ± 0.1 V

1.5 V ± 0.1 V

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

C_pd

Power dissipation capacitance

f = 10 MHz

4.1

4.3

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SCES765A –DECEMBER 2009–REVISED DECEMBER 2009

www.ti.com

PARAMETER MEASUREMENT INFORMATION

(Propagation Delays, Setup and Hold Times, and Pulse Width)

From Output

Under Test

(see Note A)

1 MΩ

LOAD CIRCUIT

= 1.2 V

= 1.5 V

= 1.8 V

= 2.5 V

= 3.3 V

= 0.8 V

± 0.1 V

5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF

/2 /2 /2

± 0.1 V

± 0.15 V

± 0.2 V

± 0.3 V

5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF

V /2

Input

0 V

Input

VOLTAGE WAVEFORMS

PULSE DURATION

0 V

PHL

PLH

PHL

Output

Timing Input

0 V

PLH

Output

V /2

Data Input

0 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

A. C_Lincludes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output

control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the

output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, for

propagation delays t_r/t_f= 3 ns, for setup and hold times and pulse width t_r/t_f= 1.2 ns.

D. The outputs are measured one at a time, with one transition per measurement.

E. t_PLHand t_PHLare the same as t_pd

F. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit and Voltage Waveforms

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SCES765A –DECEMBER 2009–REVISED DECEMBER 2009

PARAMETER MEASUREMENT INFORMATION

(Enable and Disable Times)

2 xV

5 kΩ

From Output

Under Test

GND

TEST

PLZ PZL

2 xV

5 kΩ

(see Note A)

PHZ PZH

GND

LOAD CIRCUIT

= 1.2 V

= 1.5 V

= 1.8 V

= 2.5 V

= 3.3 V

= 0.8 V

± 0.1 V

5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF

/2 /2 /2

± 0.1 V

± 0.15 V

5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF

/2 /2 /2

± 0.2 V

± 0.3 V

∆

0.1 V

0.15 V

0.3 V

Output

V /2

Control

0 V

PZL

PLZ

Output

Waveform 1

S1 at 2 xV

+ V

∆

(see Note B)

PHZ

PZH

Output

Waveform 2

S1 at GND

- V

∆

≈0 V

(see Note B)

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

A. C_Lincludes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output

control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the

output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f= 3 ns.

D. The outputs are measured one at a time, with one transition per measurement.

E. t_PLZand t_PHZare the same as t_dis

F. t_PLHand t_PHLare the same as t_pd

G. All parameters and waveforms are not applicable to all devices.

Figure 4. Load Circuit and Voltage Waveforms

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PACKAGE OPTION ADDENDUM

www.ti.com

6-Jan-2010

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SN74AUP3G17DCUR

ACTIVE

US8

DCU

3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74AUP3G17DQER

SN74AUP3G17YFPR

PREVIEW

X2SON

DSBGA

DQE

YFP

5000

3000

TBD

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

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TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Amplifiers

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Military

Optical Networking

Security

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

www.ti.com/audio

Data Converters

DLP® Products

DSP

Clocks and Timers

Interface

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/medical

www.ti.com/military

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Logic

Power Mgmt

Microcontrollers

RFID

Telephony

Video & Imaging

Wireless

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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SN74AUP3G17DCUR产品参数

型号:	SN74AUP3G17DCUR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SOIC
包装说明：	VSSOP, TSSOP8,.12,20
针数：	8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	1.66
系列：	AUP/ULP/V
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e4
长度：	2.3 mm
负载电容（CL）：	30 pF
逻辑集成电路类型：	INVERTER
最大I（ol）：	0.004 A
湿度敏感等级：	1
功能数量：	3
输入次数：	1
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	VSSOP
封装等效代码：	TSSOP8,.12,20
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
包装方法：	TR
峰值回流温度（摄氏度）：	260
电源：	1.2/3.3 V
最大电源电流（ICC）：	0.0009 mA
Prop。Delay @ Nom-Sup：	19.8 ns
传播延迟（tpd）：	19.8 ns
认证状态：	Not Qualified
施密特触发器：	YES
座面最大高度：	0.9 mm
子类别：	Gates
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	0.8 V
标称供电电压 (Vsup)：	1.2 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.5 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	2 mm
Base Number Matches：	1

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