SN74HC86DR原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

SN54HC86, SN74HC86

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003

Wide Operating Voltage Range of 2 V to 6 V

Outputs Can Drive Up To 10 LSTTL Loads

4-mA Output Drive at 5 V

Low Input Current of 1 µA Max

True Logic

Low Power Consumption, 20-µA Max I

CC

Typical t = 10 ns

pd

SN54HC86 . . . J OR W PACKAGE

SN74HC86 . . . D, N, NS, OR PW PACKAGE

(TOP VIEW)

SN54HC86 . . . FK PACKAGE

(TOP VIEW)

1A

1B

V

CC

13 4B

12 4A

1

2

3

4

5

6

7

14

3

2

1

20 19

18

4A

NC

4Y

1Y

NC

2A

4

5

6

7

8

1Y

17

16

11

10

9

2A

4Y

3B

3A

3Y

2B

NC

2B

15 NC

14

9 10 11 12 13

2Y

3B

8

GND

NC – No internal connection

description/ordering information

These devices contain four independent 2-input exclusive-OR gates. They perform the Boolean function

Y = A B or Y = AB + AB in positive logic.

A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced

in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the

output.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

T

A

PDIP – N

Tube of 25

Tube of 50

Reel of 2500

Reel of 250

Reel of 2000

Tube of 90

Reel of 2000

Reel of 250

Tube of 25

Tube of 150

Tube of 55

SN74HC86N

SN74HC86D

SOIC – D

SN74HC86DR

SN74HC86DT

SN74HC86NSR

SN74HC86PW

SN74HC86PWR

SN74HC86PWT

SNJ54HC86J

SNJ54HC86W

SNJ54HC86FK

HC86

–40°C to 85°C

SOP – NS

TSSOP – PW

HC86

CDIP – J

CFP – W

LCCC – FK

SNJ54HC86J

SNJ54HC86W

SNJ54HC86FK

–55°C to 125°C

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  2003, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54HC86, SN74HC86

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

Y

A

B

L

H

L

H

L

H

exclusive-OR logic

An exclusive-OR gate has many applications, some of which can be represented better by alternative logic

symbols.

Exclusive OR

= 1

These are five equivalent exclusive-OR symbols valid for an ’HC86 gate in positive logic; negation may be

shown at any two ports.

Logic Identity Element

Even-Parity Element

Odd-Parity Element

=

2k

2k + 1

The output is active (low) if

all inputs stand at the same

logic level (i.e., A = B).

The output is active (low) if

an even number of inputs

(i.e., 0 or 2) are active.

The output is active (high) if

an odd number of inputs (i.e.,

only 1 of the 2) are active.

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V

CC

I

Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

IK

I

CC

Output clamp current, I

(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

OK

O O CC

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA

Continuous current through V

O

CC

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W

JA

N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W

NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54HC86, SN74HC86

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003

recommended operating conditions (see Note 3)

SN54HC86

SN74HC86

UNIT

MIN NOM

MAX

MIN NOM

MAX

V

Supply voltage

2

1.5

5

6

2

1.5

5

6

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 2 V

High-level input voltage

= 4.5 V

= 6 V

3.15

4.2

3.15

4.2

V

IH

= 2 V

0.5

1.35

1.8

0.5

1.35

1.8

V

IL

Low-level input voltage

= 4.5 V

= 6 V

V

Input voltage

0

V

0

V

I

CC

Output voltage

O

CC

V

CC

V

CC

V

CC

= 2 V

1000

500

400

125

1000

500

400

85

∆t/∆v

Input transition rise/fall time

= 4.5 V

= 6 V

ns

T

A

Operating free-air temperature

–55

–40

°C

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

T

= 25°C

SN54HC86

SN74HC86

A

PARAMETER

TEST CONDITIONS

V

UNIT

CC

MIN

TYP

MAX

MIN

1.9

4.4

5.9

3.7

5.2

MAX

MIN

1.9

MAX

2 V

4.5 V

6 V

1.9 1.998

4.4 4.499

5.9 5.999

I

= –20 µA

4.4

OH

V

V = V or V

IH

5.9

V

OH

OL

I

IL

I

= –4 mA

4.5 V

6 V

3.98

5.48

4.3

5.8

3.84

5.34

OH

= –5.2 mA

OH

2 V

0.002

0.001

0.17

0.15

0.1

0.26

100

2

0.1

I

= 20 µA

4.5 V

6 V

OL

V

V = V or V

0.1

V

I

IH

I

= 4 mA

4.5 V

6 V

0.4

0.33

1000

20

OL

= 5.2 mA

0.4

OL

I

V = V

I

or 0

6 V

1000

40

nA

µA

pF

I

CC

V = V

I

or 0,

I

O

= 0

6 V

CC

C

2 V to 6 V

3

10

i

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54HC86, SN74HC86

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003

switching characteristics over recommended operating free-air temperature range, C = 50 pF

L

(unless otherwise noted) (see Figure 1)

T

A

= 25°C

TYP

40

SN54HC86

MIN MAX

SN74HC86

MIN MAX

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

V

UNIT

CC

MIN

MAX

100

20

2 V

4.5 V

6 V

150

30

125

25

21

95

19

16

t

A or B

Y

12

ns

pd

t

10

17

25

2 V

28

75

110

22

t

4.5 V

6 V

8

15

ns

6

13

19

operating characteristics, T = 25°C

A

PARAMETER

TEST CONDITIONS

TYP

UNIT

C

Power dissipation capacitance per gate

No load

35

pF

pd

PARAMETER MEASUREMENT INFORMATION

V

CC

From Output

Under Test

Test

Point

Input

50%

0 V

C

= 50 pF

L

t

PLH

PHL

90%

(see Note A)

V

OH

In-Phase

Output

90%

t

50%

10%

50%

10%

LOAD CIRCUIT

OL

t

r

f

t

PLH

PHL

90%

V

CC

V

90%

t

90%

OH

Input

50%

10%

50%

10%

90%

t

Out-of-Phase

Output

50%

10%

50%

10%

0 V

OL

t

r

f

t

r

VOLTAGE WAVEFORM

INPUT RISE AND FALL TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

NOTES: A.

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.

C includes probe and test-fixture capacitance.

L

O

r

f

C. The outputs are measured one at a time with one input transition per measurement.

D. and t are the same as t

t

.

pd

PLH

PHL

Figure 1. Load Circuit and Voltage Waveforms

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

6-Oct-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

LCCC

CDIP

CFP

Drawing

84046012A

8404601CA

ACTIVE

FK

J

20

14

1

TBD

Call TI

Level-NC-NC-NC

8404601DA

W

J

JM38510/65202BCA

SN54HC86J

CDIP

SOIC

J

SN74HC86D

D

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74HC86DE4

SN74HC86DR

ACTIVE

SOIC

PDIP

SO

D

14

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74HC86DRE4

SN74HC86DT

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74HC86DTE4

SN74HC86N

D

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

N

25

Pb-Free

(RoHS)

CU NIPDAU Level-NC-NC-NC

SN74HC86NE4

SN74HC86NSR

SN74HC86NSRE4

SN74HC86PW

SN74HC86PWE4

N

25

Pb-Free

(RoHS)

CU NIPDAU Level-NC-NC-NC

NS

PW

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74HC86PWLE

SN74HC86PWR

OBSOLETE TSSOP

PW

14

TBD

Call TI

ACTIVE

TSSOP

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74HC86PWRE4

SN74HC86PWT

PW

14

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74HC86PWTE4

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SNJ54HC86FK

SNJ54HC86J

SNJ54HC86W

ACTIVE

LCCC

CDIP

CFP

FK

J

20

14

1

TBD

Call TI

Level-NC-NC-NC

W

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Eco Plan

6-Oct-2005

(2)

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

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and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

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