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SN74LV4T125

ZHCSCA5C –FEBRUARY 2014 –REVISED JUNE 2022

SN74LV4T125 具有三态输出CMOS 逻辑电平转换器的单电源四路缓冲器转换

器门

1 特性

2 应用范围

• V_CC为

• 平板电脑

• 智能手机

5V、3.3V、2.5V 和1.8V 的单电源电压转换器

• 个人计算机

• 工业汽车应用

• 工作电压范围为1.8V 至5.5V

• 升压转换

– 1.8V V_CC时，1.2V⁽¹⁾至1.8V

– 2.5V V_CC时，1.5V⁽¹⁾至2.5V

– 3.3V V_CC时，1.8V⁽¹⁾至3.3V

– 5.0V V_CC时，3.3V 至5.0V

• 降压转换

3 说明

SN74LV4T125 是一款具有较宽电压范围的低压

CMOS 缓冲门逻辑器件，用于便携式、电信、工业和

汽车应用。输出电平以电源电压为基准，并且能够支持

1.8V、2.5V、3.3V 和5V CMOS 电平。

– 1.8V V_CC时，3.3V 至1.8V

– 2.5V V_CC时，3.3V 至2.5V

– 3.3V V_CC时，5.0 V 至3.3V

• 逻辑输出以V_CC为基准

• V_CC为3.3V 时，频率高达50MHz

• 输入引脚可耐受5.5V 电压

• -40°C 至125°C 工作温度范围

• 可提供无铅封装：SC-70 (RGY)

该输入采用较低阈值电路设计，可匹配 V_CC= 3.3V 时

的1.8V 输入逻辑电平，并且可用于 1.8V 至3.3V 升压

转换。此外，5V 耐压输入引脚可实现降压转换（例

如，在 V_CC= 2.5V 时，从 3.3V 输入至 2.5V 输出）。

1.8V 至 5.5V 的宽 V_CC范围使生成的所需输出电平能

够连接至控制器或处理器。

SN74LV4T125 器件的设计电流驱动能力为 8mA，能

减少由高驱动输出导致的线路反射、过冲和下冲。

– 3.5 × 3.5 × 1mm

• 闩锁性能超过250mA，

符合JESD 17 规范

• 支持标准逻辑引脚排列

• I_off支持局部关断模式运行

• 与AUP125、LVC125 兼容的CMOS 输出B¹

器件信息

器件型号⁽¹⁾

封装尺寸（标称值）

封装

PW (TSSOP, 14)

5.00mm x 4.40mm

SN74LV4T125

RGY（VQFN，14） 3.50mm x 3.50mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

1OE

5 V, 3.3 V, 2.5 V, 1.8 V

1.8 V

4OE

1.8 V, 2.5 V, 3.3 V

3.3 V

图3-1. 简化版应用示意图

请参考较低V_CC条件下的V_IH/V_IL和输出驱动。

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCLS749

SN74LV4T125

ZHCSCA5C –FEBRUARY 2014 –REVISED JUNE 2022

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Table of Contents

8.2 Functional Block Diagram.........................................10

8.3 Feature Description...................................................10

8.4 Device Functional Modes..........................................11

9 Applications and Implementation................................12

9.1 Application Information............................................. 12

9.2 Typical Application.................................................... 12

10 Power Supply Recommendations..............................13

11 Layout...........................................................................14

11.1 Layout Guidelines................................................... 14

11.2 Layout Example...................................................... 14

12 Device and Documentation Support..........................15

12.1 Documentation Support.......................................... 15

12.2 接收文档更新通知................................................... 15

12.3 支持资源..................................................................15

12.4 Trademarks.............................................................15

12.5 Electrostatic Discharge Caution..............................15

12.6 术语表..................................................................... 15

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用范围............................................................................ 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

Pin Functions.................................................................... 3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 Switching Characteristics............................................7

6.7 Noise Characteristics..................................................8

6.8 Operating Characteristics........................................... 8

6.9 Typical Characteristics................................................8

7 Parameter Measurement Information............................9

8 Detailed Description......................................................10

8.1 Overview...................................................................10

Information.................................................................... 15

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (March 2014) to Revision C (June 2022)

Page

• 向“特性”部分添加了“I_off支持局部关断模式运行”........................................................................................1

• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1

• 添加了“ESD 等级”表、“接收文档更新通知”部分和“支持资源”部分....................................................... 1

Changes from Revision A (March 2014) to Revision B (September 2014)

Page

• 更新了“特性”...................................................................................................................................................1

• Updated Pin Functions table. .............................................................................................................................3

• Added ESD Ratings table, Thermal Information table, Typical Characteristics section, Pin Configuration and

Functions section, Detailed Description section, Power Supply Recommendations section, Layout section,

Receiving Notification of Documentation Updates section, and Community Resources section....................... 4

• Updated Detailed Design Procedure section. ..................................................................................................13

Changes from Revision * (February 2014) to Revision A (March 2014)

Page

• 将第一页预览文档更新为完整版......................................................................................................................... 1

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5 Pin Configuration and Functions

PW Package

(TOP VIEW)

RGY Package

(Transparent TOP VIEW)

V_CC

1OE

4OE

11 4Y

2OE

3OE

GND

Pin Functions

TYPE ⁽¹⁾

DESCRIPTION

NO.

NAME

1 OE

Enable 1

Input 1

Output 1

Enable 2

Input 2

2 OE

Output 2

Ground Pin

Output 3

Input 3

GND

—

3 OE

Enable 3

Output 4

Input 4

4 OE

V_CC

Enable 4

Power Pin

—

(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

MAX

UNIT

V_CC

V_I

Supply voltage range

7.0

Input voltage range⁽²⁾

Voltage range applied to any output in the high-impedance or power-off state⁽²⁾

Voltage range applied to any output in the high or low state⁽²⁾

4.6

V_O

V_CC+ 0.5

I_IK

I_OK

I_O

Input clamp current

V_I< 0

°C

–20

±50

±35

±70

150

Output clamp current

Continuous output current

V_O< 0 or V_O> V_CC

Continuous current through V_CCor GND

Junction temperature

T_J

T_stg

Storage temperature

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE

±2000

±200

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾

Machine Model (MM), per JEDEC specification

V_(ESD)Electrostatic discharge

Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002 ⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

1.6

MAX

5.5

V_CC

–3

–5

–8

–16

UNIT

V_CC

V_I

Supply voltage

Input voltage

High or Low State

H-Z

V_O

Output voltage

V_CC= 1.8 V

V_CC= 2.5 V

I_OH

High-level output current

V_CC= 3.3 V

V_CC= 5.0 V

V_CC= 1.8 V

V_CC= 2.5 V

I_OL

Low-level output current

V_CC= 3.3 V

V_CC= 5.0 V

V_CC= 1.6 V to 2.0 V

V_CC= 2.3 V to 2.7 V

V_CC= 3 V or 3.6 V

V_CC= 4.5 V to 5.0 V

Input transition rise or fall rate

Operating free-air temperature

ns/V

°C

∆t/∆v

T_A

125

–40

(1) All unused inputs of the device must be held at V_CCor GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

6.4 Thermal Information

SN74LV4T125

THERMAL METRIC⁽¹⁾

14 PINS

126.9

54.2

RGY

14 PINS

52.9

UNIT

R_θJA

R_θJCtop

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

67.8

68.6

29.0

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

7.5

2.6

68.0

29.1

ψ_JB

R_θJCbot

9.3

—

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

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6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

T_A= 25°C

T_A= –40°C to 125°C

PARAMETER

TEST CONDITIONS

V_CC

UNIT

MIN

TYP

MAX

MIN

MAX

V_CC= 1.65 V to 1.9 V

V_CC= 2.3 V to 2.7 V

V_CC= 3 V to 3.6 V

V_CC= 4.5 V to 5.0 V

V_CC= 1.65 V to 1.9 V

V_CC= 2.3 V to 2.77 V

V_CC= 3 V to 3.6 V

V_CC= 4.5 V to 5.5 V

V_CC= 1.65 V to 5.5 V

V_CC= 1.65 V

0.95

1.1

1.3

1.2

1.35

High-level input

voltage

V_IH

0.55

0.7

0.5

0.6

Low-level input

voltage

V_IL

0.85

0.9

0.75

0.85

I_OH= –50 µA

_CC–0.1

1.4

_CC–0.1

1.35

2.0

I_OH= –2 mA

I_OH= –3 mA

I_OH= –5 mA

I_OH= –8 mA

I_OH= –16 mA

I_OL= 50 µA

V_CC= 2.3 V

2.05

2.7

2.6

High-level output

voltage

V_OH

V_CC= 3.0 V

V_CC= 4.5 V

2.6

2.5

3.7

3.6

3.8

3.7

V_CC= 5.0 V

4.4

4.3

V_CC= 1.65 V to 5.5 V

V_CC= 1.65 V

V_CC= 1.8 V

0.1

I_OH= 2 mA

I_OH= 3 mA

0.2

0.3

V_CC= 2.3 V

0.2

0.3

V_CC= 2.5 V

0.25

0.35

0.4

0.3

Low-level output

voltage

V_OL

I_OH= 5 mA

I_OH= 8 mA

I_OH= 16 mA

0.4

V_CC= 3.0 V

V_CC= 3.3 V

V_CC= 4.5 V

V_CC= 5.0 V

0.45

0.5

0.45

0.50

0.55

Input leakage

current

V_CC= 0 V, 1.8 V,

2.5 V, 3.3 V, 5.5 V

I_I

V_I=0 V or V_CC

±0.1

±1

μA

V_CC= 5.0 V

V_CC= 3.3 V

V_CC= 2.5 V

V_CC= 1.8 V

Static supply

current

V_I= 0 V or V_CC

I_O= 0; open on loading

I_CC

μA

One input at 0.3 V or 3.4 V

Other inputs at 0 or V_CC

I_O= 0

V_CC= 5.5 V

V_CC= 1.8 V

Additional static

supply current

1.35

1.5

∆I_CC

One input at 0.3 V or 1.1 V

Other inputs at 0 or V_CC

I_O= 0

Off-state (High

I_OZ

Impedance State) V_O= V_CCor GND

Output Current

V_CC= 5.5 V

V_CC= 0 V

±0.25

0.5

±2.5

μA

Partial power down

V_Oor V_I= 0 to 5.5 V

current

I_off

C_i

Input capacitance V_I= V_CCor GND

Output capacitance V_O= V_CCor GND

V_CC= 3.3 V

1.6

4.8

1.6

4.8

C_o

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6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) (see 图7-1)

T_A= 25°C

T_A= –65°C to 125°C

FROM

(INPUT)

(OUTPUT)

FREQUENCY

(TYP)

PARAMETER

V_CC

C_L

UNIT

MIN

TYP

2.8

MAX

3.2

3.5

4.5

5.5

6.5

MIN

TYP

MAX

3.5

4.5

5.5

6.5

7.5

8.5

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

15 pF

30 pF

5.0 V

3.3 V

2.5 V

1.8 V

5.0 V

3.3 V

2.5 V

1.8 V

5.0 V

3.3 V

2.5 V

1.8 V

5.0 V

3.3 V

2.5 V

1.8 V

5.0 V

3.3 V

2.5 V

1.8 V

DC to 50 MHz

5.5

t_pd

Any In

5.5

6.5

3.5

3.8

DC to 50 MHz

DC to 30 MHz

7.5

12.5

3.5

4.2

5.8

4.5

6.1

6.5

DC to 50 MHz

5.8

5.7

8.5

5.5

7.5

t_PZH

t_PZL

t_PHZ

DC to 50 MHz

DC to 30 MHz

8.5

3.5

9.5

16.5

14.5

15.5

3.5

5.3

5.8

4.5

6.2

7.5

9.5

DC to 50 MHz

5.6

6.2

8.5

9.5

17.5

18.5

3.5

DC to 50 MHz

DC to 30 MHz

10.5

3.5

18.5

3.5

4.5

DC to 50 MHz

4.5

6.5

5.5

7.5

6.5

DC to 50 MHz

DC to 30 MHz

8.5

2.7

3.2

2.5

DC to 50 MHz

2.3

2.8

3.3

2.8

3.2

3.8

4.3

5.5

2.5

3.3

3.8

4.2

t_PLZ

4.2

DC to 50 MHz

DC to 30 MHz

5.7

8.5

6.5

5.0 V

2.5 V

DC to 50 MHz

DC to 30 MHz

15 pF

t_sk

Any In

1.8 V

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6.7 Noise Characteristics

V_CC= 3.3 V, C_L= 50 pF, T_A= 25°C⁽¹⁾

PARAMETER

MIN

TYP

0.4

MAX

UNIT

V_OL(P)

V_OL(V)

V_OH(V)

V_IH(D)

V_IL(D)

Quiet output, maximum dynamic V_OL

Quiet output, minimum dynamic V_OL

Quiet output, minimum dynamic V_OH

High-level dynamic input voltage

Low-level dynamic input voltage

0.8

–0.3

–0.8

2.31

0.99

(1) Characteristics are for surface-mount packages only.

6.8 Operating Characteristics

V_CC= 5 V, T_A= 25°C

PARAMETER

TEST CONDITIONS

TYP

UNIT

C_pd

Power dissipation capacitance

C_L= 50 pF, f = 10 MHz

6.9 Typical Characteristics

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

œ0.5

Output

Input

Time - ns

C001

图6-1. Switching Characteristics at 50 MHz

Excellent Signal Integrity (1.8 V to 3.3 V at 3.3-V V_CC

)

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7 Parameter Measurement Information

7.1

Open

= 1 kΩ

TEST

From Output

Under Test

Test

From Output

Under Test

GND

Point

PLH PHL

Open

(see Note A)

t /t

PLZ PZL

GND

(see Note A)

PHZ PZH

Open Drain

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

3-STATE AND OPEN-DRAIN OUTPUTS

3 V

1.5 V

Timing Input

0 V

3 V

0 V

1.5 V

Input

1.5 V

Data Input

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

3 V

0 V

3 V

0 V

Output

Control

1.5 V

Input

PLZ

PZL

PLH

PHL

Output

≈V

Waveform 1

In-Phase

Output

50% V

S1 at V

(see Note B)

+ 0.3 V

PZH

PHL

PLH

PHZ

Output

Waveform 2

S1 at GND

Out-of-Phase

Output

− 0.3 V

50% V

≈0 V

(see Note B)

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. C includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.

D. The outputs are measured one at a time, with one input transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

图7-1. Load Circuit and Voltage Waveforms

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8 Detailed Description

8.1 Overview

The SN74LVxTxx family was created to allow up- or down-voltage translation with only one power rail. The

family has over-voltage tolerant inputs that allow down translation from up to 5.5 V to the V_CClevel that can be

as low as 1.8 V. The family SN74LVxTxx also has a lowered switching threshold that allows it to translate up to

the V_CClevel that can be as high as 5.5 V.

8.1.1 Translating Down

Using these parts to translate down is very simple. Because the inputs are tolerant to 5.5 V at any valid V_CC

they can be used to down translate. The input can be any level above V_CCup to 5.5 V and the output will equal

the V_CClevel, which can be as low as 1.8 V. One important advantage to down translating using this part is that

the I_CCcurrent will remain less than or equal to the specified value.

Down translation possibilities with SN74LVxTxx:

• With 1.8-V V_CCfrom 2.5 V, 3.3 V, or 5 V down to 1.8 V.

• With 2.5-V V_CCfrom 3.3 V or 5 V down to 2.5 V.

• With 3.3-V V_CCfrom 5 V down to 3.3 V.

8.1.2 Translating Up

Using the SN74LVxTxx family to translate up is very simple. The input switching threshold is lowered so the high

level of the input voltage can be much lower than a typical CMOS V_IH. For instance, If the V_CCis 3.3 V then the

typical CMOS switching threshold would be V_CC/ 2 or 1.65 V. This means the input high level must be at least

V_CC× 0.7 or 2.31 V. On the LVxT devices the input threshold for 3.3-V V_CCis approximately 1 V. This allows a

signal with a 1.8-V V_IHto be translated up to the V_CClevel of 3.3 V.

Up translation possibilities with SN74LVxTxx:

• With 2.5-V V_CCfrom 1.8 V to 2.5 V.

• With 3.3-V V_CCfrom 1.8 V or 2.5 V to 3.3 V.

• With 5-V V_CCFrom 2.5 V or 3.3 V to 5 V.

8.2 Functional Block Diagram

1OE

2OE

3OE

4OE

8.3 Feature Description

This part is a single supply buffer that is capable up or down translation. The output will equal V_CCwhile the

input can vary from 1.2 V to 5.5 V.

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Up Translation Mode:

• 1.2 V to 1.8 V at 1.8-V V_CC

• 1.5 V to 2.5 V at 2.5-V V_CC

• 1.8 V to 3.3 V at 3.3-V V_CC

• 3.3 V to 5.0 V at 5.0-V V_CC

Down Translation Mode:

• 3.3 V to 1.8 V at 1.8-V V_CC

• 3.3 V to 2.5 V at 2.5-V V_CC

• 5.0 V to 3.3 V at 3.3-V V_CC

8.4 Device Functional Modes

This device performs the function of a buffer where input logic level equals the output logic level, while providing

buffering and drive to the output. The SN74LV4T125 device will also translate voltages up or down while

performing this function.

表8-1. Function Table

(Each Buffer)

INPUTS ⁽¹⁾

OUTPUT ⁽²⁾

表8-2. Supply V_CC= 3.3 V

INPUT b

OUTPUT

(Lower Level Input)

(V_CCCMOS)

V_IH(min) = 1.35 V

V_IL(max) = 0.8 V

V_OH(min) = 2.9 V

V_OL(max) = 0.2 V

(1) H = High Voltage Level, L = Low Voltage Level, X = Do not

Care, Z = High Impedance

(2) H = Driving High, L = Driving Low, Z = High Impedance State

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9 Applications and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

Based upon the lower-threshold circuit design of the LVxT family, the LVxT family also supports level translation.

For level translation up and down, the LVxT family requires only a single power supply.

1.8V, 3.3V, 5.0V

Standard Logic Mode 1.8V, 3.3V

9.2 Typical Application

VIH = 2.0V

VIL = 0.8V

VIH = 0.99V

VIL = 0.55V

Vcc = 5.0V

Vcc = 1.8V

5.0V, 3.3V

2.5V, 1.8V

1.5V, 1.2V

System

5.0V

3.3V

System

5.0V

System

1.8V

System

LV1Txx Logic

Vcc = 3.3V

5.0V, 3.3V

2.5V, 1.8V

System

3.3V

System

LV1Txx Logic

VOH min = 2.4V

VIH min = 1.36V

VOL max = 0.4V

VIL min = 0.8V

图9-1. Switching Thresholds for 1.8 V to 3.3 V Translation

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9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. The input threshold levels are lowered to

allow for up translation. At 5 V the device has equivalent TTL input levels.

9.2.2 Detailed Design Procedure

1. Recommended input conditions:

• Rise time and fall time specifications. See (Δt/ΔV) in Recommended Operating Conditions table.

• Specified high and low levels. See (V_IHand V_IL) in Recommended Operating Conditions table.

• Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid V_CC

2. Recommend output conditions:

• Load currents should not exceed 35 mA per output and 70 mA total for the part.

• Outputs should not be pulled above V_CC

9.2.3 Application Curves

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

œ0.5

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

œ0.5

Input

Output

Input

Output

0.0

12.5

25.0

37.5

50.0

62.5

75.0

87.5

Time - ns

Time - nS

C002

C001

图9-2. Switching Characteristics at 50 MHz

Excellent Signal Integrity (3.3 V to 3.3 V at 3.3-V

V_CC

图9-3. Switching Characteristics at 15 MHz

Excellent Signal Integrity (3.3 V to 1.8 V at 1.8-V

V_CC

)

10 Power Supply Recommendations

The power supply can be any voltage between the Min and Max supply voltage rating located in the

Recommended Operating Conditions.

Each V_CCpin should have a good bypass capacitor to prevent power disturbance. For devices with a single

supply, 0.1 µF is recommended. If there are multiple V_CCpins, then 0.01 µF or 0.022 µF is recommended for

each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 µF

and 1 µF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as

possible for best results.

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11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices inputs should not ever float.

In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two

inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be

left unconnected because the undefined voltages at the outside connections result in undefined operational

states. Specified in 图11-1 are the rules that must be observed under all circumstances.

All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating.

The logic level that should be applied to any particular unused input depends on the function of the device.

Generally they will be tied to GND or V_CCwhichever make more sense or is more convenient.

It is generally acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable

pin it will disable the outputs section of the part when asserted. This will not disable the input section of the IOs

so they also cannot float when disabled.

11.2 Layout Example

Input

Unused Input

Output

Unused Input

Output

Input

图11-1. Layout Diagram

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Additional Product Selection

DEVICE

PACKAGE

DCK, DBV

DESCRIPTION

SN74LV1T00

SN74LV1T02

SN74LV1T04

SN74LV1T08

SN74LV1T34

SN74LV1T14

SN74LV1T32

SN74LV1T86

SN74LV1T125

SN74LV1T126

SN74LV4T125

2‐Input Positive‐NAND Gate

2‐Input Positive‐NOR Gate

Inverter Gate

DCK, DBV

2‐Input Positive‐AND Gate

Single Buffer Gate

DCK, DBV, DRL

DCK, DBV

Single Schmitt‐Trigger Inverter Gate

2‐Input Positive‐OR Gate

Single 2‐Input Exclusive‐Or Gate

Single Buffer Gate with 3‐state Output

DCK, DBV

DCK, DBV, DRL

RGY, PW

Quadruple Bus Buffer Gate With 3‐State Outputs

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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14-Jun-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

SN74LV4T125PWR

SN74LV4T125RGYR

ACTIVE

TSSOP

VQFN

2000 RoHS & Green

3000 RoHS & Green

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

-40 to 125

LV4T125

LVT125

Samples

RGY

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

14-Jun-2022

OTHER QUALIFIED VERSIONS OF SN74LV4T125 :

Automotive : SN74LV4T125-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74LV4T125PWR

SN74LV4T125RGYR

TSSOP

VQFN

2000

3000

330.0

12.4

6.9

5.6

1.6

8.0

12.0

RGY

3.75

1.15

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74LV4T125PWR

SN74LV4T125RGYR

TSSOP

VQFN

2000

3000

364.0

356.0

364.0

356.0

27.0

35.0

RGY

Pack Materials-Page 2

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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SN74LV540ADBLE产品参数

型号:	SN74LV540ADBLE
是否Rohs认证：	不符合
生命周期：	Obsolete
零件包装代码：	SSOP
包装说明：	SSOP, SSOP20,.3
针数：	20
Reach Compliance Code：	not_compliant
风险等级：	5.7
其他特性：	WITH DUAL OUTPUT ENABLE
控制类型：	ENABLE LOW
系列：	LV/LV-A/LVX/H
JESD-30 代码：	R-PDSO-G20
长度：	7.2 mm
逻辑集成电路类型：	BUS DRIVER
最大I（ol）：	0.008 A
位数：	8
功能数量：	1
端口数量：	2
端子数量：	20
最高工作温度：	85 °C
最低工作温度：	-40 °C
输出特性：	3-STATE
输出极性：	INVERTED
封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP
封装等效代码：	SSOP20,.3
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH
包装方法：	TAPE AND REEL
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V
Prop。Delay @ Nom-Sup：	12 ns
传播延迟（tpd）：	18.5 ns
认证状态：	Not Qualified
座面最大高度：	2 mm
子类别：	Bus Driver/Transceivers
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	2 V
标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	5.3 mm
Base Number Matches：	1

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