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    产品型号SN74LVC02ARGYRG4的Datasheet PDF文件预览

    SN54LVC02A, SN74LVC02A  
    QUADRUPLE 2-INPUT POSITIVE-NOR GATES  
    www.ti.com  
    SCAS280Q–JANUARY 1993–REVISED JULY 2005  
    FEATURES  
    •
    •
    Operate From 1.65 V to 3.6 V  
    •
    •
    Latch-Up Performance Exceeds 250 mA Per  
    JESD 17  
    Specified From –40°C to 85°C,  
    –40°C to 125°C, and –55°C to 125°C  
    ESD Protection Exceeds JESD 22  
    – 2000-V Human-Body Model (A114-A)  
    – 200-V Machine Model (A115-A)  
    •
    •
    •
    Inputs Accept Voltages to 5.5 V  
    Max tpd of 4.4 ns at 3.3 V  
    Typical VOLP (Output Ground Bounce)  
    <0.8 V at VCC = 3.3 V, TA = 25°C  
    – 1000-V Charged-Device Model (C101)xxxxx  
    xxxxx  
    xxxxx  
    •
    Typical VOHV (Output VOH Undershoot)  
    >2 V at VCC = 3.3 V, TA = 25°C  
    SN54LVC02A . . . J OR W PACKAGE  
    SN74LVC02A . . . D, DB, NS, OR PW PACKAGE  
    (TOP VIEW)  
    SN74LVC02A . . . RGY PACKAGE  
    (TOP VIEW)  
    SN54LVC02A . . . FK PACKAGE  
    (TOP VIEW)  
    1Y  
    1A  
    V
    CC  
    14  
    13  
    12  
    11  
    10  
    9
    1
    2
    3
    4
    5
    6
    7
    1
    14  
    3
    2
    1 20 19  
    18  
    4Y  
    4B  
    4A  
    3Y  
    3B  
    3A  
    4B  
    NC  
    4A  
    1B  
    NC  
    2Y  
    4
    5
    6
    7
    8
    1A  
    1B  
    2Y  
    2A  
    2B  
    13 4Y  
    2
    3
    4
    5
    6
    1B  
    17  
    16  
    12  
    11  
    10  
    9
    4B  
    4A  
    3Y  
    3B  
    2Y  
    2A  
    15 NC  
    14  
    9 10 11 12 13  
    NC  
    2A  
    2B  
    3Y  
    8
    GND  
    7
    8
    NC - No internal connection  
    DESCRIPTION/ORDERING INFORMATION  
    The SN54LVC02A quadruple 2-input positive-NOR gate is designed for 2.7-V to 3.6-V VCC operation, and the  
    SN74LVC02A quadruple 2-input positive-NOR gate is designed for 1.65-V to 3.6-V VCC operation.  
    The 'LVC02A devices perform the Boolean function Y = A + B or Y = A B in positive logic.  
    ORDERING INFORMATION  
    TA  
    PACKAGE(1)  
    ORDERABLE PART NUMBER  
    SN74LVC02ARGYR  
    SN74LVC02AD  
    TOP-SIDE MARKING  
    LC02A  
    –40°C to 85°C  
    QFN – RGY  
    SOIC – D  
    Reel of 1000  
    Tube of 50  
    Reel of 2500  
    Reel of 250  
    Reel of 2000  
    Reel of 2000  
    Tube of 90  
    Reel of 2000  
    Reel of 250  
    Tube of 25  
    Tube of 150  
    Tube of 55  
    SN74LVC02ADR  
    LVC02A  
    SN74LVC02ADT  
    SOP – NS  
    SN74LVC02ANSR  
    SN74LVC02ADBR  
    SN74LVC02APW  
    SN74LVC02APWR  
    SN74LVC02APWT  
    SNJ54LVC02AJ  
    LVC02A  
    LC02A  
    –40°C to 125°C  
    SSOP – DB  
    TSSOP – PW  
    LC02A  
    CDIP – J  
    CFP – W  
    LCCC – FK  
    SNJ54LVC02AJ  
    SNJ54LVC02AW  
    SNJ54LVC02AFK  
    –55°C to 125°C  
    SNJ54LVC02AW  
    SNJ54LVC02AFK  
    (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
    www.ti.com/sc/package.  
    Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
    Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
    PRODUCTION DATA information is current as of publication date.  
    Copyright © 1993–2005, Texas Instruments Incorporated  
    Products conform to specifications per the terms of the Texas  
    On products compliant to MIL-PRF-38535, all parameters are  
    Instruments standard warranty. Production processing does not  
    tested unless otherwise noted. On all other products, production  
    necessarily include testing of all parameters.  
    processing does not necessarily include testing of all parameters.  
    SN54LVC02A, SN74LVC02A  
    QUADRUPLE 2-INPUT POSITIVE-NOR GATES  
    www.ti.com  
    SCAS280Q–JANUARY 1993–REVISED JULY 2005  
    DESCRIPTION/ORDERING INFORMATION (CONTINUED)  
    Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
    in a mixed 3.3-V/5-V system environment.  
    FUNCTION TABLE  
    (EACH GATE)  
    INPUTS  
    OUTPUT  
    Y
    A
    H
    X
    L
    B
    X
    H
    L
    L
    L
    H
    LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)  
    A
    Y
    B
    Absolute Maximum Ratings(1)  
    over operating free-air temperature range (unless otherwise noted)  
    MIN  
    –0.5  
    –0.5  
    MAX  
    6.5  
    UNIT  
    V
    VCC  
    VI  
    Supply voltage range  
    Input voltage range(2)  
    6.5  
    V
    VO  
    IIK  
    Output voltage range(2)(3)  
    –0.5 VCC + 0.5  
    V
    Input clamp current  
    VI < 0  
    –50  
    –50  
    ±50  
    ±100  
    86  
    mA  
    mA  
    mA  
    mA  
    IOK  
    IO  
    Output clamp current  
    VO < 0  
    Continuous output current  
    Continuous current through VCC or GND  
    D package(4)  
    DB package(4)  
    NS package(4)  
    PW package(4)  
    RGY package(5)  
    96  
    θJA  
    Package thermal impedance  
    76  
    °C/W  
    113  
    47  
    Tstg  
    Ptot  
    Storage temperature range  
    Power dissipation  
    –65  
    150  
    500  
    °C  
    TA = –40°C to 125°C(6)(7)  
    mW  
    (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
    only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
    conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
    (2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.  
    (3) The value of VCC is provided in the recommended operating conditions table.  
    (4) The package thermal impedance is calculated in accordance with JESD 51-7.  
    (5) The package thermal impedance is calculated in accordance with JESD 51-5.  
    (6) For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K.  
    (7) For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.  
    2
    SN54LVC02A, SN74LVC02A  
    QUADRUPLE 2-INPUT POSITIVE-NOR GATES  
    www.ti.com  
    SCAS280Q–JANUARY 1993–REVISED JULY 2005  
    Recommended Operating Conditions(1)  
    SN54LVC02A  
    –55°C to 125°C  
    UNIT  
    MIN  
    2
    MAX  
    Operating  
    3.6  
    VCC  
    Supply voltage  
    V
    Data retention only  
    VCC = 2.7 V to 3.6 V  
    VCC = 2.7 V to 3.6 V  
    1.5  
    2
    VIH  
    VIL  
    VI  
    High-level input voltage  
    Low-level input voltage  
    Input voltage  
    V
    V
    V
    V
    0.8  
    5.5  
    VCC  
    –12  
    –24  
    12  
    0
    0
    VO  
    Output voltage  
    VCC = 2.7 V  
    VCC = 3 V  
    VCC = 2.7 V  
    VCC = 3 V  
    IOH  
    High-level output current  
    Low-level output current  
    mA  
    mA  
    IOL  
    24  
    (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,  
    Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
    Recommended Operating Conditions(1)  
    SN74LVC02A  
    TA = 25°C  
    MIN  
    –40°C to 85°C  
    –40°C to 125°C  
    UNIT  
    V
    MAX  
    MIN  
    MAX  
    MIN  
    MAX  
    Operating  
    1.65  
    3.6  
    1.65  
    3.6  
    1.65  
    3.6  
    VCC  
    Supply voltage  
    Data retention only  
    VCC = 1.65 V to 1.95 V  
    VCC = 2.3 V to 2.7 V  
    VCC = 2.7 V to 3.6 V  
    VCC = 1.65 V to 1.95 V  
    VCC = 2.3 V to 2.7 V  
    VCC = 2.7 V to 3.6 V  
    1.5  
    1.5  
    1.5  
    0.65 × VCC  
    0.65 × VCC  
    0.65 × VCC  
    High-level  
    input voltage  
    VIH  
    1.7  
    2
    1.7  
    2
    1.7  
    2
    V
    0.35 × VCC  
    0.35 × VCC  
    0.35 × VCC  
    Low-level  
    input voltage  
    VIL  
    0.7  
    0.8  
    5.5  
    VCC  
    –4  
    0.7  
    0.8  
    5.5  
    VCC  
    –4  
    0.7  
    0.8  
    5.5  
    VCC  
    –4  
    V
    VI  
    Input voltage  
    0
    0
    0
    0
    0
    0
    V
    V
    VO  
    Output voltage  
    VCC = 1.65 V  
    VCC = 2.3 V  
    VCC = 2.7 V  
    VCC = 3 V  
    –8  
    –8  
    –8  
    High-level  
    output current  
    IOH  
    mA  
    mA  
    –12  
    –24  
    4
    –12  
    –24  
    4
    –12  
    –24  
    4
    VCC = 1.65 V  
    VCC = 2.3 V  
    VCC = 2.7 V  
    VCC = 3 V  
    8
    8
    8
    Low-level  
    output current  
    IOL  
    12  
    12  
    12  
    24  
    24  
    24  
    (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,  
    Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
    3
    SN54LVC02A, SN74LVC02A  
    QUADRUPLE 2-INPUT POSITIVE-NOR GATES  
    www.ti.com  
    SCAS280Q–JANUARY 1993–REVISED JULY 2005  
    Electrical Characteristics  
    over recommended operating free-air temperature range (unless otherwise noted)  
    SN54LVC02A  
    –55°C to 125°C  
    MIN TYP  
    PARAMETER  
    TEST CONDITIONS  
    VCC  
    UNIT  
    MAX  
    IOH = –100 µA  
    2.7 V to 3.6 V  
    2.7 V  
    VCC – 0.2  
    2.2  
    2.4  
    2.2  
    VOH  
    IOH = –12 mA  
    V
    3 V  
    IOH = –24 mA  
    IOL = 100 µA  
    IOL = 12 mA  
    3 V  
    2.7 V to 3.6 V  
    2.7 V  
    0.2  
    0.4  
    VOL  
    V
    IOL = 24 mA  
    3 V  
    0.55  
    ±5  
    II  
    VI = 5.5 V or GND  
    3.6 V  
    µA  
    µA  
    µA  
    pF  
    ICC  
    ∆ICC  
    Ci  
    VI = VCC or GND, IO = 0  
    3.6 V  
    10  
    One input at VCC – 0.6 V, Other inputs at VCC or GND  
    VI = VCC or GND  
    2.7 V to 3.6 V  
    3.3 V  
    500  
    5(1)  
    (1) TA = 25°C  
    Electrical Characteristics  
    over recommended operating free-air temperature range (unless otherwise noted)  
    SN74LVC02A  
    –40°C to 85°C  
    PAR-  
    AMETER  
    TEST CONDITIONS  
    VCC  
    TA = 25°C  
    –40°C to 125°C  
    UNIT  
    MIN  
    TYP  
    MAX  
    MIN  
    VCC – 0.2  
    1.2  
    MAX  
    MIN  
    VCC – 0.3  
    1.05  
    MAX  
    IOH = –100 µA  
    1.65 V to 3.6 V VCC – 0.2  
    IOH = –4 mA  
    IOH = –8 mA  
    1.65 V  
    2.3 V  
    1.29  
    1.9  
    2.2  
    2.4  
    2.3  
    1.7  
    1.55  
    VOH  
    V
    2.7 V  
    2.2  
    2.05  
    IOH = –12 mA  
    3 V  
    2.4  
    2.25  
    IOH = –24 mA  
    IOL = 100 µA  
    3 V  
    2.2  
    2
    1.65 V to 3.6 V  
    1.65 V  
    2.3 V  
    0.1  
    0.24  
    0.3  
    0.4  
    0.55  
    ±1  
    0.2  
    0.3  
    0.6  
    IOL = 4 mA  
    0.45  
    0.7  
    0.4  
    0.55  
    ±5  
    VOL  
    IOL = 8 mA  
    0.75  
    0.6  
    V
    IOL = 12 mA  
    2.7 V  
    IOL = 24 mA  
    3 V  
    0.8  
    II  
    VI = 5.5 V or GND  
    VI = VCC or GND, IO = 0  
    3.6 V  
    ±20  
    40  
    µA  
    µA  
    ICC  
    3.6 V  
    1
    10  
    One input at VCC – 0.6 V,  
    Other inputs at VCC or  
    GND  
    ∆ICC  
    2.7 V to 3.6 V  
    3.3 V  
    500  
    500  
    5000  
    µA  
    Ci  
    VI = VCC or GND  
    5
    pF  
    4
    SN54LVC02A, SN74LVC02A  
    QUADRUPLE 2-INPUT POSITIVE-NOR GATES  
    www.ti.com  
    SCAS280Q–JANUARY 1993–REVISED JULY 2005  
    Switching Characteristics  
    over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)  
    SN54LVC02A  
    FROM  
    (INPUT)  
    TO  
    (OUTPUT)  
    PARAMETER  
    VCC  
    –55°C to 125°C  
    UNIT  
    MIN  
    MAX  
    5.4  
    2.7 V  
    tpd  
    A or B  
    Y
    ns  
    3.3 V ± 0.3 V  
    1
    4.4  
    Switching Characteristics  
    over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)  
    SN74LVC02A  
    FROM  
    (INPUT)  
    TO  
    (OUTPUT)  
    PARAMETER  
    VCC  
    TA = 25°C  
    –40°C to 85°C –40°C to 125°C  
    UNIT  
    MIN  
    1
    TYP  
    3.8  
    2.9  
    3
    MAX  
    8.4  
    MIN  
    1
    MAX  
    8.9  
    7.4  
    5.4  
    4.4  
    1
    MIN  
    1
    MAX  
    10.4  
    9.5  
    7
    1.8 V ± 0.15 V  
    2.5 V ± 0.2 V  
    2.7 V  
    1
    6.9  
    1
    1
    tpd  
    A or B  
    Y
    ns  
    ns  
    1
    5.2  
    1
    1
    3.3 V ± 0.3 V  
    3.3 V ± 0.3 V  
    1
    3.6  
    4.2  
    1
    1
    5.5  
    1.5  
    tsk(o)  
    Operating Characteristics  
    TA = 25°C  
    TEST  
    CONDITIONS  
    PARAMETER  
    VCC  
    TYP UNIT  
    1.8 V  
    2.5 V  
    3.3 V  
    7.5  
    Cpd  
    Power dissipation capacitance per gate  
    f = 10 MHz  
    8.5  
    9.5  
    pF  
    5
    SN54LVC02A, SN74LVC02A  
    QUADRUPLE 2-INPUT POSITIVE-NOR GATES  
    www.ti.com  
    SCAS280Q–JANUARY 1993–REVISED JULY 2005  
    PARAMETER MEASUREMENT INFORMATION  
    V
    LOAD  
    S1  
    Open  
    R
    L
    From Output  
    Under Test  
    TEST  
    /t  
    S1  
    GND  
    t
    t
    Open  
    PLH PHL  
    C
    L
    t
    /t  
    V
    R
    L
    PLZ PZL  
    LOAD  
    GND  
    (see Note A)  
    /t  
    PHZ PZH  
    LOAD CIRCUIT  
    INPUTS  
    V
    CC  
    V
    M
    V
    LOAD  
    C
    L
    R
    L
    V
    ∆
    V
    I
    t /t  
    r f  
    1.8 V ± 0.15 V  
    2.5 V ± 0.2 V  
    2.7 V  
    V
    V
    2.7 V  
    2.7 V  
    ≤2 ns  
    ≤2 ns  
    ≤2.5 ns  
    ≤2.5 ns  
    V
    /2  
    /2  
    2 × V  
    2 × V  
    6 V  
    6 V  
    30 pF  
    30 pF  
    50 pF  
    50 pF  
    1 kΩ  
    500 Ω  
    500 Ω  
    500 Ω  
    0.15 V  
    0.15 V  
    0.3 V  
    CC  
    CC  
    CC  
    V
    CC  
    CC  
    CC  
    1.5 V  
    1.5 V  
    3.3 V ± 0.3 V  
    0.3 V  
    V
    I
    Timing Input  
    Data Input  
    V
    M
    0 V  
    t
    w
    t
    t
    h
    su  
    V
    I
    V
    I
    Input  
    V
    M
    V
    M
    V
    M
    V
    M
    0 V  
    0 V  
    VOLTAGE WAVEFORMS  
    PULSE DURATION  
    VOLTAGE WAVEFORMS  
    SETUP AND HOLD TIMES  
    V
    I
    V
    I
    Output  
    Control  
    V
    M
    V
    M
    Input  
    V
    M
    V
    M
    0 V  
    0 V  
    t
    t
    t
    t
    t
    PHL  
    PZL  
    PLZ  
    PLH  
    Output  
    Waveform 1  
    V
    V
    OH  
    V
    V
    /2  
    LOAD  
    V
    V
    V
    M
    M
    Output  
    V
    V
    M
    S1 at V  
    LOAD  
    V
    OL  
    + V  
    ∆
    OL  
    (see Note B)  
    OL  
    t
    PHL  
    PLH  
    t
    t
    PHZ  
    PZH  
    Output  
    Waveform 2  
    S1 at GND  
    V
    V
    OH  
    V
    OH  
    V
    - V  
    ∆
    V
    M
    OH  
    M
    Output  
    M
    ≈0 V  
    OL  
    (see Note B)  
    VOLTAGE WAVEFORMS  
    PROPAGATION DELAY TIMES  
    INVERTING AND NONINVERTING OUTPUTS  
    VOLTAGE WAVEFORMS  
    ENABLE AND DISABLE TIMES  
    LOW- AND HIGH-LEVEL ENABLING  
    NOTES: A. C includes probe and jig capacitance.  
    L
    B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
    Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
    C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.  
    O
    D. The outputs are measured one at a time, with one transition per measurement.  
    E.  
    F.  
    G.  
    t
    t
    t
    and t  
    and t  
    and t  
    are the same as t  
    .
    dis  
    .
    PLZ  
    PZL  
    PLH  
    PHZ  
    are the same as t  
    PZH  
    en  
    are the same as t .  
    PHL pd  
    H. All parameters and waveforms are not applicable to all devices.  
    Figure 1. Load Circuit and Voltage Waveforms  
    6
    PACKAGE OPTION ADDENDUM  
    www.ti.com  
    25-Sep-2013  
    PACKAGING INFORMATION  
    Orderable Device  
    Status Package Type Package Pins Package  
    Eco Plan Lead/Ball Finish  
    MSL Peak Temp  
    Op Temp (°C)  
    Device Marking  
    Samples  
    Drawing  
    Qty  
    (1)  
    (2)  
    (3)  
    (4/5)  
    5962-9760401Q2A  
    ACTIVE  
    LCCC  
    FK  
    20  
    1
    TBD  
    POST-PLATE  
    N / A for Pkg Type  
    -55 to 125  
    5962-  
    9760401Q2A  
    SNJ54LVC  
    02AFK  
    5962-9760401QCA  
    5962-9760401QDA  
    SN74LVC02AD  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    CDIP  
    CFP  
    J
    14  
    14  
    14  
    1
    1
    TBD  
    TBD  
    A42  
    A42  
    N / A for Pkg Type  
    N / A for Pkg Type  
    Level-1-260C-UNLIM  
    -55 to 125  
    -55 to 125  
    -40 to 125  
    5962-9760401QC  
    A
    SNJ54LVC02AJ  
    W
    D
    5962-9760401QD  
    A
    SNJ54LVC02AW  
    SOIC  
    50  
    Green (RoHS  
    & no Sb/Br)  
    CU NIPDAU  
    LVC02A  
    SN74LVC02ADBLE  
    SN74LVC02ADBR  
    OBSOLETE  
    ACTIVE  
    SSOP  
    SSOP  
    DB  
    DB  
    14  
    14  
    TBD  
    Call TI  
    Call TI  
    -40 to 125  
    -40 to 125  
    2000  
    2000  
    50  
    Green (RoHS  
    & no Sb/Br)  
    CU NIPDAU  
    Level-1-260C-UNLIM  
    LC02A  
    SN74LVC02ADBRG4  
    SN74LVC02ADE4  
    SN74LVC02ADG4  
    SN74LVC02ADR  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    SSOP  
    SOIC  
    SOIC  
    SOIC  
    SOIC  
    SOIC  
    SOIC  
    SOIC  
    SOIC  
    SO  
    DB  
    D
    14  
    14  
    14  
    14  
    14  
    14  
    14  
    14  
    14  
    14  
    Green (RoHS  
    & no Sb/Br)  
    CU NIPDAU  
    CU NIPDAU  
    CU NIPDAU  
    CU NIPDAU  
    CU NIPDAU  
    CU NIPDAU  
    CU NIPDAU  
    CU NIPDAU  
    CU NIPDAU  
    CU NIPDAU  
    Level-1-260C-UNLIM  
    Level-1-260C-UNLIM  
    Level-1-260C-UNLIM  
    Level-1-260C-UNLIM  
    Level-1-260C-UNLIM  
    Level-1-260C-UNLIM  
    Level-1-260C-UNLIM  
    Level-1-260C-UNLIM  
    Level-1-260C-UNLIM  
    Level-1-260C-UNLIM  
    -40 to 125  
    -40 to 125  
    -40 to 125  
    -40 to 125  
    -40 to 125  
    -40 to 125  
    -40 to 125  
    -40 to 125  
    -40 to 125  
    -40 to 125  
    LC02A  
    Green (RoHS  
    & no Sb/Br)  
    LVC02A  
    LVC02A  
    LVC02A  
    LVC02A  
    LVC02A  
    LVC02A  
    LVC02A  
    LVC02A  
    LVC02A  
    D
    50  
    Green (RoHS  
    & no Sb/Br)  
    D
    2500  
    2500  
    2500  
    250  
    Green (RoHS  
    & no Sb/Br)  
    SN74LVC02ADRE4  
    SN74LVC02ADRG4  
    SN74LVC02ADT  
    D
    Green (RoHS  
    & no Sb/Br)  
    D
    Green (RoHS  
    & no Sb/Br)  
    D
    Green (RoHS  
    & no Sb/Br)  
    SN74LVC02ADTE4  
    SN74LVC02ADTG4  
    SN74LVC02ANSR  
    D
    250  
    Green (RoHS  
    & no Sb/Br)  
    D
    250  
    Green (RoHS  
    & no Sb/Br)  
    NS  
    2000  
    Green (RoHS  
    & no Sb/Br)  
    Addendum-Page 1  
    PACKAGE OPTION ADDENDUM  
    www.ti.com  
    25-Sep-2013  
    Orderable Device  
    Status Package Type Package Pins Package  
    Eco Plan Lead/Ball Finish  
    MSL Peak Temp  
    Op Temp (°C)  
    -40 to 125  
    -40 to 125  
    -40 to 125  
    -40 to 125  
    -40 to 125  
    Device Marking  
    Samples  
    Drawing  
    Qty  
    (1)  
    (2)  
    (3)  
    (4/5)  
    SN74LVC02ANSRE4  
    SN74LVC02ANSRG4  
    SN74LVC02APW  
    ACTIVE  
    SO  
    NS  
    14  
    14  
    14  
    14  
    14  
    2000  
    Green (RoHS  
    & no Sb/Br)  
    CU NIPDAU  
    CU NIPDAU  
    CU NIPDAU  
    CU NIPDAU  
    CU NIPDAU  
    Level-1-260C-UNLIM  
    Level-1-260C-UNLIM  
    Level-1-260C-UNLIM  
    Level-1-260C-UNLIM  
    Level-1-260C-UNLIM  
    LVC02A  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    SO  
    NS  
    PW  
    PW  
    PW  
    2000  
    90  
    Green (RoHS  
    & no Sb/Br)  
    LVC02A  
    LC02A  
    LC02A  
    LC02A  
    TSSOP  
    TSSOP  
    TSSOP  
    Green (RoHS  
    & no Sb/Br)  
    SN74LVC02APWE4  
    SN74LVC02APWG4  
    90  
    Green (RoHS  
    & no Sb/Br)  
    90  
    Green (RoHS  
    & no Sb/Br)  
    SN74LVC02APWLE  
    SN74LVC02APWR  
    OBSOLETE  
    ACTIVE  
    TSSOP  
    TSSOP  
    PW  
    PW  
    14  
    14  
    TBD  
    Call TI  
    Call TI  
    -40 to 125  
    -40 to 125  
    2000  
    2000  
    2000  
    250  
    Green (RoHS  
    & no Sb/Br)  
    CU NIPDAU  
    Level-1-260C-UNLIM  
    LC02A  
    LC02A  
    LC02A  
    LC02A  
    LC02A  
    LC02A  
    LC02A  
    LC02A  
    SN74LVC02APWRE4  
    SN74LVC02APWRG4  
    SN74LVC02APWT  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    TSSOP  
    TSSOP  
    TSSOP  
    TSSOP  
    TSSOP  
    VQFN  
    PW  
    PW  
    PW  
    PW  
    PW  
    RGY  
    RGY  
    FK  
    14  
    14  
    14  
    14  
    14  
    14  
    14  
    20  
    Green (RoHS  
    & no Sb/Br)  
    CU NIPDAU  
    CU NIPDAU  
    CU NIPDAU  
    CU NIPDAU  
    CU NIPDAU  
    CU NIPDAU  
    CU NIPDAU  
    POST-PLATE  
    Level-1-260C-UNLIM  
    Level-1-260C-UNLIM  
    Level-1-260C-UNLIM  
    Level-1-260C-UNLIM  
    Level-1-260C-UNLIM  
    Level-2-260C-1 YEAR  
    Level-2-260C-1 YEAR  
    N / A for Pkg Type  
    -40 to 125  
    -40 to 125  
    -40 to 125  
    -40 to 125  
    -40 to 125  
    -40 to 125  
    -40 to 125  
    -55 to 125  
    Green (RoHS  
    & no Sb/Br)  
    Green (RoHS  
    & no Sb/Br)  
    SN74LVC02APWTE4  
    SN74LVC02APWTG4  
    SN74LVC02ARGYR  
    SN74LVC02ARGYRG4  
    SNJ54LVC02AFK  
    250  
    Green (RoHS  
    & no Sb/Br)  
    250  
    Green (RoHS  
    & no Sb/Br)  
    3000  
    3000  
    1
    Green (RoHS  
    & no Sb/Br)  
    VQFN  
    Green (RoHS  
    & no Sb/Br)  
    LCCC  
    TBD  
    5962-  
    9760401Q2A  
    SNJ54LVC  
    02AFK  
    SNJ54LVC02AJ  
    SNJ54LVC02AW  
    ACTIVE  
    ACTIVE  
    CDIP  
    CFP  
    J
    14  
    14  
    1
    1
    TBD  
    TBD  
    A42  
    A42  
    N / A for Pkg Type  
    N / A for Pkg Type  
    -55 to 125  
    -55 to 125  
    5962-9760401QC  
    A
    SNJ54LVC02AJ  
    W
    5962-9760401QD  
    A
    SNJ54LVC02AW  
    Addendum-Page 2  
    PACKAGE OPTION ADDENDUM  
    www.ti.com  
    25-Sep-2013  
    (1) The marketing status values are defined as follows:  
    ACTIVE: Product device recommended for new designs.  
    LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
    NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
    PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
    OBSOLETE: TI has discontinued the production of the device.  
    (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
    information and additional product content details.  
    TBD: The Pb-Free/Green conversion plan has not been defined.  
    Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
    lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
    Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
    the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
    Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
    in homogeneous material)  
    (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
    (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
    (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
    of the previous line and the two combined represent the entire Device Marking for that device.  
    Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
    provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
    continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
    TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
    In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
    OTHER QUALIFIED VERSIONS OF SN54LVC02A, SN74LVC02A :  
    Catalog: SN74LVC02A  
    •
    Automotive: SN74LVC02A-Q1, SN74LVC02A-Q1  
    •
    Enhanced Product: SN74LVC02A-EP  
    •
    Addendum-Page 3  
    PACKAGE OPTION ADDENDUM  
    www.ti.com  
    25-Sep-2013  
    Military: SN54LVC02A  
    •
    NOTE: Qualified Version Definitions:  
    Catalog - TI's standard catalog product  
    •
    •
    •
    •
    Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects  
    Enhanced Product - Supports Defense, Aerospace and Medical Applications  
    Military - QML certified for Military and Defense Applications  
    Addendum-Page 4  
    PACKAGE MATERIALS INFORMATION  
    www.ti.com  
    26-Jan-2013  
    TAPE AND REEL INFORMATION  
    *All dimensions are nominal  
    Device  
    Package Package Pins  
    Type Drawing  
    SPQ  
    Reel  
    Reel  
    A0  
    B0  
    K0  
    P1  
    W
    Pin1  
    Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
    (mm) W1 (mm)  
    SN74LVC02ADBR  
    SN74LVC02ADR  
    SN74LVC02ADT  
    SSOP  
    SOIC  
    DB  
    D
    14  
    14  
    14  
    14  
    14  
    14  
    14  
    2000  
    2500  
    250  
    330.0  
    330.0  
    330.0  
    330.0  
    330.0  
    330.0  
    330.0  
    16.4  
    16.4  
    16.4  
    16.4  
    12.4  
    12.4  
    12.4  
    8.2  
    6.5  
    6.5  
    8.2  
    6.9  
    6.9  
    3.75  
    6.6  
    9.0  
    2.5  
    2.1  
    2.1  
    2.5  
    1.6  
    1.6  
    1.15  
    12.0  
    8.0  
    16.0  
    16.0  
    16.0  
    16.0  
    12.0  
    12.0  
    12.0  
    Q1  
    Q1  
    Q1  
    Q1  
    Q1  
    Q1  
    Q1  
    SOIC  
    D
    9.0  
    8.0  
    SN74LVC02ANSR  
    SN74LVC02APWR  
    SN74LVC02APWT  
    SN74LVC02ARGYR  
    SO  
    NS  
    PW  
    PW  
    RGY  
    2000  
    2000  
    250  
    10.5  
    5.6  
    12.0  
    8.0  
    TSSOP  
    TSSOP  
    VQFN  
    5.6  
    8.0  
    3000  
    3.75  
    8.0  
    Pack Materials-Page 1  
    PACKAGE MATERIALS INFORMATION  
    www.ti.com  
    26-Jan-2013  
    *All dimensions are nominal  
    Device  
    Package Type Package Drawing Pins  
    SPQ  
    Length (mm) Width (mm) Height (mm)  
    SN74LVC02ADBR  
    SN74LVC02ADR  
    SN74LVC02ADT  
    SSOP  
    SOIC  
    DB  
    D
    14  
    14  
    14  
    14  
    14  
    14  
    14  
    2000  
    2500  
    250  
    367.0  
    367.0  
    367.0  
    367.0  
    367.0  
    367.0  
    367.0  
    367.0  
    367.0  
    367.0  
    367.0  
    367.0  
    367.0  
    367.0  
    38.0  
    38.0  
    38.0  
    38.0  
    35.0  
    35.0  
    35.0  
    SOIC  
    D
    SN74LVC02ANSR  
    SN74LVC02APWR  
    SN74LVC02APWT  
    SN74LVC02ARGYR  
    SO  
    NS  
    PW  
    PW  
    RGY  
    2000  
    2000  
    250  
    TSSOP  
    TSSOP  
    VQFN  
    3000  
    Pack Materials-Page 2  
    MECHANICAL DATA  
    MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001  
    DB (R-PDSO-G**)  
    PLASTIC SMALL-OUTLINE  
    28 PINS SHOWN  
    0,38  
    0,22  
    0,65  
    28  
    M
    0,15  
    15  
    0,25  
    0,09  
    5,60  
    5,00  
    8,20  
    7,40  
    Gage Plane  
    1
    14  
    0,25  
    A
    0°–ā8°  
    0,95  
    0,55  
    Seating Plane  
    0,10  
    2,00 MAX  
    0,05 MIN  
    PINS **  
    14  
    16  
    20  
    24  
    28  
    30  
    38  
    DIM  
    6,50  
    5,90  
    6,50  
    5,90  
    7,50  
    8,50  
    7,90  
    10,50  
    9,90  
    10,50 12,90  
    A MAX  
    A MIN  
    6,90  
    9,90  
    12,30  
    4040065 /E 12/01  
    NOTES: A. All linear dimensions are in millimeters.  
    B. This drawing is subject to change without notice.  
    C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
    D. Falls within JEDEC MO-150  
    POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
    IMPORTANT NOTICE  
    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
    changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
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    supplied at the time of order acknowledgment.  
    TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
    and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
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    performed.  
    TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
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