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产品型号SN74LVC1G125DCK的概述

芯片SN74LVC1G125DCK的概述 SN74LVC1G125DCK是一款由德州仪器（Texas Instruments，TI）公司生产的单通道四态缓冲器/驱动器。该芯片以其极低的功耗和高电压兼容性而著称，广泛应用于多种数字电路系统，特别是在高速和高密度应用中。作为一种高性能的逻辑器件，SN74LVC1G125DCK能够在逻辑高和逻辑低之间实现稳定的转换，确保信号的完整性与可靠性。芯片SN74LVC1G125DCK的详细参数 SN74LVC1G125DCK的主要技术参数如下： - 电源电压(Vcc)：1.65V 到 5.5V，适应广泛的应用场景。 - 输入电压(IH)：保证逻辑高（输入高电平）的最低电压为0.7×Vcc。 - 输出驱动能力：可驱动大约 -32mA（在Vcc=5V时），输出电流范围使其能够适应多种负载。 - 静态功耗：功耗极低，典型值为 1μA。 - 输入/输出信号...

产品型号SN74LVC1G125DCK的Datasheet PDF文件预览

SN74LVC1G125

SINGLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES223C – APRIL 1999 – REVISED FEBRUARY 2000

DBV OR DCK PACKAGE

(TOP VIEW)

EPIC (Enhanced-Performance Implanted

CMOS) Submicron Process

Feature Supports Partial-Power-Down

off

GND

Mode Operation

Supports 5-V V

Operation

Package Options Include Plastic

Small-Outline Transistor (DBV, DCK)

Packages

description

This bus buffer gate is designed for 1.65-V to 5.5-V V

operation.

The SN74LVC1G125 features a single line driver with a 3-state output. The output is disabled when the

output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,

off

preventing damaging current backflow through the device when it is powered down.

The SN74LVC1G125 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OUTPUT

†

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74LVC1G125

SINGLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES223C – APRIL 1999 – REVISED FEBRUARY 2000

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V

Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V

+ 0.5 V

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA

Output clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA

Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA

Continuous current through V

Package thermal impedance, θ (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347°C/W

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA

DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder“recommendedoperatingconditions”isnotimplied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The value of V is provided in the recommended operating conditions table.

3. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 4)

MIN

1.65

MAX

UNIT

Operating

5.5

Supply voltage

Data retention only

1.5

= 1.65 V to 1.95 V

= 2.3 V to 2.7 V

= 3 V to 3.6 V

0.65 × V

1.7

High-level input voltage

= 4.5 V to 5.5 V

= 1.65 V to 1.95 V

= 2.3 V to 2.7 V

= 3 V to 3.6 V

0.7 × V

0.35 × V

0.7

Low-level input voltage

0.8

= 4.5 V to 5.5 V

0.3 × V

5.5

Input voltage

Output voltage

–4

= 1.65 V

= 2.3 V

–8

High-level output current

Low-level output current

–16

–24

–32

= 3 V

= 4.5 V

= 1.65 V

= 2.3 V

= 3 V

= 4.5 V

= 1.8 V ± 0.15 V, 2.5 V ± 0.2 V

= 3.3 V ± 0.3 V

= 5 V ± 0.5 V

∆t/∆v

Input transition rise or fall rate

Operating free-air temperature

ns/V

–40

°C

NOTE 4: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74LVC1G125

SINGLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES223C – APRIL 1999 – REVISED FEBRUARY 2000

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

†

TYP

PARAMETER

TEST CONDITIONS

MIN

V –0.1

MAX

UNIT

= –100

1.65 V to 5.5 V

1.65 V

= –4 mA

= –8 mA

1.2

1.9

2.4

2.3

2.3 V

= –16 mA

= –24 mA

= –32 mA

3 V

4.5 V

1.65 V to 5.5 V

1.65 V

3.8

= 100

0.1

0.45

0.3

= 4 mA

= 8 mA

2.3 V

= 16 mA

= 24 mA

= 32 mA

0.4

3 V

0.55

4.5 V

0.55

A or OE

inputs

V = 5.5 V or GND

0 to 5.5 V

±5

V or V = 5.5 V

3.6 V

±10

off

= 0 to 5.5 V

V = 5.5 V or GND,

= 0

1.65 V to 5.5 V

3 V to 5.5 V

3.3 V

∆I

One input at V

– 0.6 V,

Other inputs at V

or GND

500

V = V

or GND

= 3.3 V, T = 25°C.

†

All typical values are at V

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figures 1 through 4)

= 1.8 V

= 2.5 V

= 3.3 V

= 5 V

± 0.15 V

± 0.2 V

± 0.3 V

± 0.5 V

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN MAX

MIN

MAX

MIN MAX

dis

operating characteristics, T = 25°C

= 1.8 V

TYP

= 2.5 V

TYP

= 3.3 V

= 5 V

TYP

PARAMETER

TEST CONDITIONS

f = 10 MHz

UNIT

TYP

Power dissipation capacitance

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74LVC1G125

SINGLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES223C – APRIL 1999 – REVISED FEBRUARY 2000

PARAMETER MEASUREMENT INFORMATION

= 1.8 V ± 0.15 V

2 × V

Open

1 kΩ

From Output

Under Test

TEST

GND

Open

= 30 pF

2 × V

GND

PLZ PZL

1 kΩ

(see Note A)

PHZ PZH

LOAD CIRCUIT

Input

Timing

Input

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

Data

Input

Output

Control

0 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

PZL

PLZ

Output

Waveform 1

Input

S1 at 2 × V

(see Note B)

+ 0.15 V

0 V

PZH

PHZ

PLH

PHL

Output

Waveform 2

S1 at GND

– 0.15 V

Output

0 V

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

NOTES: A.

includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.

D. The outputs are measured one at a time with one transition per measurement.

and t

are the same as t

dis

PLZ

PZL

PLH

PHZ

PZH

PHL

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74LVC1G125

SINGLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES223C – APRIL 1999 – REVISED FEBRUARY 2000

PARAMETER MEASUREMENT INFORMATION

= 2.5 V ± 0.2 V

2 × V

Open

500 Ω

From Output

Under Test

TEST

GND

Open

= 30 pF

2 × V

GND

PLZ PZL

500 Ω

(see Note A)

PHZ PZH

LOAD CIRCUIT

Input

Timing

Input

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

Data

Input

Output

Control

0 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

PZL

PLZ

Output

Waveform 1

Input

S1 at 2 × V

(see Note B)

+ 0.15 V

0 V

PZH

PHZ

PLH

PHL

Output

Waveform 2

S1 at GND

– 0.15 V

Output

0 V

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

NOTES: A.

includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.

D. The outputs are measured one at a time with one transition per measurement.

and t

are the same as t

dis

PLZ

PZL

PLH

PHZ

PZH

PHL

Figure 2. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74LVC1G125

SINGLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES223C – APRIL 1999 – REVISED FEBRUARY 2000

PARAMETER MEASUREMENT INFORMATION

= 3.3 V ± 0.3 V

6 V

Open

GND

TEST

500 Ω

Open

6 V

From Output

Under Test

PLZ PZL

GND

PHZ PZH

= 50 pF

500 Ω

(see Note A)

LOAD CIRCUIT

1.5 V

3 V

0 V

1.5 V

Input

3 V

0 V

Timing

Input

VOLTAGE WAVEFORMS

PULSE DURATION

3 V

0 V

Data

Input

1.5 V

3 V

0 V

Output

Control

1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

PLZ

PZL

3 V

Output

Waveform 1

S1 at 6 V

3 V

0 V

1.5 V

Input

1.5 V

+ 0.3 V

(see Note B)

PLH

PHL

PZH

PHZ

– 0.3 V

Output

Waveform 2

S1 at GND

1.5 V

Output

(see Note B)

0 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

ENABLE AND DISABLE TIMES

NOTES: A.

includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

and t

are the same as t

dis

PLZ

PZL

PLH

PHZ

PZH

PHL

Figure 3. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74LVC1G125

SINGLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES223C – APRIL 1999 – REVISED FEBRUARY 2000

PARAMETER MEASUREMENT INFORMATION

= 5 V ± 0.5 V

11 V

Open

GND

500 Ω

From Output

Under Test

TEST

Open

11 V

PLH PHL

= 50 pF

500 Ω

PLZ PZL

(see Note A)

GND

PHZ PZH

LOAD CIRCUIT

Timing Input

Data Input

0 V

Input

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Output

Control

Input

0 V

PHL

PZL

PLZ

PLH

PHL

Output

Waveform 1

S1 at 11 V

5.5 V

Output

+ 0.3 V

PHZ

(see Note B)

PLH

PZH

Output

Waveform 2

S1 at GND

– 0.3 V

Output

≈ 0 V

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A.

C includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

and t

are the same as t

PLZ

PZL

PLH

PHZ

PZH

PHL

dis

Figure 4. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

SN74LVC1G125DCK相关文章

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SN74LVC1G125DCK产品参数

型号:	SN74LVC1G125DCK
是否Rohs认证：	不符合
生命周期：	Obsolete
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	SOT
包装说明：	PLASTIC, SOT-5
针数：	5
Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01
风险等级：	5.27
Is Samacsys：	N
控制类型：	ENABLE LOW
系列：	LVC/LCX/Z
JESD-30 代码：	R-PDSO-G5
长度：	2 mm
负载电容（CL）：	50 pF
逻辑集成电路类型：	BUS DRIVER
最大I（ol）：	0.024 A
位数：	1
功能数量：	1
端口数量：	2
端子数量：	5
最高工作温度：	85 °C
最低工作温度：	-40 °C
输出特性：	3-STATE
输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP
封装等效代码：	TSSOP5/6,.08
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V
传播延迟（tpd）：	9 ns
认证状态：	Not Qualified
座面最大高度：	1.1 mm
子类别：	Bus Driver/Transceivers
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	1.65 V
标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	1.25 mm
Base Number Matches：	1

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产品型号SN74LVC1G125DCK的概述

产品型号SN74LVC1G125DCK的Datasheet PDF文件预览

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