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SN74LVC32A-EP

QUADRUPLE 2-INPUT POSITIVE-OR GATE

www.ti.com

SCAS733C–NOVEMBER 2003–REVISED MARCH 2007

FEATURES

•

Inputs Accept Voltages to 5.5 V

Max t_pdof 3.8 ns at 3.3 V

•

Controlled Baseline

–

One Assembly/Test Site, One Fabrication

Site

Typical V_OLP(Output Ground Bounce)

<0.8 V at V_CC= 3.3 V, T_A= 25°C

•

Extended Temperature Performance of

–40°C to 125°C and –55°C to 125°C

•

Typical V_OHV(Output V_OHUndershoot)

>2 V at V_CC= 3.3 V, T_A= 25°C

Enhanced Diminishing Manufacturing Sources

(DMS) Support

ESD Protection Exceeds JESD 22

–

2000-V Human-Body Model (A114-A)

200-V Machine Model (A115-A)

•

Enhanced Product-Change Notification

(1)

Qualification Pedigree

1000-V Charged-Device Model (C101)

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

D OR PW PACKAGE

(TOP VIEW)

•

Operates From 2 V to 3.6 V

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

GND

DESCRIPTION/ORDERING INFORMATION

The SN74LVC32A quadruple 2-input positive-OR gate is designed for 2.7-V to 3.6-V V_CCoperation.

Y + A ) B or Y + A • B

The device performs the Boolean function

in positive logic.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in

a mixed 3.3-V/5-V system environment.

ORDERING INFORMATION⁽¹⁾

T_A

PACKAGE⁽²⁾

ORDERABLE PART NUMBER

SN74LVC32AQDREP

TOP-SIDE MARKING

LVC32AE

SOIC – D

Reel of 2500

–40°C to 125°C

TSSOP – PW

SOIC – D

Reel of 2000

Reel of 2500

Reel of 2000

SN74LVC32AQPWREP

SN74LVC32AMDREP

LVC32AE

LVC32AM

–55°C to 125°C

TSSOP – PW

SN74LVC32AMPWREP

LVC32AM

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

FUNCTION TABLE

(EACH GATE)

INPUTS

OUTPUT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

On products compliant to MIL-PRF-38535, all parameters are

Instruments standard warranty. Production processing does not

tested unless otherwise noted. On all other products, production

necessarily include testing of all parameters.

processing does not necessarily include testing of all parameters.

SN74LVC32A-EP

QUADRUPLE 2-INPUT POSITIVE-OR GATE

www.ti.com

SCAS733C–NOVEMBER 2003–REVISED MARCH 2007

LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)

Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.5

MAX UNIT

V_CC

V_I

Supply voltage range

Input voltage range⁽²⁾

Output voltage range⁽²⁾⁽³⁾

6.5

V_O

I_IK

V_CC+ 0.5

–50

Input clamp current

V_I< 0 V

I_OK

I_O

Output clamp current

V_O< 0 V

–50

Continuous output current

Continuous current through V_CCor GND

±50

±100

D package

θ_JA

Package thermal impedance⁽⁴⁾

Storage temperature range

°C/W

°C

PW package

113

T_stg

–65

150

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The value of V_CCis provided in the recommended operating conditions table.

(4) The package thermal impedance is calculated in accordance with JESD 51-7.

Recommended Operating Conditions⁽¹⁾⁽²⁾

MIN

MAX UNIT

Operating

3.6

V_CC

Supply voltage

Data retention only

V_CC= 2.7 V to 3.6 V

1.5

V_IH

V_IL

V_I

High-level input voltage

Low-level input voltage

Input voltage

0.8

5.5

V_CC

–12

–24

V_O

Output voltage

V_CC= 2.7 V

V_CC= 3 V

V_CC= 2.7 V

V_CC= 3 V

I_OH

High-level output current

I_OL

Low-level output current

ns/V

°C

∆t/∆v

T_A

Input transition rise or fall rate

Operating free-air temperature

M suffix

Q suffix

–55

–40

125

(1) All unused inputs of the device must be held at V_CCor GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

(2) Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of

overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.

Submit Documentation Feedback

SN74LVC32A-EP

QUADRUPLE 2-INPUT POSITIVE-OR GATE

www.ti.com

SCAS733C–NOVEMBER 2003–REVISED MARCH 2007

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

2.7 V to 3.6 V

2.7 V

MIN TYP⁽¹⁾

V_CC– 0.2

MAX UNIT

I_OH= –100 µA

2.2

2.4

2.2

V_OH

I_OH= –12 mA

3 V

I_OH= –24 mA

I_OL= 100 µA

I_OL= 12 mA

3 V

2.7 V to 3.6 V

2.7 V

0.2

V_OL

0.4

0.55

±5

I_OL= 24 mA

3 V

I_I

V_I= 5.5 V or GND

3.6 V

µA

I_CC

∆I_CC

C_i

V_I= V_CCor GND, I_O= 0

3.6 V

One input at V_CC– 0.6 V, Other inputs at V_CCor GND

V_I= V_CCor GND

2.7 V to 3.6 V

3.3 V

500

(1) All typical values are at V_CC= 3.3 V, T_A= 25°C.

Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)

V_CC= 3.3 V

± 0.3 V

V_CC= 2.7 V

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN

MAX

MIN

MAX

3.8

t_pd

A or B

4.4

Operating Characteristics

T_A= 25°C

V_CC= 2.5 V

TYP

V_CC= 3.3 V

TYP

PARAMETER

Power dissipation capacitance per gate

TEST CONDITIONS

UNIT

C_pd

f = 10 MHz

10.6

12.5

Submit Documentation Feedback

SN74LVC32A-EP

QUADRUPLE 2-INPUT POSITIVE-OR GATE

www.ti.com

SCAS733C–NOVEMBER 2003–REVISED MARCH 2007

PARAMETER MEASUREMENT INFORMATION

LOAD

Open

From Output

Under Test

TEST

GND

Open

PLH PHL

PLZ PZL

LOAD

GND

(see Note A)

PHZ PZH

LOAD CIRCUIT

INPUTS

LOAD

∆

t /t

r f

2.7 V

≤2.5 ns

1.5 V

6 V

50 pF

500 Ω

0.3 V

3.3 V ± 0.3 V

Timing Input

Data Input

0 V

Input

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Output

Control

Input

0 V

PHL

PZL

PLZ

PLH

Output

Waveform 1

LOAD

Output

S1 at V

LOAD

+ V

∆

(see Note B)

PHL

PLH

PHZ

PZH

Output

Waveform 2

S1 at GND

- V

∆

Output

≈0 V

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A. C includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.

D. The outputs are measured one at a time, with one transition per measurement.

and t

are the same as t

dis

PLZ

PZL

PLH

PHZ

are the same as t

PZH

are the same as t .

PHL pd

H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

Submit Documentation Feedback

PACKAGE OPTION ADDENDUM

www.ti.com

22-Sep-2008

PACKAGING INFORMATION

Orderable Device

SN74LVC32AMDREP

SN74LVC32AMPWREP

SN74LVC32AMPWREPG4

SN74LVC32AQDREP

SN74LVC32AQPWREP

V62/04661-01XE

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

SOIC

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

SOIC

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

V62/04661-01YE

TSSOP

SOIC

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

V62/04661-02XE

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

V62/04661-02YE

TSSOP

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC32A-EP :

Catalog: SN74LVC32A

•

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

22-Sep-2008

Automotive: SN74LVC32A-Q1

Military: SN54LVC32A

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Military - QML certified for Military and Defense Applications

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74LVC32AMDREP

SOIC

2500

2000

2500

2000

330.0

16.4

12.4

16.4

12.4

6.5

6.9

6.5

6.9

9.0

5.6

9.0

5.6

2.1

1.6

2.1

1.6

8.0

16.0

12.0

16.0

12.0

SN74LVC32AMPWREP TSSOP

SN74LVC32AQDREP SOIC

SN74LVC32AQPWREP TSSOP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74LVC32AMDREP

SN74LVC32AMPWREP

SN74LVC32AQDREP

SN74LVC32AQPWREP

SOIC

TSSOP

SOIC

2500

2000

2500

2000

367.0

333.2

367.0

345.9

367.0

38.0

35.0

28.6

35.0

TSSOP

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All

semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

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harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

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In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which

have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such

components to meet such requirements.

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SN74LVC32AMDREP产品参数

型号:	SN74LVC32AMDREP
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	SOIC
包装说明：	SOP, SOP14,.25
针数：	14
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	0.83
系列：	LVC/LCX/Z
JESD-30 代码：	R-PDSO-G14
JESD-609代码：	e4
长度：	8.65 mm
负载电容（CL）：	50 pF
逻辑集成电路类型：	OR GATE
最大I（ol）：	0.024 A
湿度敏感等级：	1
功能数量：	4
输入次数：	2
端子数量：	14
最高工作温度：	125 °C
最低工作温度：	-55 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP14,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
包装方法：	TR
峰值回流温度（摄氏度）：	260
电源：	3.3 V
最大电源电流（ICC）：	0.01 mA
Prop。Delay @ Nom-Sup：	3.8 ns
传播延迟（tpd）：	4.4 ns
认证状态：	Not Qualified
施密特触发器：	NO
座面最大高度：	1.75 mm
子类别：	Gates
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	2 V
标称供电电压 (Vsup)：	2.7 V
表面贴装：	YES
技术：	CMOS
温度等级：	MILITARY
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm

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