SNJ54173各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

SN54173, SN54LS173A, SN74173, SN74LS173A

4-BIT D-TYPE REGISTERS

WITH 3-STATE OUTPUTS

SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

SN54173, SN54LS173A . . . J OR W PACKAGE

SN74173 . . . N PACKAGE

3-State Outputs Interface Directly With

System Bus

SN74LS173A . . . D or N PACKAGE

(TOP VIEW)

Gated Output-Control LInes for Enabling or

Disabling the Outputs

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

M

N

V

CC

Fully Independent Clock Virtually

Eliminates Restrictions for Operating in

One of Two Modes:

– Parallel Load

– Do Nothing (Hold)

CLR

1D

2D

3D

4D

G2

G1

1Q

2Q

3Q

4Q

For Application as Bus Buffer Registers

CLK

GND

Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Flat

(W) Packages, Ceramic Chip Carriers (FK),

and Standard Plastic (N) and Ceramic (J)

DIPs

SN54LS173A . . . FK PACKAGE

(TOP VIEW)

TYPICAL

PROPAGATION

DELAY TIME

MAXIMUM

CLOCK

FREQUENCY

TYPE

3

2

1 20 19

18

1D

2D

NC

3D

4D

1Q

2Q

NC

3Q

4Q

4

5

6

7

8

’173

23 ns

18 ns

35 MHz

50 MHz

17

16

15

14

’LS173A

description

9 10 11 12 13

The ’173 and ’LS173A 4-bit registers include

D-type flip-flops featuring totem-pole 3-state

outputs capable of driving highly capacitive

or relatively low-impedance loads. The

high-impedance third state and increased

high-logic-level drive provide these flip-flops with

the capability of being connected directly to and

NC – No internal connection

driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of

the SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or

54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can

be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load,

respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic

levels, the output control circuitry is designed so that the average output disable times are shorter than the

average output enable times.

Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both

data-enable (G1, G2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next

positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both

are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus

lines. The outputs are disabled independently from the level of the clock by a high logic level at either

output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed

operation is given in the function table.

The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of

–55°C to 125°C. The SN74173 and SN74LS173A are characterized for operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54173, SN54LS173A, SN74173, SN74LS173A

4-BIT D-TYPE REGISTERS

WITH 3-STATE OUTPUTS

SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

FUNCTION TABLE

INPUTS

OUTPUT

Q

DATA ENABLE

DATA

D

CLR

CLK

G1

X

G2

X

H

L

X

L

↑

X

L

X

Q

0

H

X

↑

X

H

L

↑

L

H

When either M or N (or both) is (are) high, the output is

disabled to the high-impedance state; however, sequential

operation of the flip-flops is not affected.

†

logic symbol

’173

’LS173A

15

CLR

1

R

CLR

M

R

1

&

M

2

EN

C1

EN

C1

N

9

&

G1

10

G2

7

G1

G2

10

7

CLK

14

1D

3

4

5

6

14

13

12

11

3

4

5

6

1D

1Q

2Q

3Q

4Q

1D

2D

3D

4D

1D

1Q

2Q

3Q

4Q

13

2D

12

3D

11

4D

†

This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.

Pin numbers shown are for D, J, N, and W packages.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54173, SN54LS173A, SN74173, SN74LS173A

4-BIT D-TYPE REGISTERS

WITH 3-STATE OUTPUTS

SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

logic diagram (positive logic)

1

M

Output

Control

2

N

1D

14

1D

C1

9

G1

3

Data

Enable

R

1Q

10

G2

1D

13

2D

C1

4

5

6

R

2Q

7

CLK

1D

12

3D

C1

R

3Q

1D

11

4D

C1

R

4Q

15

CLR

Pin numbers shown are for D, J, N, and W packages.

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54173, SN54LS173A, SN74173, SN74LS173A

4-BIT D-TYPE REGISTERS

WITH 3-STATE OUTPUTS

SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

schematics of inputs and outputs

’173

’LS173A

Equivalent of Each Input

V

CC

V

CC

4 kΩ NOM

20 kΩ NOM

Input

Typical of All Outputs

V

CC

V

CC

90 Ω NOM

100 Ω NOM

Output

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V

CC

Input voltage: ’173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V

’LS173A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V

Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V

Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W

JA

N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Voltage values are with respect to network ground terminal.

2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace

length of zero.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54173, SN54LS173A, SN74173, SN74LS173A

4-BIT D-TYPE REGISTERS

WITH 3-STATE OUTPUTS

SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

recommended operating conditions (see Note 3)

SN54173

SN74173

UNIT

MIN NOM

MAX

5.5

–2

MIN NOM

MAX

5.25

–5.2

16

V

Supply voltage

4.5

5

4.75

5

V

CC

OH

OL

I

High-level output current

Low-level output current

Operating free-air temperature

mA

°C

16

T

A

–55

125

0

70

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54173

SN74173

†

PARAMETER

UNIT

TEST CONDITIONS

‡

MIN TYP

MAX

MIN TYP

MAX

V

High-level input voltage

Low-level input voltage

Input clamp voltage

2

V

IH

0.8

IL

V

= MIN,

I = –12 mA

–1.5

IK

CC

I

V

= 2 V,

= MAX

CC

IL

IH

V

High-level output voltage

Low-level output voltage

2.4

V

OH

OL

= 0.8 V,

I

OH

V

= MIN,

= 0.8 V,

V

= 2 V,

= 16 mA

CC

IL

IH

V

0.4

I

OL

V

= 2.4 V

= 0.4 V

150

40

Off-state (high-impedance state)

output current

V

= MAX,

= 2 V

O

CC

IH

I

µA

O(off)

I

V

–150

–40

Input current

at maximum input voltage

V

CC

= MAX,

V = 5.5 V

I

1

mA

I

High-level input current

Low-level input current

V

CC

V

CC

V

CC

V

CC

= MAX,

= MAX

= MAX,

V = 2.4 V

40

–1.6

–70

72

40

–1.6

–70

72

µA

mA

IH

I

V = 0.4 V

I

IL

§

Short-circuit output current

Supply current

–30

OS

CC

See Note 4

50

†

‡

§

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

All typical values are at V = 5 V, T = 25°C.

Not more than one output should be shorted at a time.

CC

A

NOTE 4:

I

ismeasuredwithalloutputsopen;CLRgrounded,followingmomentaryconnectionto4.5V, N, G1, G2,andalldatainputsgrounded;

CC

and CLK and M at 4.5 V.

timing requirements over recommended operating conditions (unless otherwise noted)

SN54173

SN74173

UNIT

MIN

MAX

25

MIN

MAX

25

f

t

Input clock frequency

Pulse duration

MHz

ns

clock

CLK or CLR

20

17

10

2

20

17

10

2

w

Data enable (G1, G2)

Data

t

Setup time

Hold time

ns

su

h

CLR (inactive state)

Data enable (G1, G2)

Data

t

10

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54173, SN54LS173A, SN74173, SN74LS173A

4-BIT D-TYPE REGISTERS

WITH 3-STATE OUTPUTS

SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

switching characteristics, V

= 5 V, T = 25°C, R = 400 Ω (see Figure 1)

A L

CC

SN54173

TYP

SN74173

TYP

PARAMETER

TEST CONDITIONS

UNIT

MIN

MAX

MIN

MAX

Maximum clock frequency

Propagation delay time,

25

35

25

35

MHz

ns

f

t

max

18

28

19

27

43

31

18

28

19

27

43

31

PHL

high-to-low-level output from clear input

Propagation delay time,

low-to-high-level output from clock input

t

PLH

C

= 50 pF

L

ns

Propagation delay time,

high-to-low-level output from clock input

PHL

Output enable time to high level

Output enable time to low level

Output disable time from high level

Output disable time from low level

7

3

16

21

5

30

14

20

7

3

16

21

5

30

14

20

t

PZH

PZL

PHZ

PLZ

ns

C

= 5 pF

L

11

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54173, SN54LS173A, SN74173, SN74LS173A

4-BIT D-TYPE REGISTERS

WITH 3-STATE OUTPUTS

SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

recommended operating conditions

SN54LS173A

MIN NOM MAX

SN74LS173A

MIN NOM MAX

UNIT

V

Supply voltage

4.5

5

5.5

–1

4.75

5

5.25

–2.6

24

V

CC

OH

OL

I

High-level output current

Low-level output current

Operating free-air temperature

mA

°C

12

T

A

–55

125

0

70

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54LS173A

SN74LS173A

UNIT

V

†

PARAMETER

TEST CONDITIONS

‡

MIN TYP

MAX

MIN TYP

MAX

V

High-level input voltage

Low-level input voltage

Input clamp voltage

2

IH

0.7

0.8

V

IL

V

= MIN,

= V max,

IL

I = –18 mA

–1.5

V

IK

CC

I

V

= 2 V,

= MAX

CC

IH

V

High-level output voltage

Low-level output voltage

2.4

3.4

2.4

3.1

V

OH

OL

I

IL

OH

= 12 mA

= 24 mA

= 2.7 V

= 0.4 V

0.25

0.4

0.25

0.35

0.4

0.5

20

V

= MIN,

= 0.8 V,

OL

CC

V

IL

V

20

Off-state (high-impedance state)

output current

V

= MAX,

= 2 V

O

CC

I

V

O(off)

V

–20

IH

Input current

at maximum input voltage

V

CC

= MAX,

V = 7 V

I

0.1

mA

I

High-level input current

Low-level input current

V

CC

V

CC

V

CC

V

CC

= MAX,

= MAX

= MAX,

V = 2.7 V

20

–0.4

–130

30

20

–0.4

–130

24

µA

mA

IH

I

V = 0.4 V

I

IL

§

Short-circuit output current

Supply current

–30

OS

CC

See Note 4

19

†

‡

§

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

All typical values are at V = 5 V, T = 25°C.

Not more than one output should be shorted at a time.

CC

A

NOTE 4:

I

ismeasuredwithalloutputsopen;CLRgrounded,followingmomentaryconnectionto4.5V, N, G1, G2,andalldatainputsgrounded;

CC

and CLK and M at 4.5 V.

timing requirements over recommended operating conditions (unless otherwise noted)

SN54LS173A SN74LS173A

UNIT

MIN

MAX

MIN

MAX

f

t

Input clock frequency

Pulse duration

30

25

MHz

ns

clock

CLK or CLR

25

35

17

10

0

25

35

17

10

0

w

Data enable (G1, G2)

Data

t

Setup time

Hold time

ns

su

h

CLR (inactive state)

Data enable (G1, G2)

Data

t

3

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54173, SN54LS173A, SN74173, SN74LS173A

4-BIT D-TYPE REGISTERS

WITH 3-STATE OUTPUTS

SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

switching characteristics, V

= 5 V, T = 25°C, R = 667 Ω (see Figure 2)

A L

CC

SN54LS173A

SN74LS173A

PARAMETER

TEST CONDITIONS

UNIT

MIN

30

TYP

MAX

MIN

30

TYP

MAX

Maximum clock frequency

Propagation delay time,

50

MHz

ns

f

t

max

26

17

22

35

25

30

26

17

22

35

25

30

PHL

high-to-low-level output from clear input

Propagation delay time,

low-to-high-level output from clock input

t

PLH

C

= 45 pF

L

ns

Propagation delay time,

high-to-low-level output from clock input

PHL

Output enable time to high level

Output enable time to low level

Output disable time from high level

Output disable time from low level

15

18

11

23

27

20

17

15

18

11

23

27

20

17

t

PZH

PZL

PHZ

PLZ

ns

C

= 5 pF

L

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54173, SN54LS173A, SN74173, SN74LS173A

4-BIT D-TYPE REGISTERS

WITH 3-STATE OUTPUTS

SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

PARAMETER MEASUREMENT INFORMATION

SERIES 54/74 AND 54S/74S DEVICES

V

CC

Test

R

L

V

CC

Point

Test

S1

Point

V

CC

From Output

Under Test

(see

Note B)

R

L

R

L

C

L

From Output

Under Test

1 kΩ

(see Note B)

(see Note A)

From Output

Under Test

Test

Point

C

L

(see Note A)

C

L

(see Note A)

S2

LOAD CIRCUIT

FOR 2-STATE TOTEM-POLE OUTPUTS

FOR OPEN-COLLECTOR OUTPUTS

FOR 3-STATE OUTPUTS

3 V

0 V

High-Level

Timing

Input

1.5 V

Pulse

t

w

t

su

h

3 V

Data

Input

Low-Level

Pulse

1.5 V

0 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Output

3 V

Control

(low-level

enabling)

1.5 V

0 V

3 V

0 V

1.5 V

Input

t

PZL

PLZ

≈1.5 V

t

PHL

PLH

Waveform 1

(see Notes C

and D)

1.5 V

In-Phase

Output

(see Note D)

V

OH

OL

V

OL

V

OL

+ 0.5 V

1.5 V

V

t

PZH

PHZ

t

PHL

PLH

V

OH

V

OH

Out-of-Phase

Output

V

Waveform 2

(see Notes C

and D)

OH

OL

– 0.5 V

1.5 V

(see Note D)

V

≈1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A.

C includes probe and jig capacitance.

L

B. All diodes are 1N3064 or equivalent.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. S1 and S2 are closed for t

, t

, and t

; S1 is open and S2 is closed for t

PLZ PZH

; S1 is closed and S2 is open for t

.

PLH PHL PHZ

PZL

E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω, t and t ≤ 7 ns for Series

O

r

f

54/74 devices and t and t ≤ 2.5 ns for Series 54S/74S devices.

r

f

F. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54173, SN54LS173A, SN74173, SN74LS173A

4-BIT D-TYPE REGISTERS

WITH 3-STATE OUTPUTS

SDLS067A – OCTOBER 1976 – REVISED JUNE 1999

PARAMETER MEASUREMENT INFORMATION

SERIES 54LS/74LS DEVICES

V

CC

V

CC

Test

Point

Test

Point

R

L

S1

V

CC

R

L

(see

Note B)

From Output

Under Test

From Output

Under Test

(see Note B)

R

L

C

L

5 kΩ

From Output

Under Test

Test

Point

(see Note A)

C

L

(see Note A)

C

L

(see Note A)

S2

LOAD CIRCUIT FOR

2-STATE

TOTEM-POLE OUTPUTS

LOAD CIRCUIT

FOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

3 V

High-Level

Timing

Input

1.3 V

Pulse

0 V

t

w

t

h

t

su

3 V

0 V

Data

Input

Low-Level

Pulse

1.3 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Output

3 V

0 V

Control

(low-level

enabling)

1.3 V

3 V

0 V

1.3 V

Input

t

PZL

PLZ

≈1.5 V

Waveform 1

S2 Open

(see Notes C

and D)

t

PLH

PHL

1.3 V

V

In-Phase

Output

(see Note D)

OH

OL

V

OL

V

OL

+ 0.3 V

1.3 V

V

t

PZH

PHZ

t

PHL

PLH

V

OH

V

OH

Waveform 2

S2 Closed

(see Notes C

and D)

V

Out-of-Phase

Output

(see Note D)

– 0.3 V

OH

OL

1.3 V

V

≈1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A.

C includes probe and jig capacitance.

L

B. All diodes are 1N3064 or equivalent.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. S1 and S2 are closed for t

, t

, and t

; S1 is open and S2 is closed for t

PLZ PZH

; S1 is closed and S2 is open for t .

PLH PHL PHZ

PZL

E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.

F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω, t ≤ 15 ns, t ≤ 6 ns.

O

r

f

G. The outputs are measured one at a time with one input transition per measurement.

Figure 2. Load Circuits and Voltage Waveforms

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

26-Sep-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

LCCC

CDIP

CFP

Drawing

JM38510/36101B2A

JM38510/36101BEA

JM38510/36101BFA

JM38510/36101SEA

JM38510/36101SFA

SN54173J

ACTIVE

OBSOLETE

ACTIVE

FK

J

20

16

1

TBD

Call TI

Level-NC-NC-NC

Call TI

W

J

CDIP

CFP

W

J

CDIP

PDIP

SOIC

SN54LS173AJ

J

SN74173N

N

D

SN74LS173AD

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LS173ADE4

SN74LS173ADR

SN74LS173ADRE4

SN74LS173AN

ACTIVE

SOIC

PDIP

SO

D

16

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

N

25

Pb-Free

(RoHS)

CU NIPDAU Level-NC-NC-NC

SN74LS173ANE4

SN74LS173ANSR

SN74LS173ANSRE4

N

25

Pb-Free

(RoHS)

CU NIPDAU Level-NC-NC-NC

NS

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SNJ54173J

SNJ54173W

ACTIVE

OBSOLETE

ACTIVE

CDIP

CFP

J

W

FK

J

16

20

16

1

TBD

Call TI

Level-NC-NC-NC

Call TI

SNJ54LS173AFK

SNJ54LS173AJ

SNJ54LS173AW

LCCC

CDIP

CFP

1

Level-NC-NC-NC

ACTIVE

W

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

26-Sep-2005

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

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Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

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Applications

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Amplifiers

amplifier.ti.com

www.ti.com/audio

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dsp.ti.com

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Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

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Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

型号:	SNJ54173J
Brand Name：	Texas Instruments
生命周期：	Active
零件包装代码：	DIP
包装说明：	DIP, DIP16,.3
针数：	16
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.4
其他特性：	WITH HOLD MODE; WITH DUAL OUTPUT ENABLE; DISABLE TIME CL = 5PF
系列：	54
JESD-30 代码：	R-GDIP-T16
长度：	19.56 mm
负载电容（CL）：	50 pF
逻辑集成电路类型：	D FLIP-FLOP
最大频率@ Nom-Sup：	25000000 Hz
最大I（ol）：	0.016 A
位数：	4
功能数量：	1
端子数量：	16
最高工作温度：	125 °C
最低工作温度：	-55 °C
输出特性：	3-STATE
输出极性：	TRUE
封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DIP
封装等效代码：	DIP16,.3
封装形状：	RECTANGULAR
封装形式：	IN-LINE
包装方法：	TUBE
峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V
最大电源电流（ICC）：	72 mA
Prop。Delay @ Nom-Sup：	43 ns
传播延迟（tpd）：	43 ns
认证状态：	Not Qualified
筛选级别：	MIL-PRF-38535
座面最大高度：	5.08 mm
子类别：	FF/Latch
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	NO
技术：	TTL
温度等级：	MILITARY
端子形式：	THROUGH-HOLE
端子节距：	2.54 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
触发器类型：	POSITIVE EDGE
宽度：	7.62 mm
最小 fmax：	25 MHz
Base Number Matches：	1

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