SST39VF801C-70-4C-B3KE-T技术参数全新原装原理图各脚功能电路原理-中国IC网-芯三七

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

The SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C are 512K

x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST proprietary,

high performance CMOS SuperFlash® technology. The split-gate cell design and

thick-oxide tunneling injector attain better reliability and manufacturability com-

pared with alternate approaches. The SST39VF801C / SST39VF802C /

SST39LF801C / SST39LF802C write (Program or Erase) with a 2.7-3.6V power

supply. These devices conforms to JEDEC standard pinouts for x16 memories.

Features

• Organized as 512K x16

• Security-ID Feature

– SST: 128 bits; User: 128 words

• Single Voltage Read and Write Operations

• Fast Read Access Time:

– 2.7-3.6V for SST39VF801C/802C

– 3.0-3.6V for SST39LF801C/802C

– 70 ns for SST39VF801C/802C

– 55 ns for SST39LF801C/802C

• Superior Reliability

• Fast Erase and Word-Program:

– Endurance: 100,000 Cycles (Typical)

– Greater than 100 years Data Retention

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 40 ms (typical)

– Word-Program Time: 7 µs (typical)

• Low Power Consumption (typical values at 5 MHz)

– Active Current: 5 mA (typical)

– Standby Current: 3 µA (typical)

– Auto Low Power Mode: 3 µA (typical)

• Automatic Write Timing

– Internal V_PPGeneration

• Hardware Block-Protection/WP# Input Pin

• End-of-Write Detection

– Top Block-Protection (top 8 KWord)

– Bottom Block-Protection (bottom 8 KWord)

– Toggle Bits

– Data# Polling

– Ready/Busy# Pin

• Sector-Erase Capability

– Uniform 2 KWord sectors

• CMOS I/O Compatibility

• Block-Erase Capability

• JEDEC Standard

– Flexible block architecture; one 8-, two 4-, one 16-, and

fifteen 32-KWord blocks

– Flash EEPROM Pinouts and command sets

• Chip-Erase Capability

• Packages Available

– 48-lead TSOP (12mm x 20mm)

– 48-ball TFBGA (6mm x 8mm)

– 48-ball WFBGA (4mm x 6mm)

• Erase-Suspend/Erase-Resume Capabilities

• Hardware Reset Pin (RST#)

• Latched Address and Data

• All devices are RoHS compliant

www.microchip.com

DS25041A

05/11

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Product Description

The SST39VF801C/802C and SST39LF801C/802C devices are 512K x16 CMOS Multi-Purpose Flash

Plus (MPF+) manufactured with SST proprietary, high performance CMOS SuperFlash technology.

The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability

compared with alternate approaches. The SST39VF801C/802C and SST39LF801C/802C write (Program

or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16

memories.

Featuring high performance Word-Program, the SST39VF801C/802C and SST39LF801C/802C

devices provide a typical Word-Program time of 7 µsec. These devices use Toggle Bit, Data# Polling,

or the RY/BY# pin to indicate the completion of Program operation. To protect against inadvertent

write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured,

and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical

endurance of 100,000 cycles. Data retention is rated at greater than 100 years.

The SST39VF801C/802C and SST39LF801C/802C devices are suited for applications that require

convenient and economical updating of program, configuration, or data memory. For all system appli-

cations, they significantly improve performance and reliability, while lowering power consumption. They

inherently use less energy during Erase and Program than alternative flash technologies. The total

energy consumed is a function of the applied voltage, current, and time of application. Since for any

given voltage range, the SuperFlash technology uses less current to program and has a shorter erase

time, the total energy consumed during any Erase or Program operation is less than alternative flash

technologies. These devices also improve flexibility while lowering the cost for program, data, and con-

figuration storage applications.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of

Erase/Program cycles that have occurred. Therefore the system software or hardware does not have

to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro-

gram times increase with accumulated Erase/Program cycles.

To meet high density, surface mount requirements, the SST39VF801C/802C and SST39LF801C/802C

are offered in 48-lead TSOP, 48-ball TFBGA, and 48-ball WFBGA packages. See Figures 2, 3, and 4

for pin assignments.

DS25041A

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2

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Block Diagrams

SuperFlash

Memory

X-Decoder

Memory Address

Address Buffer Latches

Y-Decoder

CE#

OE#

WE#

WP#

I/O Buffers and Data Latches

DQ - DQ

Control Logic

RESET#

RY/BY#

15

0

1434 B1.0

Figure 1: Functional Block Diagram

DS25041A

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8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Pin Assignment

A16

NC

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A15

A14

A13

A12

A11

A10

A9

A8

NC

V

DQ15

SS

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

Standard Pinout

Top View

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RST#

NC

WP#

RY/BY#

A18

A17

A7

V

DD

Die Up

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

A6

A5

A4

A3

A2

A1

V

SS

CE#

A0

1434 48-tsop EK P1.0

Figure 2: Pin Assignments for 48-Lead TSOP

TOP VIEW (balls facing down)

6

5

4

3

2

1

A13 A12 A14 A15 A16 NC DQ15 V

SS

A8 A10 A11 DQ7 DQ14 DQ13 DQ6

WE# RST# NC NC DQ5 DQ12 DQ4

RY/BY#WP# A18 NC DQ2 DQ10 DQ11 DQ3

A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1

A9

V

DD

A3

A4

A2

A1

A0 CE# OE# V

SS

A

B

C

D

E F G H

1434 48-tfbga B3K P2.0

Figure 3: Pin Assignments for 48-Ball TFBGA

DS25041A

05/11

4

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

TOP VIEW (balls facing down)

6

A2

A1

A0

A4

A3

A6 A17 NC NC WE# RST# A9 A11

A7 WP# RY/BY# A10 A13 A14

5

4

3

2

1

A5 A18

A8 A12 A15

DQ4 DQ11 A16

CE# DQ8 DQ10

V

OE# DQ9 NC

NC DQ5 DQ6 DQ7

SS

DQ0 DQ1 DQ2 DQ3

V

DQ12 DQ13 DQ14 DQ15 V

DD SS

A B C D E F G H J K L

1434 48-wfbga MAQ P3.0

Figure 4: Pin Assignments for 48-Ball WFBGA

Table 1: Pin Description

Symbol

Pin Name

Functions

A_MS¹-A₀

Address Inputs

To provide memory addresses.

During Sector-Erase A_MS-A₁₁address lines will select the sector.

During Block-Erase A_MS-A₁₅address lines will select the block.

DQ₁₅-DQ₀Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

WP#

Write Protect

To protect the top/bottom boot block from Erase/Program operation when

grounded.

RST#

CE#

OE#

WE#

V_DD

Reset

To reset and return the device to Read mode.

To activate the device when CE# is low.

To gate the data output buffers.

Chip Enable

Output Enable

Write Enable

Power Supply

Ground

To control the Write operations.

To provide power supply voltage: 2.7-3.6V

V_SS

NC

No Connection

Ready/Busy#

Unconnected pins.

RY/BY#

To output the status of a Program or Erase operation

RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required

to allow RY/BY# to transition high indicating the device is ready to read.

T1.2 25041

1. A_MS= Most significant address

A_MS= A₁₈

DS25041A

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5

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Table 2: Top / Bottom Boot Block Address

Bottom Boot Block Address

SST39VF801C/SST39LF801C

Top Boot Block Address

SST39VF802C/SST39LF802C

Size

(KWord)

Size

#

Address Range

#

Address Range

(KWord)

18

17

16

15

14

13

12

11

10

9

8

7E000H-7FFFFH

7D000H-7DFFFH

7C000H-7CFFFH

78000H-7BFFFH

70000H-77FFFH

68000H-6FFFFH

60000H-67FFFH

58000H-5FFFFH

50000H-57FFFH

48000H-4FFFFH

40000H-47FFFH

38000H-3FFFFH

30000H-37FFFH

28000H-2FFFFH

20000H-27FFFH

18000H-1FFFFH

10000H-17FFFH

08000H-0FFFFH

00000H-07FFFH

18

17

16

15

14

13

12

11

10

9

32

16

4

78000H-7FFFFH

70000H-77FFFH

68000H-6FFFFH

60000H-67FFFH

58000H-5FFFFH

50000H-57FFFH

48000H-4FFFFH

40000H-47FFFH

38000H-3FFFFH

30000H-37FFFH

28000H-2FFFFH

20000H-27FFFH

18000H-1FFFFH

10000H-17FFFH

08000H-0FFFFH

04000H-07FFFH

03000H-03FFFH

02000H-02FFFH

00000H-01FFFH

4

16

32

8

7

6

5

4

3

2

1

4

0

8

T2.25041

DS25041A

05/11

6

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written

to the device using standard microprocessor write sequences. A command is written by asserting WE#

low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever

occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

The SST39VF801C/802C and SST39LF801C/802C also have the Auto Low Power mode which puts

the device in a near standby mode after data has been accessed with a valid Read operation. This

reduces the I_DDactive read current from typically 5 mA to typically 3 µA. The Auto Low Power mode

reduces the typical I_DDactive read current to the range of 2 mA/MHz of Read cycle time. The device

exits the Auto Low Power mode with any address transition or control signal transition used to initiate

another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power

mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high.

Read

The Read operation of the SST39VF801C/802C and SST39LF801C/802C is controlled by CE# and OE#,

both have to be low for the system to obtain data from the outputs. CE# is used for device selection.

When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output con-

trol and is used to gate data from the output pins. The data bus is in high impedance state when either

CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 6).

Word-Program Operation

The SST39VF801C/802C and SST39LF801C/802C are programmed on a word-by-word basis. Before

programming, the sector where the word exists must be fully erased. The Program operation is accom-

plished in three steps. The first step is the three-byte load sequence for Software Data Protection. The

second step is to load word address and word data. During the Word-Program operation, the

addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is

latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal

Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs

first. The Program operation, once initiated, will be completed within 10 µs. See Figures 7 and 8 for

WE# and CE# controlled Program operation timing diagrams and Figure 22 for flowcharts. During the

Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program

operation, the host is free to perform additional tasks. Any commands issued during the internal Pro-

gram operation are ignored. During the command sequence, WP# should be statically held high or low.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or

block-by-block) basis. The SST39VF801C/802C and SST39LF801C/802C offer both Sector-Erase and

Block-Erase mode.

The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based

on non-uniform block sizes—fifteen 32 KWord, one 16 KWord, two 4 KWord, and one 8 KWord blocks.

See Figure 2 for top and bottom boot device block addresses. The Sector-Erase operation is initiated

by executing a six-byte command sequence with Sector-Erase command (50H) and sector address

(SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command

sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector

or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or

50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the

DS25041A

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7

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle

Bit methods. See Figures 12 and 13 for timing waveforms and Figure 26 for the flowchart. Any com-

mands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt

to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP#

should be statically held high or low.

Erase-Suspend/Erase-Resume Commands

The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing

data to be read from any memory location, or program data into any sector/block that is not suspended

for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-

Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the

Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not

suspended from an Erase operation. Reading at address location within erase-suspended sectors/

blocks will output DQ₂toggling and DQ₆at ‘1’. While in Erase-Suspend mode, a Word-Program opera-

tion is allowed except for the sector or block selected for Erase-Suspend.

To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue

Erase Resume command. The operation is executed by issuing one byte command sequence with

Erase Resume command (30H) at any address in the last Byte sequence.

Chip-Erase Operation

The SST39VF801C/802C and SST39LF801C/802C provide a Chip-Erase operation, which allows the

user to erase the entire memory array to the ‘1’ state. This is useful when the entire device must be

quickly erased.

The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase

command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising

edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is

Toggle Bit or Data# Polling. See Table 7 for the command sequence, Figure 11 for timing diagram, and

Figure 26 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When

WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should

be statically held high or low.

Write Operation Status Detection

The SST39VF801C/802C and SST39LF801C/802C provide two software means to detect the comple-

tion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software

detection includes two status bits: Data# Polling (DQ₇) and Toggle Bit (DQ₆). The End-of-Write detec-

tion mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase opera-

tion.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a

Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this

occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with

either DQ₇or DQ₆. In order to prevent spurious rejection, if an erroneous result occurs, the software

routine should include a loop to read the accessed location an additional two (2) times. If both reads

are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

DS25041A

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8

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Ready/Busy# (RY/BY#)

The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that

indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain out-

put, it allows several devices to be tied in parallel to V_DDvia an external pull-up resistor. After the rising

edge of the final WE# pulse in the command sequence, the RY/BY# status is valid.

When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress.

When RY/BY# is high (Ready), the devices may be read or left in standby mode.

Data# Polling (DQ₇)

When the SST39VF801C/802C and SST39LF801C/802C are in the internal Program operation, any

attempt to read DQ₇will produce the complement of the true data. Once the Program operation is

completed, DQ₇will produce true data. Note that even though DQ₇may have valid data immediately follow-

ing the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on

the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal

Erase operation, any attempt to read DQ₇will produce a ‘0’. Once the internal Erase operation is com-

pleted, DQ₇will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#)

pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the ris-

ing edge of sixth WE# (or CE#) pulse. See Figure 9 for Data# Polling timing diagram and Figure 23 for

a flowchart.

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any consecutive attempts to read DQ₆will produce

alternating ‘1’s and ‘0’s, i.e., toggling between 1 and 0. When the internal Program or Erase operation

is completed, the DQ₆bit will stop toggling. The device is then ready for the next operation. For Sector-

, Block-, or Chip-Erase, the toggle bit (DQ₆) is valid after the rising edge of sixth WE# (or CE#) pulse.

DQ₆will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector/Block. If Pro-

gram operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ₆will toggle.

An additional Toggle Bit is available on DQ₂, which can be used in conjunction with DQ₆to check

whether a particular sector is being actively erased or erase-suspended. Table 3 shows detailed status

bits information. The Toggle Bit (DQ₂) is valid after the rising edge of the last WE# (or CE#) pulse of

Write operation. See Figure 10 for Toggle Bit timing diagram and Figure 23 for a flowchart.

Table 3: Write Operation Status

Status

DQ₇

DQ₇#

0

DQ₆

Toggle

1

DQ₂

No Toggle

Toggle

RY/BY#

Normal Operation

Standard Program

Standard Erase

0

1

Erase-Suspend

Mode

Read from Erase-Sus-

pended Sector/Block

1

Toggle

Read from Non-Erase-

Suspended Sector/Block

Data

N/A

1

0

Program

DQ₇#

Toggle

T3.0 25041

Note: DQ₇and DQ₂require a valid address when reading status information.

DS25041A

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9

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Data Protection

The SST39VF801C/802C and SST39LF801C/802C provide both hardware and software features to pro-

tect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.

V_DDPower Up/Down Detection: The Write operation is inhibited when V_DDis less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-

vents inadvertent writes during power-up or power-down.

Hardware Block Protection

The SST39VF802C/SST39LF802C support top hardware block protection, which protects the top 8

KWord block of the device. The SST39VF801C/SST39LF801C support bottom hardware block protec-

tion, which protects the bottom 8KWord block of the device. The Boot Block address ranges are

described in Table 4. Program and Erase operations are prevented on the 8 KWord when WP# is low.

If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected,

enabling Program and Erase operations on that block.

Table 4: Boot Block Address Ranges

Product

Address Range

00000H - 01FFFH

7E000H - 7FFFFH

Bottom Boot Block

SST39VF801C/SST39LF801C

Top Boot Block

SST39VF802C/SST39LF802C

T4.0 25041

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the device to read array data. When the RST#

pin is held low for at least T_RP,any in-progress operation will terminate and return to Read mode. When

no internal Program/Erase operation is in progress, a minimum period of T_RHRis required after RST#

is driven high before a valid Read can take place (see Figure 18).

The Erase or Program operation that has been interrupted needs to be re-initiated after the device

resumes normal operation mode to ensure data integrity.

Software Data Protection (SDP)

The SST39VF801C/802C and SST39LF801C/802C provide the JEDEC approved Software Data Pro-

tection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation

requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the

Program operation, providing optimal protection from inadvertent Write operations, e.g., during the

system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence.

These devices are shipped with the Software Data Protection permanently enabled. See Table 7 for

DS25041A

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8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

the specific software command codes. During SDP command sequence, invalid commands will abort

the device to read mode within T_RC.The contents of DQ₁₅-DQ₈can be V_ILor V_IH, but no other value,

during any SDP command sequence.

Common Flash Memory Interface (CFI)

The SST39VF801C/802C and SST39LF801C/802C also contain the CFI information to describe the

characteristics of the device. In order to enter the CFI Query mode, the system writes a three-byte

sequence, same as product ID entry command with 98H (CFI Query command) to address 555H in

the last byte sequence. Additionally, the system can use the one-byte sequence with 55H on the

Address and 89H on the Data Bus to enter the CFI Query mode. Once the device enters the CFI

Query mode, the system can read CFI data at the addresses given in Tables 8 through 10. The system

must write the CFI Exit command to return to Read mode from the CFI Query mode.

Product Identification

The Product Identification mode identifies the devices as the SST39VF801C / SST39VF802C /

SST39LF801C / SST39LF802C, and manufacturer as SST. This mode may be accessed software

operations. Users may use the Software Product Identification operation to identify the part (i.e., using

the device ID) when using multiple manufacturers in the same socket. For details, see Table 7 for soft-

ware operation, Figure 14 for the Software ID Entry and Read timing diagram and Figure 24 for the

Software ID Entry command sequence flowchart.

Table 5: Product Identification

Address

Data

Manufacturer’s ID

0000H

BFH

Device ID

SST39VF801C/SST39LF801C

SST39VF802C/SST39LF802C

0001H

233BH

233AH

T5.2 25041

Product Identification Mode Exit/CFI Mode Exit

In order to return to the standard Read mode, the Software Product Identification mode must be exited.

Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to

the Read mode. This command may also be used to reset the device to the Read mode after any inad-

vertent transient condition that apparently causes the device to behave abnormally, e.g., not read cor-

rectly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program

or Erase operation. See Table 7 for software command codes, Figure 16 for timing waveform, and Fig-

ure 25 for flowcharts.

DS25041A

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11

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Security ID

The SST39VF801C/802C and SST39LF801C/802C devices offer a 136 Word Security ID space. The

Secure ID space is divided into two segments—one factory programmed segment and one user pro-

grammed segment. The first segment is programmed and locked at SST with a random 128-bit num-

ber. The user segment, with a 128 word space, is left un-programmed for the customer to program as

desired.

To program the user segment of the Security ID, the user must use the Security ID Word-Program

command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once

this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables

any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither

Sec ID segment can be erased.

The Secure ID space can be queried by executing a three-byte command sequence with Enter Sec ID

command (88H) at address 555H in the last byte sequence. To exit this mode, the Exit Sec ID com-

mand should be executed. Refer to Table 7 for more details.

DS25041A

05/11

12

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Operations

Table 6: Operation Modes Selection

Mode

Read

CE#

V_IL

OE#

V_IL

WE# DQ

Address

A_IN

V_IH

V_IL

D_OUT

Program

Erase

V_IL

V_IH

D_IN

X¹

A_IN

V_IL

Sector or block address, XXH for Chip-

Erase

Standby

V_IH

X

V_IL

X

High Z

X

Write Inhibit

High Z/ D_OUT

X

V_IH

Product Identification

Software Mode

V_IL

V_IH

See Table 7

T6.0 25041

1. X can be V_ILor V_IH, but no other value.

Table 7: Software Command Sequence

Command

Sequence

1st Bus

Write Cycle

2nd Bus

3rd Bus

4th Bus

5th Bus

Write Cycle Write Cycle

6th Bus

Write Cycle Write Cycle Write Cycle

Addr¹Data²Addr¹Data²Addr¹Data²Addr¹Data²Addr¹Data²Addr¹Data²

Word-Program

Sector-Erase

Block-Erase

555H

AAH 2AAH 55H 555H A0H WA³Data

4

AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA_X

AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BA_X

50H

30H

Chip-Erase

AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Erase-Suspend

Erase-Resume

Query Sec ID⁵

XXXH B0H

XXXH 30H

555H

AAH 2AAH 55H 555H 88H

AAH 2AAH 55H 555H A5H WA⁶Data

User Security ID

Word-Program

User Security ID

Program Lock-

Out

555H

AAH 2AAH 55H 555H 85H XXH⁶0000

H

Software ID

Entry^7,8

AAH 2AAH 55H 555H 90H

CFI Query Entry

555H

55H

AAH 2AAH 55H 555H 98H

98H

CFI Query Entry

Software ID Exit^9,10

/CFI Exit/Sec ID

Exit

555H

AAH 2AAH 55H 555H F0H

Software ID Exit^9,10

/CFI Exit/Sec ID

Exit

XXH

F0H

T7.6 25041

1. Address format A₁₀-A₀(Hex). Addresses A₁₁-A₁₈can be V_ILor V_IH, but no other value, for Command sequence.

2. DQ₁₅-DQ₈can be V_ILor V_IH, but no other value, for Command sequence

3. WA = Program Word address

4. SA_Xfor Sector-Erase; uses A_MS-A₁₁address lines

BA_X, for Block-Erase; uses A_MS-A₁₅address lines

A_MS= Most significant address; A_MS= A₁₈

DS25041A

05/11

13

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

5. With A_MS-A₄= 0; Sec ID is read with A₃-A₀,

SST ID is read with A₃= 0 (Address range = 000000H to 000007H),

User ID is read with A₃= 1 (Address range = 000008H to 000087H).

Lock Status is read with A₇-A₀= 0000FFH. Unlocked: DQ₃= 1 / Locked: DQ₃= 0.

6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H-000087H.

7. The device does not remain in Software Product ID Mode if powered down.

8. With A_MS-A₁=0; SST Manufacturer ID = 00BFH, is read with A₀= 0,

SST39VF801C/SST39LF801C Device ID = 233BH, is read with A₀= 1, SST39VF802C/SST39LF802C Device ID =

233AH, is read with A₀= 1,

A_MS= Most significant address; A_MS= A₁₈

9. Both Software ID Exit operations are equivalent

10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1)

using the Sec ID mode again (the programmed ‘0’ bits cannot be reversed to ‘1’). Valid Word-Addresses for Sec ID are

from 000000H-000007H and 000008H-000087H.

Table 8: CFI Query Identification String¹

Address

10H

Data

0051H

0052H

0059H

0002H

0000H

Query Unique ASCII string “QRY”

11H

12H

13H

Primary OEM command set

14H

15H

Address for Primary Extended Table

16H

17H

Alternate OEM command set (00H = none exists)

Address for Alternate OEM extended Table (00H = none exits)

18H

19H

1AH

T8.1 25041

1. Refer to CFI publication 100 for more details.

Table 9: System Interface Information

Address

Data

1BH

0027H

V_DDMin (Program/Erase)

DQ₇-DQ₄: Volts, DQ₃-DQ₀: 100 millivolts

1CH

0036H

V_DDMax (Program/Erase)

DQ₇-DQ₄: Volts, DQ₃-DQ₀: 100 millivolts

1DH

1EH

1FH

20H

21H

22H

23H

24H

25H

26H

0000H

0003H

0000H

0004H

0005H

0001H

0000H

0001H

V_PPmin. (00H = no V_PPpin)

V_PPmax. (00H = no V_PPpin)

Typical time out for Word-Program 2^Nµs (2³= 8 µs)

Typical time out for min. size buffer program 2^Nµs (00H = not supported)

Typical time out for individual Sector/Block-Erase 2^Nms (2⁴= 16 ms)

Typical time out for Chip-Erase 2^Nms (2⁵= 32 ms)

Maximum time out for Word-Program 2^Ntimes typical (2¹x 2³= 16 µs)

Maximum time out for buffer program 2^Ntimes typical

Maximum time out for individual Sector/Block-Erase 2^Ntimes typical (2¹x 2⁴= 32 ms)

Maximum time out for Chip-Erase 2^Ntimes typical (2¹x 2⁵= 64 ms)

T9.3 25041

DS25041A

05/11

14

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Table 10:Device Geometry Information

Address

27H

28H

29H

2AH

2BH

2CH

2DH

2EH

2FH

30H

31H

32H

33H

34H

35H

36H

37H

38H

39H

3AH

3BH

3CH

Data

0014H

0001H

0000H

0005H

0000H

0040H

0000H

0001H

0000H

0020H

0000H

0080H

0000H

000FH

0000H

0001H

Device size = 2^NBytes (14H = 20; 2²⁰= 1 MByte)

Flash Device Interface description; 0001H = x16-only asynchronous interface

Maximum number of byte in multi-byte write = 2^N(00H = not supported)

Number of Erase Sector/Block sizes supported by device

Erase Block Region 1 Information (Refer to the CFI specification or CFI publication

100)

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

T10.0 25041

DS25041A

05/11

15

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Electrical Specifications

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute

Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these conditions or conditions greater than those defined in the

operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating con-

ditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V_DD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -2.0V to V_DD+2.0V

Voltage on A₉Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Package Power Dissipation Capability (T_A= 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current¹. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

Table 11:Operating Range

Range

Ambient Temp

0°C to +70°C

V_DD

Commercial

Industrial

2.7-3.6V

-40°C to +85°C

T11.0 25041

Table 12:AC Conditions of Test¹

Input Rise/Fall Time

Output Load

5ns

C_L= 30 pF

T12.1 25041

1. See Figures 20 and 21

DS25041A

05/11

16

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Power Up Specifications

All functionalities and DC specifications are specified for a V_DDramp rate of greater than 1V per 100

ms (0V to 3V in less than 300 ms). If the VDD ramp rate is slower than 1V per 100 ms, a hardware

reset is required. The recommended V_DDpower-up to RESET# high time should be greater than 100

µs to ensure a proper reset.

1 00 µs

T

PU-READ

V

min

V

DD

0V

V

IH

RESET#

T

5 0ns

RHR

CE#

1434 F24.0

Figure 5: Power-Up Diagram

Table 13:DC Operating Characteristics V_DD= 2.7-3.6V¹

Limits

Symbol Parameter

Min

Max

Units

Test Conditions

Address input=V_ILT/V_IHT², at f=5 MHz,

_DD=V_DDMax

I_DD

Power Supply Current

V

Read³

18

30

20

mA

µA

CE#=V_IL, OE#=WE#=V_IH, all I/Os open

CE#=WE#=V_IL, OE#=V_IH

Program and Erase

Standby V_DDCurrent

I_SB

CE#=V_IHC, V_DD=V_DDMax

RST#=V_DD0.3, WP#=V_DD0.3,

WE#=V_DD0.3

I_ALP

Auto Low Power

20

µA

CE#=V_ILC, V_DD=V_DDMax

All inputs=V_SSor V_DD,WE#=V_IHC

I_LI

Input Leakage Current

1

µA

V_IN=GND to V_DD, V_DD=V_DDMax

I_LIW

Input Leakage Current

on WP# pin and RST#

10

WP#=GND to V_DDor RST#=GND to V_DD

I_LO

Output Leakage Current

Input Low Voltage

10

0.8

0.3

µA

V

V_OUT=GND to V_DD, V_DD=V_DDMax

V_DD=V_DDMin

V_IL

V_ILC

V_IH

Input Low Voltage (CMOS)

Input High Voltage

V

V_DD=V_DDMax

0.7V_DDV_DD+0.3

V

V_DD=V_DDMax

V_IHC

V_OL

V_OH

Input High Voltage (CMOS) V_DD-0.3 V_DD+0.3

V

V_DD=V_DDMax

Output Low Voltage

Output High Voltage

0.2

V

I_OL=100 µA, V_DD=V_DDMin

V_DD-0.2

V

I_OH=-100 µA, V_DD=V_DDMin

T13.8 25041

1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C

(room temperature), and V_DD= 3V. Not 100% tested.

2. See Figure 20

3. The I_DDcurrent listed is typically less than 2mA/MHz, with OE# at V_IH.Typical V_DDis 3V.

DS25041A

05/11

17

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Table 14:Recommended System Power-up Timings

Symbol

Parameter

Minimum

100

Units

µs

1

T_PU-READ

Power-up to Read Operation

Power-up to Program/Erase Operation

1

T_PU-WRITE

100

µs

T14.0 25041

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

Table 15:Capacitance (T_A= 25°C, f=1 Mhz, other pins open)

Parameter

Description

Test Condition

V_I/O= 0V

Maximum

12 pF

1

C_I/O

I/O Pin Capacitance

Input Capacitance

1

C_IN

V_IN= 0V

6 pF

T15.0 25041

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

Table 16:Reliability Characteristics

Symbol

Parameter

Endurance

Data Retention

Latch Up

Minimum Specification

Units

Cycles

Years

mA

Test Method

1,2

N_END

10,000

100

JEDEC Standard A117

JEDEC Standard A103

JEDEC Standard 78

1

T_DR

1

I_LTH

100 + I_DD

T16.2 25041

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

2. N_ENDendurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would

result in a higher minimum specification.

DS25041A

05/11

18

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

AC Characteristics

Table 17:Read Cycle Timing Parameters V_DD= 2.7-3.6V

SST39VF801C/802C

SST39LF801C/802C

Symbol Parameter

Min

Max

Min

Max

Units

ns

T_RC

T_CE

T_AA

T_OE

T_CLZ

Read Cycle Time

70

55

Chip Enable Access Time

Address Access Time

70

35

55

30

ns

Output Enable Access Time

CE# Low to Active Output

OE# Low to Active Output

CE# High to High-Z Output

OE# High to High-Z Output

Output Hold from Address Change

RST# Pulse Width

ns

1

0

ns

T_OLZ

T_CHZ

ns

1

20

15

ns

T_OHZ

ns

1

T_OH

0

ns

1

T_RP

500

50

500

50

ns

1

T_RHR

RST# High before Read

RST# Pin Low to Read Mode

ns

1,2

T_RY

20

µs

T17.3 25041

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. This parameter applies to Sector-Erase, Block-Erase and Program operations.

This parameter does not apply to Chip-Erase operations.

Table 18:Program/Erase Cycle Timing Parameters

Symbol

T_BP

Parameter

Min

Max

Units

µs

Word-Program Time

Address Setup Time

Address Hold Time

WE# and CE# Setup Time

WE# and CE# Hold Time

OE# High Setup Time

OE# High Hold Time

CE# Pulse Width

10

T_AS

0

30

0

ns

T_AH

ns

T_CS

ns

T_CH

0

ns

T_OES

T_OEH

T_CP

0

ns

10

40

30

0

ns

T_WP

WE# Pulse Width

ns

1

T_WPH

WE# Pulse Width High

CE# Pulse Width High

Data Setup Time

ns

1

T_CPH

ns

T_DS

ns

1

T_DH

Data Hold Time

ns

1

T_IDA

Software ID Access and Exit Time

Sector-Erase

150

25

50

90

0

ns

T_SE

ms

ns

T_BE

Block-Erase

T_SCE

Chip-Erase

1,2

T_BY

RY/BY# Delay Time

Bus Recovery Time

1

T_BR

µs

T18.1 25041

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.

DS25041A

05/11

19

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

T

AA

RC

ADDRESS A

MS-0

CE#

OE#

T

CE

T

OE

T

OHZ

OLZ

V

IH

WE#

T

CHZ

T

OH

CLZ

HIGH-Z

DQ

15-0

DATA VALID

1434 F03.0

Note: A_MS= Most significant address

A_MS= A₁₈

Figure 6: Read Cycle Timing Diagram

T

BP

555

2AA

555

ADDR

ADDRESSES

T

AH

T

WP

WE#

T

WPH

AS

OE#

T

CH

CE#

T

CS

T

BR

BY

RY/BY#

T

DS

T

DH

DQ

15-0

XXAA

XX55

XXA0

DATA

VALID

WORD

(ADDR/DATA)

1434 F25.0

Note: WP# must be held in proper logic state (V_IL

or V_IH) 1µs prior to and 1µs after the command sequence.

X can be V_ILor V_IH, but no other value.

Figure 7: WE# Controlled Program Cycle Timing Diagram

DS25041A

05/11

20

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

T

BP

555

2AA

555

ADDR

ADDRESSES

T

AH

T

CP

CE#

T

CPH

AS

OE#

T

CH

WE#

T

CS

T

BR

BY

RY/BY#

T

DS

T

DH

DQ

15-0

XXAA

XX55

XXA0

DATA

VALID

WORD

(ADDR/DATA)

1434 F26.0

Note: WP# must be held in proper logic state (V_ILor V_IH) 1µs prior to and 1µs after

the command sequence.

X can be V_ILor V_IH, but no other value.

Figure 8: CE# Controlled Program Cycle Timing Diagram

ADDRESS A

18-0

T

CE

CE#

T

OES

OEH

OE#

T

OE

WE#

T

BY

RY/BY#

DQ

7

DATA

DATA#

DATA

1434 F27.0

Figure 9: Data# Polling Timing Diagram

DS25041A

05/11

21

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

ADDRESS A

MS-0

T

CE

CE#

T

OEH

T

OES

T

OE

OE#

WE#

DQ and DQ

6

2

TWO READ CYCLES

WITH SAME OUTPUTS

1434 F07.0

Note: A_MS= Most significant address

A_MS= A₁₈

Figure 10:Toggle Bits Timing Diagram

T

SIX-BYTE CODE FOR CHIP-ERASE

555 555 2AA

SCE

555

2AA

555

ADDRESSES

CE#

OE#

WE#

T

OEH

T

BR

BY

RY/BY#

DQ

15-0

XX55

XXAA

XX55

XXAA

XX10

XX80

VALID

1434 F31.0

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are inter-

changeable as long as minimum timings are met. (See Table 18).

WP# must be held in proper logic state (V_IH) 1µs prior to and 1µs after the command sequence.

X can be V_ILor V_IH, but no other value.

Figure 11:WE# Controlled Chip-Erase Timing Diagram

DS25041A

05/11

22

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

T

SIX-BYTE CODE FOR BLOCK-ERASE

555 555 2AA

BE

555

2AA

BA

X

ADDRESSES

CE#

OE#

WE#

T

WP

T

BR

T

BY

RY/BY#

DQ

15-0

XX55

XXAA

XX55

XXAA

XX30

XX80

VALID

1434 F32.0

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are inter-

changeable as long as minimum timings are met. (See Table 18).

BA_X= Block Address

WP# must be held in proper logic state (V_ILor V_IH) 1µs prior to and 1µs after the command sequence.

X can be V_ILor V_IH, but no other value.

Figure 12:WE# Controlled Block-Erase Timing Diagram

T

SIX-BYTE CODE FOR SECTOR-ERASE

555 555 2AA

SE

555

2AA

SA

X

ADDRESSES

CE#

OE#

WE#

T

WP

T

BR

T

BY

RY/BY#

DQ

15-0

XX55

XXAA

XX55

XXAA

XX50

XX80

VALID

1434 F28.0

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are inter-

changeable as long as minimum timings are met. (See Table 18).

SA_X= Block Address

WP# must be held in proper logic state (V_ILor V_IH) 1µs prior to and 1µs after the command sequence.

X can be V_ILor V_IH, but no other value.

Figure 13:WE# Controlled Sector-Erase Timing Diagram

DS25041A

05/11

23

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Three-Byte Sequence for Software ID Entry

ADDRESS

CE#

555

2AA

555

0000

0001

OE#

T

IDA

T

WP

WE#

T

WPH

T

AA

XXAA

SW0

XX55

SW1

XX90

SW2

Device ID

DQ

00BF

15-0

1434 F11.0

Note: Device ID = 233BH for SST39VF801C/SST39LF801C and 233AH for SST39VF801C/SST39LF801C

WP# must be held in proper logic state (V_ILor V_IH) 1µs prior to and 1µs after the command sequence.

X can be V_ILor V_IH, but no other value.

Figure 14:Software ID Entry and Read

Three-Byte Sequence for CFI Query Entry

ADDRESS

CE#

555

2AA

555

OE#

T

IDA

T

WP

WE#

T

WPH

T

AA

DQ

XXAA

SW0

XX55

SW1

XX98

SW2

15-0

1434 F12.0

Note: WP# must be held in proper logic state (V_ILor V_IH) 1µs prior to and 1µs after the command sequence.

X can be V_ILor V_IH, but no other value.

Figure 15:CFI Query Entry and Read

DS25041A

05/11

24

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

555

2AA

555

ADDRESS

XXAA

XX55

XXF0

DQ

15-0

T

IDA

CE#

OE#

WE#

T

WP

T

WHP

SW0

SW1

SW2

1434 F13.0

Note: WP# must be held in proper logic state (V_ILor V_IH) 1µs prior to and 1µs after the command sequence.

X can be V_ILor V_IH, but no other value.

Figure 16:Software ID Exit/CFI Exit

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

ADDRESS A

555

2AA

555

MS-0

CE#

OE#

T

IDA

T

WP

WE#

T

WPH

T

AA

XXAA

SW0

XX55

SW1

XX88

SW2

DQ

15-0

1434 F20.0

Note: A_MS= Most significant address

A_MS= A₁₈

WP# must be held in proper logic state (V_ILor V_IH) 1µs prior to and 1µs after the command sequence.

X can be V_ILor V_IH, but no other value.

Figure 17:Sec ID Entry

DS25041A

05/11

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8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

RY/BY#

0V

T

RP

RST#

T

RHR

CE#/OE#

1434 F29.0

Figure 18:RST# Timing Diagram (When no internal operation is in progress)

T

RY

RY/BY#

RST#

T

RP

CE#

OE#

T

BR

1434 F30.0

Figure 19:RST# Timing Diagram (During Program or Erase operation)

V

IHT

V

INPUT

REFERENCE POINTS

OUTPUT

OT

IT

V

ILT

1434 F14.0

AC test inputs are driven at V_IHT(0.9 V_DD) for a logic ‘1’ and V_ILT(0.1 V_DD) for a logic ‘0’. Measure-

ment reference points for inputs and outputs are V_IT(0.5 V_DD) and V_OT(0.5 V_DD). Input rise and

fall times (10%  90%) are <5 ns.

Note: V_IT- V_INPUTTest

V_OT- V_OUTPUTTest

V_IHT- V_INPUTHIGH Test

V_ILT- V_INPUTLOW Test

Figure 20:AC Input/Output Reference Waveforms

DS25041A

05/11

26

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

TO TESTER

TO DUT

C_L

1434 F15.0

Figure 21:A Test Load Example

DS25041A

05/11

27

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Start

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XXA0H

Address: 555H

Load Word

Address/Word

Data

Wait for end of

Program (T

Data# Polling

,

BP

bit, or Toggle bit

operation)

Program

Completed

1434 F16.0

Note: X can V_ILor V_IH, but no other value.

Figure 22:Word-Program Algorithm

DS25041A

05/11

28

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Toggle Bit

Data# Polling

RY/BY#

Internal Timer

Program/Erase

Initiated

Program/Erase

Initiated

Program/Erase

Initiated

Program/Erase

Initiated

Read DQ

7

Read word

Wait T

,

Read RY/BY#

BP

T

SCE, SE

or T

BE

Read same

word

No

Is DQ =

7

Is

No

true data

Program/Erase

Completed

RY/BY# = 1

Yes

No

Does DQ

match

Program/Erase

Completed

6

Program/Erase

Completed

Yes

Program/Erase

Completed

1434 F17.0

Figure 23:Wait Options

DS25041A

05/11

29

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Software Product ID

Entry

Command Sequence

CFI Query Entry

Command Sequence

Sec ID Query Entry

Command Sequence

Load data: XXAAH

Address: 555H

Load data: XX98H

Address: 55H

Load data: XXAAH

Address: 555H

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX55H

Address: 2AAH

Load data: XX55H

Address: 2AAH

Wait T

IDA

Load data: XX98H

Address: 55H

Load data: XX88H

Address: 555H

Load data: XX90H

Address: 555H

Read CFI data

Wait T

IDA

Read CFI data

Read Sec ID

Read Software ID

1434 F21.0

Note: X can V_ILor V_IH, but no other value.

Figure 24:Software ID/CFI Entry Command Flowcharts

DS25041A

05/11

30

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Software ID Exit/CFI Exit/Sec ID Exit

Command Sequence

Load data: XXAAH

Address: 555H

Load data: XXF0H

Address: XXH

Load data: XX55H

Address: 2AAH

Wait T

IDA

Load data: XXF0H

Address: 555H

Return to normal

operation

Wait T

IDA

Return to normal

operation

1434 F18.0

Note: X can be V_ILor V_IH, but no other value.

Figure 25:Software ID/CFI Exit Command Flowcharts

DS25041A

05/11

31

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Chip-Erase

Sector-Erase

Block-Erase

Command Sequence

Load data: XXAAH

Address: 555H

Load data: XXAAH

Address: 555H

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX55H

Address: 2AAH

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX80H

Address: 555H

Load data: XX80H

Address: 555H

Load data: XXAAH

Address: 555H

Load data: XXAAH

Address: 555H

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX55H

Address: 2AAH

Load data: XX55H

Address: 2AAH

Load data: XX10H

Address: 555H

Load data: XX50H

Load data: XX30H

Address: SA

Address: BA

X

Wait T

BE

SCE

SE

Chip erased

to FFFFH

Sector erased

to FFFFH

Block erased

to FFFFH

1434 F19.0

Note: X can be V_ILor V_IH, but no other value.

Figure 26:Erase Command Sequence

DS25041A

05/11

32

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Product Ordering Information

SST 39 VF 801C

-

70

-

4C

-

EKE

-

XX XX XXXX

-

XX

-

XX

XXX

Environmental Attribute

E¹= non-Pb

Package Modifier

K = 48 balls or leads

Q = 48 balls (66 possible positions)

Package Type

E = TSOP (type1, die up, 12mm x 20mm)

B3 = TFBGA (6mm x 8mm, 0.8mm pitch)

MA = WFBGA (4mm x 6mm, 0.5mm pitch)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

55 = 55 ns

Hardware Block Protection

1 = Bottom Boot-Block

2 = Top Boot-Block

Device Density

80= 8 Mbit

Voltage

V = 2.7-3.6V

L = 3.0-3.6V

Product Series

39 = Multi-Purpose Flash

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

DS25041A

05/11

33

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Valid Combinations for SST39VF801C

SST39VF801C-70-4C-EKE

SST39VF801C-70-4C-B3KE

SST39VF801C-70-4C-MAQE

SST39VF801C-70-4I-MAQE

SST39VF801C-70-4I-EKE

SST39VF801C-70-4I-B3KE

Valid Combinations for SST39VF802C

SST39VF802C-70-4C-EKE

SST39VF802C-70-4C-B3KE

SST39VF802C-70-4C-MAQE

SST39VF802C-70-4I-MAQE

SST39VF802C-70-4I-EKE

SST39VF802C-70-4I-B3KE

Valid Combinations for SST39LF801C

SST39LF801C-55-4C-EKE

SST39LF801C-55-4C-B3KE

SST39LF801C-55-4C-MAQE

SST39LF802C-55-4C-MAQE

Valid Combinations for SST39LF802C

SST39LF802C-55-4C-EKE

SST39LF802C-55-4C-B3KE

Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST

sales representative to confirm availability of valid combinations and to determine availability of new combi-

nations.

DS25041A

05/11

34

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Packaging Diagrams

1.05

0.95

Pin # 1 Identifier

0.50

BSC

0.27

0.17

12.20

11.80

0.15

0.05

18.50

18.30

DETAIL

1.20

max.

0.70

0.50

20.20

19.80

0°- 5°

0.70

0.50

Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

1mm

48-tsop-EK-8

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

Figure 27:48-lead Thin Small Outline Package (TSOP) 12mm x 20mm

SST Package Code: EK

DS25041A

05/11

35

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

TOP VIEW

8.00 0.10

BOTTOM VIEW

5.60

0.80

0.45 0.05

(48X)

6

5

4

3

2

1

6

5

4

3

2

1

4.00

0.80

6.00 0.10

A

B C D E F G H

H

G F E D C B A

A1 CORNER

1.10 0.10

SIDE VIEW

0.12

SEATING PLANE

1mm

0.35 0.05

Note:

1. Complies with JEDEC Publication 95, MO-210, variant AB-1 , although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm ( 0.05 mm)

48-tfbga-B3K-6x8-450mic-5

Figure 28:48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm

SST Package Code: B3K

DS25041A

05/11

36

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

TOP VIEW

BOTTOM VIEW

5.00

0.50

6.00

0.08

0.32 0.05

(48X)

6

5

4

3

2

1

6

5

4

3

2

1

4.00

0.08

2.50

0.50

A

B

C

D

E

F

G

H

J

K

L

L K J H G F E D C B A

A1 CORNER

A1 INDICATOR

0.73 max.

0.636 nom.

DETAIL

SIDE VIEW

0.08

SEATING PLANE

0.20 0.06

1mm

Note:

1. Complies with JEDEC Publication 95, MO-207, Variant CB-4 except nominal ball size is larger

and bottom side A1 indicator is triangle at corner.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.08 mm

4. Ball opening size is 0.29 mm ( 0.05 mm)

48-wfbga-MAQ-4x6-32mic-2.0

Figure 29:48-ball Very, Very Thin-profile, Fine-pitch Ball Grid Array (WFBGA) 4mm x 6mm

SST Package Code: MAQ

DS25041A

05/11

37

8 Mbit (x16) Multi-Purpose Flash Plus

SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C

A Microchip Technology Company

Data Sheet

Table 19:Revision History

Number

Description

Date

A

May 2011

•

Initial release

ISBN: 978-1-61341-197-1

SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Tech-

nology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and

registered trademarks mentioned herein are the property of their respective owners.

Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current

package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.

Memory sizes denote raw storage capacity; actual usable capacity may be less.

SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of

Sale.

For sales office(s) location and information, please see www.microchip.com.

Silicon Storage Technology, Inc.

A Microchip Technology Company

www.microchip.com

DS25041A

05/11

38

型号:	SST39VF801C-70-4I-MAQE
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	DSBGA
包装说明：	4 X 6 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-207CB-4, WFBGA-48
针数：	48
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.32.00.51
Factory Lead Time：	7 weeks
风险等级：	2.05
最长访问时间：	70 ns
其他特性：	BOTTOM BOOT BLOCK
启动块：	BOTTOM
命令用户界面：	YES
通用闪存接口：	YES
数据轮询：	YES
JESD-30 代码：	R-PBGA-B48
JESD-609代码：	e1
长度：	6 mm
内存密度：	8388608 bit
内存集成电路类型：	FLASH
内存宽度：	16
湿度敏感等级：	3
功能数量：	1
部门数/规模：	256
端子数量：	48
字数：	524288 words
字数代码：	512000
工作模式：	ASYNCHRONOUS
最高工作温度：	85 °C
最低工作温度：	-40 °C
组织：	512KX16
封装主体材料：	PLASTIC/EPOXY
封装代码：	VFBGA
封装等效代码：	BGA48,6X11,20
封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260
电源：	3/3.3 V
编程电压：	2.7 V
认证状态：	Not Qualified
就绪/忙碌：	YES
座面最大高度：	0.73 mm
部门规模：	2K
最大待机电流：	0.00002 A
子类别：	Flash Memories
最大压摆率：	0.03 mA
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	2.7 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL
端子节距：	0.5 mm
端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	40
切换位：	YES
类型：	NOR TYPE
宽度：	4 mm
Base Number Matches：	1

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