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  • 北京元坤伟业科技有限公司

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产品型号ST16C552IJ68-F的概述

芯片ST16C552IJ68-F概述 ST16C552IJ68-F是一款由STMicroelectronics(意法半导体)生产的双通道串行通信控制器。作为一种多功能的串行接口,ST16C552为用户提供了一种在计算机和外部设备之间进行有效通信的方式,尤其适合用于串口通信、数据采集及控制等应用场合。该芯片广泛应用于工业控制、数据传输设备及其他电子产品中,因其卓越的性能和稳定性而受到设计工程师的青睐。 在当今信息化和自动化的时代,大量外部设备需要通过串行接口与主控制器进行联接和交互。ST16C552IJ68-F通过提供高效的串行通信能力,满足了对速度和可靠性日益增长的需求。它能够支持多种波特率,兼容多种通信协议,使其在多种应用中更加灵活和适应。 详细参数 ST16C552IJ68-F具备一系列技术参数,这些参数决定了其在特定应用中的表现: - 工作电压: 3.0V至5.5V - 工作温度...

产品型号ST16C552IJ68-F的Datasheet PDF文件预览

ST16C552  
ST16C552A  
DUAL UART WITH 16-BYTE FIFO AND  
PARALLEL PRINTER PORT  
December 2003  
DESCRIPTION  
The ST16C552/ST16C552A (552/552A) is a dual universal asynchronous receiver and transmitter (UART) with  
an added bi-directional parallel port that is directly compatible with a CENTRONICS type printer. The parallel port  
is designed such that the user can configure it as general purpose I/O interface, or for connection to other printer  
devices. The 552/552A provides enhanced UART functions with 16 byte FIFO’s, a modem control interface, and  
data rates up to 1.5Mbps. Onboard status registers provide the user with error indications and operational status.  
The system interrupts and control may be tailored to meet user requirements. An internal loop-back capability  
allows onboard diagnostics. A programmable baud rate generator is provided to select transmit and receive clock  
rates from 50 bps to 1.5 Mbps. The 552/552A is available in a 68 pin PLCC package. The 552/552A is compatible  
with the 16C450 and 16C550. The difference between the ST16C552 and ST16C552A is the logic state of the  
printer port, INTP interrupt. The INTP interrupt is active high (logic 1) on the ST16C552 whereas INTP is active  
low (logic 0) on the ST16C552A part when the interrupt latch mode is selected. The 552/552A is fabricated in an  
advanced CMOS process with power down mode to reduce the power consumption. The 552A does not support  
the power down mode.  
PLCC Package  
FEATURES  
Added features in device revision "F" and newer:  
5VTolerantInputs  
Pin to pin and functional compatible to ST16C452/  
452PS,TL16C552  
2.97 to 5.5 volt operation  
TXB 10  
-DTRB 11  
-RTSB 12  
-CTSB 13  
D0 14  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
INTB  
INTP  
-SLCTIN  
INIT  
SoftwarecompatiblewithINS8250,NS16C550  
1.5 Mbps transmit/receive operation (24MHz)  
16 byte transmit FIFO  
16 byte receive FIFO with error flags  
Independenttransmitandreceivecontrol  
Modem and printer status registers  
UART port and printer port Bi-directional  
Printer port direction set by single control bit or 8 bit  
pattern (AA/55)  
-AUTOFDXT  
-STROBE  
GND  
D1 15  
D2 16  
D3 17  
PD0  
ST16C552CJ68  
ST16C552ACJ68  
D4 18  
PD1  
D5 19  
PD2  
D6 20  
PD3  
D7 21  
PD4  
-TXRDYA 22  
VCC 23  
-RTSA 24  
-DTRA 25  
TXA 26  
PD5  
PD6  
PD7  
Modem control signals (-CTS, -RTS, -DSR, -DTR,  
-RI, -CD)  
INTA  
RDOUT  
Programmable character lengths (5, 6, 7, 8)  
Even, odd, ornoparitybitgenerationanddetection  
TTL compatible inputs, outputs  
Powerdownmode  
ORDERING INFORMATION  
Part number  
Pins  
68  
68  
68  
68  
Package  
PLCC  
PLCC  
PLCC  
PLCC  
Operating temperature  
Device Status  
Active  
Active  
Active  
Active  
ST16C552CJ68  
ST16C552ACJ68  
ST16C552IJ68  
ST16C552AIJ68  
0° C to + 70° C  
0° C to + 70° C  
-40° C to + 85° C  
-40° C to + 85° C  
Rev.3.40  
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017  
ST16C552/552A  
Figure 1, Block Diagram  
Transmit  
FIFO  
Registers  
Transmit  
Shift  
Register  
TX A,B  
RX A,B  
D0-D7  
-IOR  
-IOW  
-RESET  
BIDEN  
Receive  
FIFO  
Receive  
Shift  
Registers  
Register  
Printer  
Data  
PD0-PD7  
Ports  
-STROBE  
INIT  
-AUTOFDX  
A0-A2  
-CSA  
-CSB  
-CSP  
Printer  
Control  
Logic  
-SELCTIN  
PE, SELECT  
-BUSY, -ACK  
ERROR  
-DTR A,B  
-RTS A,B  
Modem  
Control  
Logic  
-CTS A,B  
-RI A,B  
-CD A,B  
-DSR A,B  
Clock  
&
Baud Rate  
INT A,B  
INTP  
-RXRDY  
-TXRDY  
Generator  
Rev.3.40  
2
ST16C552/552A  
SYMBOL DESCRIPTION  
Symbol  
A0  
Pin  
Signal Type  
Pin Description  
35  
34  
33  
68  
I
I
I
I
Address-0 Select Bit - Internal registers address selection.  
Address-1 Select Bit - Internal registers address selection.  
Address-2 Select Bit - Internal registers address selection.  
A1  
A2  
-ACK  
Acknowledge(withinternalpull-up)-General purposeinput  
or line printer acknowledge (active low). a logic 0 from the  
printer, indicates successful data transfer to the print buffer.  
-AutoFDXT  
56  
I/O  
General purpose I/O (open drain, with internal pull-up) or  
automatic line feed (open drain input with internal pull-up).  
When this signal is low the printer should automatically line  
feed after each line is printed.  
BIDEN  
BUSY  
CLK  
1
66  
4
I
I
I
Bi-Direction Enable - PD7-PD0 direction select. A logic 0  
sets the parallel port for I/O Select Register Control. A logic  
1 sets the parallel port for Control Register Bit-5 Control.  
Busy (with internal pull-up) - General purpose input or line  
printer busy (active high). can be used as an output from the  
printer to indicate printer is not ready to accept data.  
Clock Input. - An external clock must be connected to this  
pin to clock the baud rate generator and internal circuitry  
(seeProgrammableBaudRateGenerator). Thisinputisnot  
5V tolerant.  
-CSA  
-CSB  
-CSP  
32  
3
I
I
I
Chip Select A - A logic 0 at this pin enables the serial  
channel-A UART registers for CPU data transfers.  
Chip Select B - A logic 0 at this pin enables the serial  
channel-B UART registers for CPU data transfers.  
38  
Printer Port Chip Select - (active low). A logic 0 at this pin  
enables the parallel printer port registers and/or PD7-PD0  
for external CPU data transfers.  
D0-D7  
14-21  
I/O  
Data Bus (Bi-directional) - These pins are the eight bit, three  
state data bus for transferring information to or from the  
controlling CPU. D0 is the least significant bit and the first  
data bit in a transmit or receive serial data stream.  
Rev.3.40  
3
ST16C552/552A  
SYMBOL DESCRIPTION  
Symbol  
Pin  
Signal Type  
Pin Description  
-ERROR  
63  
I
Error, Printer (with internal pull-up) - General purpose input  
or line printer error. This pin may be connected to the active  
low (logic 0) output of a printer to indicate an error condition.  
GND  
INIT  
2,7,54  
27  
Pwr  
I/O  
Signal and Power Ground.  
57  
Initialize (open drain, with internal pull-up) - General pur-  
pose I/O signal. This pin may be connected for initialization  
service of a connected line printer. Generally when this  
signal is a logic 0, any connected printer will be initialized.  
INT A/B  
45,60  
O
O
Interrupt output A/B ( three state active high) - These pins  
provide individual channel interrupts, INT A-B. INT A-B are  
enabled when MCR bit-3 is set to a logic 1, interrupts are  
enabled in the interrupt enable register (IER), and when an  
interrupt condition exists. Interrupt conditions include: re-  
ceiver errors, available receiver buffer data, transmit buffer  
empty, or when a modem status flag is detected.  
-INTP  
59  
Printer Interrupt, - This pin can be used to signal the  
interrupt status of a connected printer. This pin basically  
tracks the -ACK input pin, When INTSEL is a logic 0 and  
interrupts are enabled by bit-4 in the control register. A  
latched mode can be selected by setting INTSEL to a logic  
1. In this case the interrupt -INTP is generated normally but  
does not return to the inactive state until the trailing edge of  
the read cycle (-IOR pin). -INTP is three stated until CON  
bit-4 is set to a logic 1. The difference between the  
ST16C552 and ST16C552A is the output state of INTP.  
INTP is active high (logic 1) on the ST16C552 whereas  
INTPisactivelow(logic0)ontheST16C552Apartwhenthe  
interrupt latch mode is selected.  
INTSEL  
43  
I
Interrupt Select mode - This pin selects the interrupt type for  
the printer port (-INTP). When this pin is a logic 0, the  
external -ACK signal state is generally followed, minus  
some minor propagation delay. Making this pin a logic 1 or  
connectingittoVCCwillsettheinterruptlatchedmode.Inthis  
casetheprinterinterrupt(-INTP)willnotreturntoalogic0on  
the 552 or a logic 1 on the 552A (552A is inverted), until the  
Rev.3.40  
4
ST16C552/552A  
SYMBOL DESCRIPTION  
Symbol  
Pin  
Signal Type  
Pin Description  
trailing edge of -IOR (end of the external CPU read cycle).  
-IOR  
37  
I
Read strobe.- A logic 0 transition on this pin will place the  
contents of an Internal register defined by address bits A0-  
A2 for either UART channels A/B or A0-A1 for the printer  
port, onto D0-D7 data bus for a read cycle by an external  
CPU.  
-IOW  
36  
I
Write strobe.- A logic 0 transition on this pin will transfer the  
data on the internal data bus (D0-D7), as defined by either  
address bits A0-A2 for UART channels A/B or A0-A1 for the  
printerport, intoaninternalregisterduringawritecyclefrom  
an external CPU.  
PD7-PD0  
46-53  
I/O  
PrinterDataport(Bi-directionalthreestate)-Thesepinsare  
theeightbit, threestatedatabusfortransferringinformation  
to or from an external device (usually a printer). D0 is the  
least significant bit. PD7-PD0 are latched during a write  
cycle (output mode).  
PE  
67  
44  
I
Paper Empty - General purpose input or line printer paper  
empty (Internal pull-up). This pin can be connected to  
provide a printer out of paper indication.  
RDOUT  
O
Read Out (active high) - This pin goes to a logic 1 when the  
externalCPUisreadingdatafromthe552/552A. Thissignal  
canbeusedtoenable/disableexternaltransceiversorother  
logic functions.  
-RESET  
39  
I
Master Reset (active low) - a logic 0 on this pin will reset the  
internal registers and all the outputs. The UART transmitter  
output and the receiver input will be disabled during reset  
time. (See ST16C552/552A External Reset Conditions for  
initialization details.)  
-RXRDY A/B  
9,61  
O
Receive Ready A/B (active low). This function is associated  
with the dual channel UARTs and provide the RX FIFO/  
RHR status for individual receive channels (A-B). A logic 0  
indicates there is receive data to read/unload, i.e., receive  
readystatuswithoneormoreRXcharactersavailableinthe  
FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is  
empty or when the programmed trigger level has not been  
Rev.3.40  
5
ST16C552/552A  
SYMBOL DESCRIPTION  
Symbol  
Pin  
Signal Type  
Pin Description  
reached.  
SLCT  
65  
I
Select (with internal pull-up) - General purpose input or line  
printer select status. Normally this pin is connected to a  
printer output (active low) that indicates the ready status of  
a printer, i.e., on-line and/or on-line and ready.  
-SLCTIN  
58  
I/O  
Select In (open drain, with internal pull-up) - General  
purpose I/O or line printer select. This pin can be read via  
Bit-3 in the printer command register, or written via bit-3 in  
the printer control register. As this pin is open-drain, it can  
be wire-or’d with other outputs. Normally this signal is  
connected with a printer to select the printer with an active  
low.  
-STROBE  
55  
I/O  
O
Strobe (open drain, with internal pull-up) - General purpose  
I/O or data strobe output. Normally this output is connected  
to a printer and indicates that valid data is available at the  
printer port (PD0-PD7).  
-TXRDY A/B  
22,42  
Transmit Ready A/B (active low). These outputs provide the  
TX FIFO/THR status for individual transmit channels (A-B).  
As such, an individual channel’s -TXRDY A-B buffer ready  
status is indicated by logic 0, i.e., at least one location is  
empty and available in the FIFO or THR. This pin goes to  
a logic 1 when there are no more empty locations in the  
FIFO or THR.  
VCC  
23,40,64  
29,8  
Pwr  
I
2.97 to 5.5V power supply input. All inputs are 5V tolerant  
except for XTAL1 and all printer port inputs for devices with  
revision"F"andnewer.  
-CD A/B  
Carrier Detect (active low) - These inputs are associated  
with individual UART channels A through B. A logic 0 on this  
pin indicates that a carrier has been detected by the modem  
for that channel.  
-CTS A/B  
28,13  
I
CleartoSend(activelow)-Theseinputsareassociatedwith  
individualUARTchannels,AthroughB.Alogic0onthispin(s)  
indicates the modem or data set is ready to accept transmit  
datafromthe552/552Aforthegivenchannel. Statuscanbe  
testedbyreadingMSRbit-4forthatchannel(s).-CTShasno  
Rev.3.40  
6
ST16C552/552A  
SYMBOL DESCRIPTION  
Symbol  
Pin  
Signal Type  
Pin Description  
effect on the transmit or receive operation.  
-DSR A/B  
31,5  
I
Data Set Ready (active low) - These inputs are associated  
with individual UART channels, A through B. A logic 0 on  
this pin(s) indicates the modem or data set is powered-on  
and is ready for data exchange with the UART. This pin has  
no effect on the UART’s transmit or receive operation.  
-DTR A/B  
25,11  
O
Data Terminal Ready (active low) - These outputs are  
associated with individual UART channels, A through B. A  
logic0onthispin(s)indicatesthatthe552/552Aispowered-  
on and ready. This pin can be controlled via the modem  
control register for channel(s) A-B. Writing a logic 1 to MCR  
bit-0willsetthe-DTRoutputtologic0, enablingthemodem.  
This pin will be a logic 1 after writing a logic 0 to MCR bit-  
0, or after a reset. This pin has no effect on the UART’s  
transmit or receive operation.  
-RI A/B  
30,6  
I
Ring Indicator (active low) - These inputs are associated  
with individual UART channels, A through B. A logic 0 on  
this pin(s) indicates the modem has received a ringing  
signal from the telephone line(s). A logic 1 transition on this  
inputpinwillgenerateaninterruptfortheringingchannel(s).  
This pin does not have any effect on the transmit or receive  
operation.  
-RTS A/B  
24,12  
O
RequesttoSend(activelow)-Theseoutputsareassociated  
with individual UART channels, A through B. A logic 0 on the  
-RTS pin(s) indicates the transmitter has data ready and  
waiting to send for the given channel(s). Writing a logic 1 in  
the modem control register (MCR bit-1) will set this pin to a  
logic 0 indicating data is available. After a reset this pin will  
be set to a logic 1. This pin does not have any effect on the  
transmit or receive operation.  
RX A/B  
41,62  
I
Receive Data Input, RX A-B. - These inputs are associated  
withindividualserialchannel(s)tothe552.TheRXsignalwill  
bealogic1duringreset,idle(nodata),orwhenthetransmitter  
is disabled. During the local loop-back mode, the RX input  
pins are disabled and TX data is internally connected to the  
Rev.3.40  
7
ST16C552/552A  
Symbol  
Pin  
Signal Type  
Pin Description  
UARTRXInputs,internally.  
TXA/B  
26,10  
O
Transmit Data, TX A-B - These outputs are associated with  
individual serial transmit channel(s) from the 552/552A.  
The TX signal will be a logic 1 during reset, idle (no data),  
or when the transmitter is disabled. During the local loop-  
back mode, the TX output pins are disabled and TX data is  
internally connected to the UART RX Inputs.  
GENERAL DESCRIPTION  
Howeverwiththe16byteFIFOinthe552/552A,thedata  
bufferwillnotrequireunloading/loadingfor1.53ms.This  
increases the service interval giving the external CPU  
additional time for other applications and reducing the  
overallUARTinterruptservicingtime.Inaddition,the4  
selectable levels of FIFO trigger interrupt is uniquely  
provided for maximum data throughput performance  
especially when operating in a multi-channel environ-  
ment.TheFIFOmemorygreatlyreducesthebandwidth  
requirementoftheexternalcontrollingCPU,increases  
performance,andreducespowerconsumption.  
The 552/552A provides serial asynchronous receive  
data synchronization, parallel-to-serial and serial-to-  
parallel data conversions for both the transmitter and  
receiver sections. These functions are necessary for  
convertingtheserialdatastreamintoparalleldatathat  
is required with digital data systems. Synchronization  
for the serial data stream is accomplished by adding  
start and stops bits to the transmit data to form a data  
character (character orientated protocol). Data integ-  
rity is insured by attaching a parity bit to the data  
character. The parity bit is checked by the receiver for  
any transmission bit errors. The electronic circuitry to  
provide all these functions is fairly complex especially  
when manufactured on a single integrated silicon  
chip. The 552/552A represents such an integration  
with greatly enhanced features. The 552/552A is  
fabricated with an advanced CMOS process.  
The 552/552A combines the package functions of a  
dual UART and a printer interface on a single inte-  
grated chip. The 552/552A UART is indented to be  
software compatible with the INS8250/NS16C550  
while the bi-directional printer interface mode is in-  
tended to operate with a CENTRONICS type parallel  
printer. However, the printer interface is designed  
such that it may be configured to operate with other  
parallelprinterinterfacesorusedasageneralpurpose  
parallel interface. The 552/552A is available in two  
versions, the ST16C552 and the ST16C552A. The  
552A provides a active low (logic 0) interrupt for the  
printer port (INTP) while the 552 provides an active  
high (logic 1) INTP interrupt. Additionally, the 552A  
does not support the power down feature.  
The 552/552A is an upward solution that provides 16  
bytes of transmit and receive FIFO memory, instead  
of none in the 16C452. The 552/552A is designed to  
work with high speed modems and shared network  
environments, that require fast data processing time.  
Increased performance is realized in the 552/552A by  
the transmit and receive FIFO’s. This allows the  
external processor to handle more networking tasks  
within a given time. For example, the ST16C452  
without a receive FIFO, will require unloading of the  
RHR in 95.5 microseconds (This example uses a  
character length of 11 bits, including start/stop bits at  
115.2Kbps). This means the external CPU will have to  
service the receive FIFO every 100 microseconds.  
The 552/552A is capable of operation to 1.5Mbps with  
a 24 MHz external clock input. With an external clock  
input of 1.8432 MHz the user can select data rates up  
to 115.2 Kbps.  
Rev.3.40  
8
ST16C552/552A  
registers (PR), I/O status register (SR), I/O select  
register (IOSEL), and a command and control register  
(COM/CON). Register functions are more fully de-  
scribedinthefollowingparagraphs.  
The rich feature set of the 552/552A is available  
through internal registers. Selectable receive FIFO  
trigger levels, selectable TX and RX baud rates,  
modem interface controls, and a power-down mode  
are all standard features. Following a power on reset  
oranexternalreset, the552/552Aissoftwarecompat-  
ible with the previous generation, 16C452.  
FUNCTIONAL DESCRIPTIONS  
Functional Modes  
Two functional user modes are selectable for the 552/  
552A package. The first of these provides the dual  
UART functions, while the other provides the func-  
tions of a parallel printer interface. These features are  
available through selection at the package interface  
select pins.  
UARTA-BFunctions  
The UART mode provides the user with the capability  
to transfer information between an external CPU and  
the 552/552A package. A logic 0 on chip select pins -  
CSA or -CSB allows the user to configure, send data,  
and/or receive data via the UART channels A-B.  
Printer Port Functions  
The Printer mode provides the user with the capability  
totransferinformationbetweenanexternalCPUandthe  
552/552A parallel printer port. A logic 0 on chip select  
pin -CSP allows the user to configure, send data, and/  
or receive data via the bi-directional parallel 8-bit data  
bus,PD0-PD7.  
InternalRegisters  
The552/552Aprovides12internalregistersformonitor-  
ing and control of the UART functions and another 6  
registersformonitoringandcontrollingtheprinterport.  
TheseresistersareshowninTable4below.TheUART  
registersfunctionasdataholdingregisters(THR/RHR),  
interruptstatusandcontrolregisters(IER/ISR),aFIFO  
controlregister(FCR), linestatusandcontrolregisters  
(LCR/LSR),modemstatusandcontrolregisters(MCR/  
MSR),programmabledatarate(clock)controlregisters  
(DLL/DLM),andauserassessablescratchpadregister  
(SPR).The printerportregistersfunctionsdataholding  
Rev.3.40  
9
ST16C552/552A  
Table 4, INTERNAL REGISTER DECODE  
A2  
A1  
A0  
READMODE  
WRITEMODE  
General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): Note 1*  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ReceiveHoldingRegister  
InterruptStatusRegister  
TransmitHoldingRegister  
InterruptEnableRegister  
FIFOControlRegister  
LineControlRegister  
ModemControlRegister  
Line Status Register  
Modem Status Register  
ScratchpadRegister  
ScratchpadRegister  
Baud Rate Register Set (DLL/DLM): Note *2  
0
0
0
0
0
1
LSB of Divisor Latch  
MSB of Divisor Latch  
LSB of Divisor Latch  
MSB of Divisor Latch  
Printer Port Set (PR/SR/IOSEL/COM/CON): Note *3  
X
X
X
0
0
1
0
1
0
PORTREGISTER  
STATUSREGISTER  
COMMANDREGISTER  
PORTREGISTER  
I/OSELECTREGISTER  
CONTROLREGISTER  
Note 1* The General Register set is accessible only when CS A or CS B is a logic 0.  
Note 2* The Baud Rate register set is accessible only when CS A or CS B is a logic 0 and LCR bit-7 is a logic 1.  
Note 3*: Printer Port Register set is accessible only when -CSP is a logic 0 in conjunction with the states of the  
interface signal BIDEN and Printer Control Register bit-5 or IOSEL register.  
Rev.3.40  
10  
ST16C552/552A  
FIFO Operation  
P(Programmedwordlength)+12. Toconvertthetime  
outvaluetoacharactervalue, theuserhastoconsider  
the complete word length, including data information  
length, start bit, parity bit, and the size of stop bit, i.e.,  
1X, 1.5X, or 2X bit times.  
The 16 byte transmit and receive data FIFO’s are  
enabledbytheFIFOControlRegister(FCR)bit-0. The  
user can set the receive trigger level via FCR bits 6/  
7 but not the transmit trigger level. The transmit  
interrupt trigger level is set to 16 following a reset. The  
receiver FIFO section includes a time-out function to  
ensure data is delivered to the external CPU. An  
interrupt is generated whenever the Receive Holding  
Register (RHR) has not been read following the load-  
ing of a character or the receive trigger level has not  
been reached.  
Example -A: If the user programs a word length of 7,  
with no parity and one stop bit, the time out will be:  
T=4X7(programmedwordlength)+12=40bittimes.  
The character time will be equal to 40 / 9 = 4.4  
characters, or as shown in the fully worked out ex-  
ample: T = [(programmed word length = 7) + (stop bit  
= 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) =  
4.4 characters.  
Hardware/Software and Time-out Interrupts  
Example -B: If the user programs the word length = 7,  
with parity and one stop bit, the time out will be:  
T=4X7(programmedwordlength)+12=40bittimes.  
Character time = 40 / 10 [ (programmed word length  
= 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4  
characters.  
TheinterruptsareenabledbyIERbits0-3.Caremustbe  
takenwhenhandlingtheseinterrupts.Followingareset  
the transmitter interrupt is enabled, the 552/552A will  
issue an interrupt to indicate that transmit holding  
register is empty. This interrupt must be serviced prior  
tocontinuingoperations.TheLSRregisterprovidesthe  
current singular highest priority interrupt only. It could  
be noted that CTS and RTS interrupts have lowest  
interrupt priority. A condition can exist where a higher  
priorityinterruptmaymaskthelowerpriorityCTS/RTS  
interrupt(s). Only after servicing the higher pending  
interruptwillthelowerpriorityCTS/RTSinterrupt(s)be  
reflected in the status register. Servicing the interrupt  
without investigating further interrupt conditions can  
result in data errors.  
Programmable Baud Rate Generator  
The 552/552A supports high speed modem technolo-  
giesthathaveincreasedinputdataratesbyemploying  
data compression schemes. For example a 33.6Kbps  
modem that employs data compression may require a  
115.2Kbpsinputdatarate. A128.0KbpsISDNmodem  
that supports data compression may need an input  
data rate of 460.8Kbps. The 552/552A can support a  
standard data rate of 921.6Kbps.  
When two interrupt conditions have the same priority,  
it is important to service these interrupts correctly.  
Receive Data Ready and Receive Time Out have the  
same interrupt priority (when enabled by IER bit-3).  
The receiver issues an interrupt after the number of  
characters have reached the programmed trigger  
level. In this case the 552/552A FIFO may hold more  
characters than the programmed trigger level. Follow-  
ingtheremovalofadatabyte, theusershouldrecheck  
LSR bit-0 for additional characters. A Receive Time  
OutwillnotoccurifthereceiveFIFOisempty.Thetime  
out counter is reset at the center of each stop bit  
receivedoreachtimethereceiveholdingregister(RHR)  
isread(seeFigure4,ReceiveTime-outInterrupt).The  
actual time out value is T (Time out length in bits) = 4 X  
Single baud rate generator is provided for the trans-  
mitter and receiver, allowing independent TX/RX  
channel control. The programmable Baud Rate Gen-  
erator is capable of accepting an input clock up to 24  
MHz, as required for supporting a 1.5Mbps data rate.  
The 552/552A requires that an external clock source  
be connected to the CLK input pin to clock the internal  
baudrategeneratorforstandardorcustomrates. (see  
Baud Rate Generator Programming below).  
Thegeneratordividestheinput16Xclockbyanydivisor  
from1to216 -1.The552/552Adividesthebasicexternal  
clockby16.Thebasic16Xclockprovidestableratesto  
support standard and custom applications using the  
Rev.3.40  
11  
ST16C552/552A  
samesystemdesign.Theratetableisconfiguredviathe  
DLL and DLM internal register functions. Customized  
Baud Rates can be achieved by selecting the proper  
divisorvaluesfortheMSBandLSBsectionsofbaudrate  
generator.  
forselectingthedesiredfinalbaudrate.Theexamplein  
Table 5 below, shows the selectable baud rate table  
available when using a 1.8432 MHz external clock  
input.  
Programming the Baud Rate Generator Registers  
DLM (MSB) and DLL (LSB) provides a user capability  
Table 5, BAUD RATE GENERATOR PROGRAMMING TABLE (1.8432 MHz CLOCK):  
Output  
Output  
User  
DLM  
Program  
Value  
DLL  
Program  
Value  
Baud Rate 16 x Clock 16 x Clock  
MCR  
Divisor  
(Decimal)  
Divisor  
(HEX)  
(HEX)  
(HEX)  
50  
110  
150  
300  
600  
1200  
2400  
4800  
7200  
9600  
19.2k  
38.4k  
57.6k  
115.2k  
2304  
1047  
768  
384  
192  
96  
48  
24  
16  
12  
900  
417  
300  
180  
C0  
60  
30  
18  
10  
0C  
06  
09  
04  
03  
01  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
17  
00  
80  
C0  
60  
30  
18  
10  
0C  
06  
03  
02  
01  
6
3
2
1
03  
02  
01  
Rev.3.40  
12  
ST16C552/552A  
DMA Operation  
togetherinternally(SeeFigure6).The-CTS,-DSR,-CD,  
and -RI are disconnected from their normal modem  
control inputs pins, and instead are connected inter-  
nally to -DTR, -RTS, INT enable and MCR bit-2. Loop-  
back test data is entered into the transmit holding  
register via the user data bus interface, D0-D7. The  
transmitUARTserializesthedataandpassestheserial  
data to the receive UART via the internal loop-back  
connection.ThereceiveUARTconvertstheserialdata  
backintoparalleldatathatisthenmadeavailableatthe  
user data interface, D0-D7. The user optionally com-  
paresthereceiveddatatotheinitialtransmitteddatafor  
verifyingerrorfreeoperationoftheUARTTX/RXcircuits.  
The 552/552A FIFO trigger level provides additional  
flexibility to the user for block mode operation. LSR  
bits 5-6 provide an indication when the transmitter is  
empty or has an empty location(s). The user can  
optionally operate the transmit and receive FIFO’s in  
the DMA mode (FCR bit-3). When the transmit and  
receive FIFO’s are enabled and the DMA mode is  
deactivated (DMA Mode “0”), the 552/552A activates  
the interrupt output pin for each data transmit or  
receive operation. When DMA mode is activated  
(DMA Mode “1”), the user takes the advantage of  
block mode operation by loading or unloading the  
FIFO in a block sequence determined by the receive  
trigger level and the transmit FIFO. In this mode, the  
552/552A sets the interrupt output pin when charac-  
ters in the transmit FIFO is below 16, or the characters  
in the receive FIFO’s are above the receive trigger  
level.  
In this mode, the receiver and transmitter interrupts  
are fully operational. The Modem Control Interrupts  
are also operational. However, the interrupts can only  
be read using lower four bits of the Modem Control  
Register (MCR bits 0-3) instead of the four Modem  
Status Register bits 4-7. The interrupts are still con-  
trolled by the IER.  
Power Down Mode  
The 552 is designed to operate with low power con-  
sumption. The 552 (only) is designed with a special  
power down mode to further reduce power consump-  
tion when the chip is not being used. When MCR bit-  
7 and IER bit-5 are enabled (set to a logic 1), the 552  
powers down. The use of two power down enable bits  
helps to prevent accidental software shut-down. The  
552willremainpowereddownuntildisabledbysetting  
either IER bit-5 or MCR bit-7 to a logic 0.  
Loop-back Mode  
The internal loop-back capability allows onboard diag-  
nostics. In the loop-back mode the normal modem  
interface pins are disconnected and reconfigured for  
loop-back internally. MCR register bits 0-3 are used  
for controlling loop-back diagnostic testing. In the  
loop-backmodeINTenableandMCRbit-2intheMCR  
register (bits 2,3) control the modem -RI and -CD  
inputs respectively. MCR signals -DTR and -RTS (bits  
0-1) are used to control the modem -CTS and -DSR  
inputs respectively. The transmitter output (TX) and  
the receiver input (RX) are disconnected from their  
associated interface pins, and instead are connected  
Rev.3.40  
13  
ST16C552/552A  
Figure6,INTERNALLOOP-BACKMODEDIAGRAM  
Transmit  
FIFO  
Transmit  
Shift  
TX A,B  
D0-D7  
-IOR  
Registers  
Register  
-IOW  
-RESET  
BIDEN  
Receive  
FIFO  
Receive  
Shift  
RX A,B  
Registers  
Register  
Printer  
Data  
PD0-PD7  
Ports  
-STROBE  
INIT  
-AUTOFDX  
-SELCTIN  
A0-A2  
-CSA  
-CSB  
-CSP  
Printer  
Control  
Logic  
PE, SELECT  
-BUSY, -ACK  
ERROR  
-RTS  
-CD  
-DTR  
-RI  
(-OP1)  
-DSR  
Clock  
&
Baud Rate  
Generator  
INT A,B  
INTP  
-RXRDY  
-TXRDY  
(-OP2)  
-CTS  
Rev.3.40  
14  
ST16C552/552A  
Printer Port  
inputand/oroutputfunctions.Thesignalshaveinternal  
pull-up resistors and can be wire-or’d. Normally, -  
STROBE is used to strobe PD0-PD7 bus data into a  
printerinputbuffer.-SLCTINnormallyselectstheprinter  
while AutoFDXT signals the printer to auto-linefeed.  
Other signals provide similar printer functions but are  
notbi-directional.Theprinterfunctionsforthesesignals  
are described in table 1, Symbol Description.  
The552/552Acontainsageneralpurpose8-bitparallel  
interface port that is designed to directly interface with  
a CENTRONICS Printer. A number of the control/  
interrupt signals and the 8-bit data bus have been  
designed as bi-directional data buses. This allows the  
interfacetofunctionwithotherdeviceparalleldatabus  
applications.Signal-ACKisusedtogeneratean-INTP  
interfaceinterruptthatwouldnormallybeconnectedto  
the user CPU. -INTP can be made to follow the -ACK  
signal, normal mode (see Figure 7) or it can be config-  
ured for the latch mode. In the latch mode the interrupt  
is not cleared until printer status register (SR) is read.  
Another signal (INIT) can be made to function as an  
outgoing or incoming interrupt, or combined with other  
interruptstoprovideacommonwire-orinterruptoutput.  
Interfacesignals-STROBE,-AutoFDXT,and-SLCTIN  
are bi-directional and can be used as combinations of  
The interface provides a mode steering signal called  
BIDEN.BIDENcontrolsthebi-directional8-bitdatabus  
(PD0-PD7)direction,inputoroutput.WhenBIDENisa  
logic 1 a single control bit (D5) in the control register  
sets the input or output mode. Setting BIDEN to a logic  
0 however sets an IBM interface compatible mode. In  
thismodethebusdirection(input/output)issetbyeight  
data bits in the IOSEL register. An AA (Hex) pattern  
sets the input mode while a 55 (hex) pattern sets the  
outputmode.I/OdirectionisdepictedinTable6below.  
Table 6, PD0-PD7 I/O DIRECTION MODE SELECTION  
PORTDIRECTION  
BIDEN  
CONTROLREGISTER(D5)  
I/OSELECTREGISTER  
Input mode  
Output mode  
Output mode  
Input mode  
0
0
1
1
X (Note 4)  
X (Note 4)  
AA Hex  
55 Hex  
X (Note 4)  
X (Note 4)  
0
1
Note: 4 = don’t care  
Rev.3.40  
15  
ST16C552/552A  
REGISTER FUNCTIONAL DESCRIPTIONS  
The following table delineates the assigned bit functions for the eighteen 552/552A internal registers. The  
assigned bit functions are more fully defined in the following paragraphs.  
Table 7, ST16C552/552A INTERNAL REGISTERS  
A2 A1 A0  
Register  
[Default]  
Note 5*  
BIT-7  
BIT-6  
BIT-5  
BIT-4  
BIT-3  
BIT-2  
BIT-1  
BIT-0  
General Register Set: Note 1*  
0
0
0
0
0
0
0
0
1
RHR [XX]  
THR [XX]  
IER [00]  
bit-7  
bit-7  
0
bit-6  
bit-6  
0
bit-5  
bit-5  
bit-4  
bit-4  
0
bit-3  
bit-3  
bit-2  
bit-2  
bit-1  
bit-1  
bit-0  
bit-0  
En  
Pwr  
down  
mode  
Modem  
Status  
Interrupt  
Receive  
Line  
Status  
interrupt  
Transmit  
Holding  
Register  
interrupt  
Receive  
Holding  
Register  
0
0
0
1
1
1
1
1
0
0
0
0
1
0
1
FCR [00]  
ISR [01]  
LCR [00]  
MCR [00]  
LSR [60]  
RCVR  
trigger  
(MSB)  
RCVR  
trigger  
(LSB)  
0
0
0
DMA  
mode  
select  
XMIT  
FIFO  
reset  
RCVR  
FIFO  
reset  
FIFO  
enable  
FIFO’s  
enabled  
FIFO’s  
enabled  
0
INT  
priority  
bit-2  
INT  
priority  
bit-1  
INT  
priority  
bit-0  
INT  
status  
divisor  
latch  
enable  
set  
break  
set  
parity  
even  
parity  
parity  
enable  
stop  
bits  
word  
length  
bit-1  
word  
length  
bit-0  
Pwr  
down  
0
0
loop  
back  
INT A/B  
enable  
[X]  
-RTS  
-DTR  
FIFO  
data  
THR &  
TSR  
THR.  
empty  
break  
interrupt  
framing  
error  
parity  
error  
overrun  
error  
receive  
data  
error  
empty  
ready  
1
1
1
1
0
1
MSR [X0]  
SPR [FF]  
CD  
RI  
DSR  
bit-5  
CTS  
bit-4  
delta  
-CD  
delta  
-RI  
delta  
-DSR  
delta  
-CTS  
bit-7  
bit-6  
bit-3  
bit-2  
bit-1  
bit-0  
Special Register Set: Note *2  
0
0
0
0
0
1
DLL[XX]  
DLM[XX]  
bit-7  
bit-6  
bit-5  
bit-4  
bit-3  
bit-2  
bit-1  
bit-9  
bit-0  
bit-8  
bit-15  
bit-14  
bit-13  
bit-12  
bit-11  
bit-10  
Rev.3.40  
16  
ST16C552/552A  
A2 A1 A0  
Register  
[Default]  
Note 5*  
BIT-7  
BIT-6  
BIT-5  
BIT-4  
BIT-3  
BIT-2  
BIT-1  
BIT-0  
Printer Port Register Set: Note 3*  
[X]  
[X]  
[X]  
0
0
0
0
0
1
PR[00]  
PR[00]  
SR[4F]  
bit-7  
bit-7  
bit-6  
bit-6  
bit-5  
bit-5  
PE  
bit-4  
bit-4  
bit-3  
bit-3  
bit-2  
bit-2  
-IRQ  
bit-1  
bit-1  
bit-0  
bit-0  
-Busy  
-ACK  
SLCT  
Error  
State  
logic  
“1”  
logic  
“1”  
[X]  
[X]  
0
1
1
0
IOSEL  
bit-7  
bit-6  
bit-5  
bit-4  
bit-3  
bit-2  
INIT  
bit-1  
bit-0  
COM[E0]  
logic  
“1”  
logic  
“1”  
logic  
“1”  
-INTP  
Enable  
-SLCTIN  
-Auto  
FDXT  
-STROBE  
[X]  
1
0
CON[00]  
[X]  
[X]  
PD 0-7  
-INTP  
-SLCTIN  
INIT  
-Auto  
-STROBE  
IN/OUT  
Enable  
FDXT  
Note 1* The General Register set is accessible only when CS A or CS B is a logic 0.  
Note 2* The Baud Rate register set is accessible only when CS A or CS B is a logic 0 and LCR bit-7 is a logic 1.  
Note 3*: Printer Port Register set is accessible only when -CSP is a logic 0 in conjunction with the states of the  
interface signal BIDEN and Printer Control Register bit-5 or IOSEL register.  
Note 5* The value between the square brackets represents the register’s initialized HEX value, X =N/A.  
oneFIFOlocationavailable).  
MODEM (UART) REGISTER DESCRIPTIONS  
The serial receive section also contains an 8-bit  
Receive Holding Register, RHR. Receive data is  
removed from the 552/552A and receive FIFO by  
reading the RHR register. The receive section pro-  
vides a mechanism to prevent false starts. On the  
falling edge of a start or false start bit, an internal  
receiver counter starts counting clocks at the 16x  
clock rate. After 7 1/2 clocks the start bit time should  
be shifted to the center of the start bit. At this time the  
start bit is sampled and if it is still a logic 0 it is  
validated. Evaluating the start bit in this manner  
prevents the receiver from assembling a false charac-  
ter. Receiver status codes will be posted in the LSR.  
Transmit (THR) and Receive (RHR) Holding Reg-  
isters  
The serial transmitter section consists of an 8-bit  
Transmit Hold Register (THR) and Transmit Shift  
Register (TSR). The status of the THR is provided in  
the Line Status Register (LSR). Writing to the THR  
transfers the contents of the data bus (D7-D0) to the  
THR, providing that the THR or TSR is empty. The  
THR empty flag in the LSR register will be set to a logic  
1 when the transmitter is empty or when data is  
transferred to the TSR. Note that a write operation can  
be performed when the transmit holding register  
empty flag is set (logic 0 = FIFO full, logic 1= at least  
Rev.3.40  
17  
ST16C552/552A  
Interrupt Enable Register (IER)  
D) LSR BIT-6 will indicate when both the transmit  
FIFO and transmit shift register are empty.  
The Interrupt Enable Register (IER) masks the inter-  
rupts from receiver ready, transmitter empty, line  
status and modem status registers. These interrupts  
would normally be seen on the INT A,B output pins.  
E) LSR BIT-7 will indicate any FIFO data errors.  
IER BIT-0:  
IER Vs Receive FIFO Interrupt Mode Operation  
This interrupt will be issued when the FIFO has  
reached the programmed trigger level or is cleared  
when the FIFO drops below the trigger level in the  
FIFO mode of operation.  
Logic 0 = Disable the receiver ready interrupt. (normal  
default condition)  
When the receive FIFO (FCR BIT-0 = a logic 1) and  
receive interrupts (IER BIT-0 = logic 1) are enabled,  
the receive interrupts and register status will reflect  
the following:  
Logic 1 = Enable the receiver ready interrupt.  
A) The receive data available interrupts are issued to  
the external CPU when the FIFO has reached the  
programmed trigger level. It will be cleared when the  
FIFO drops below the programmed trigger level.  
IER BIT-1:  
This interrupt will be issued whenever the THR is  
empty and is associated with bit-1 in the LSR register.  
Logic 0 = Disable the transmitter empty interrupt.  
(normal default condition)  
B) FIFO status will also be reflected in the user  
accessible ISR register when the FIFO trigger level is  
reached. Both the ISR register status bit and the  
interrupt will be cleared when the FIFO drops below  
the trigger level.  
Logic 1 = Enable the transmitter empty interrupt.  
IER BIT-2:  
This interrupt will be issued whenever a fully as-  
sembled receive character is transferred from the  
RSR to the RHR/FIFO, i.e., data ready, LSR bit-0.  
Logic 0 = Disable the receiver line status interrupt.  
(normal default condition)  
C) The data ready bit (LSR BIT-0) is set as soon as a  
character is transferred from the shift register to the  
receive FIFO. It is reset when the FIFO is empty.  
Logic 1 = Enable the receiver line status interrupt.  
IER Vs Receive/Transmit FIFO Polled Mode Op-  
eration  
IER BIT-3:  
Logic 0 = Disable the modem status register interrupt.  
(normal default condition)  
Logic 1 = Enable the modem status register interrupt.  
When FCR BIT-0 equals a logic 1; resetting IER bits  
0-3 enables the 552/552A in the FIFO polled mode of  
operation. Since the receiver and transmitter have  
separate bits in the LSR either or both can be used in  
the polled mode by selecting respective transmit or  
receive control bit(s).  
IER BIT -4:  
Not Used - initialized to a logic 0.  
IER BIT-5: (ST16C552 only)  
A) LSR BIT-0 will be a logic 1 as long as there is one  
byte in the receive FIFO.  
Logic 0 = Disable the power down mode. (normal  
default condition). The ST16C552A does not support  
the power down mode and this bit is set to “0”.  
Logic 1 = Enable the power down mode (MCR bit-7  
must also be a logic 1 before power down will be  
activated).  
B) LSR BIT 1-4 will provide the type of errors encoun-  
tered, if any.  
C) LSR BIT-5 will indicate when the transmit FIFO is  
empty.  
Rev.3.40  
18  
ST16C552/552A  
IER BIT 6-7:  
FCR BIT-2:  
Not Used - initialized to a logic 0.  
Logic 0 = No FIFO transmit reset. (normal default  
condition)  
FIFO Control Register (FCR)  
Logic 1 = Clears the contents of the transmit FIFO and  
resets the FIFO counter logic (the transmit shift regis-  
ter is not cleared or altered). This bit will return to a  
logic 0 after clearing the FIFO.  
This register is used to enable the FIFO’s, clear the  
FIFO’s, set the receive FIFO trigger levels, and select  
the DMA mode. The DMA, and FIFO modes are  
defined as follows:  
FCR BIT-3:  
Logic 0 = Set DMA mode “0”. (normal default condi-  
DMA MODE  
tion)  
Mode 0 Set and enable the interrupt for each  
single transmit or receive operation, and is similar to  
the ST16C450 mode. Transmit Ready (-TXRDY) will  
go to a logic 0 when ever an empty transmit space is  
available in the Transmit Holding Register (THR).  
Receive Ready (-RXRDY) will go to a logic 0 when-  
ever the Receive Holding Register (RHR) is loaded  
with a character.  
Mode 1 Set and enable the interrupt in a block  
mode operation. The transmit interrupt is set when the  
transmit FIFO is below the programmed trigger level.  
-TXRDY remains a logic 0 as long as one empty FIFO  
location is available. The receive interrupt is set when  
the receive FIFO fills to the programmed trigger level.  
However the FIFO continues to fill regardless of the  
programmed level until the FIFO is full. -RXRDY  
remains a logic 0 as long as the FIFO fill level is above  
the programmed trigger level.  
Logic 1 = Set DMA mode “1.”  
Transmit operation in mode “0”:  
When the 552/552A is in the ST16C450 mode (FIFO’s  
disabled, FCR bit-0 = logic 0) or in the FIFO mode  
(FIFO’s enabled, FCR bit-0 = logic 1, FCR bit-3 = logic  
0) and when there are no characters in the transmit  
FIFO or transmit holding register, the -TXRDY pin will  
be a logic 0. Once active the -TXRDY pin will go to a  
logic 1 after the first character is loaded into the  
transmit holding register.  
Receive operation in mode “0”:  
When the 552/552A is in mode “0” (FCR bit-0 = logic  
0) or in the FIFO mode (FCR bit-0 = logic 1, FCR bit-  
3 = logic 0) and there is at least one character in the  
receive FIFO, the -RXRDY pin will be a logic 0. Once  
active the -RXRDY pin will go to a logic 1 when there  
are no more characters in the receiver.  
FCR BIT-0:  
Transmit operation in mode “1”:  
Logic 0 = Disable the transmit and receive FIFO.  
(normal default condition)  
Logic 1 = Enable the transmit and receive FIFO. This  
bit must be a “1” when other FCR bits are written to or  
they will not be programmed.  
When the 552/552A is in FIFO mode ( FCR bit-0 =  
logic 1, FCR bit-3 = logic 1 ), the -TXRDY pin will be  
a logic 1 when the transmit FIFO is completely full. It  
will be a logic 0 if one or more FIFO locations are  
empty.  
FCR BIT-1:  
Receive operation in mode “1”:  
Logic 0 = No FIFO receive reset. (normal default  
condition)  
Logic 1 = Clears the contents of the receive FIFO and  
resets the FIFO counter logic (the receive shift regis-  
ter is not cleared or altered). This bit will return to a  
logic 0 after clearing the FIFO.  
Whenthe552/552AisinFIFOmode(FCRbit-0=logic  
1, FCR bit-3 = logic 1) and the trigger level has been  
reached, or a Receive Time Out has occurred, the -  
RXRDY pin will go to a logic 0. Once activated, it will  
go to a logic 1 after there are no more characters in the  
FIFO.  
Rev.3.40  
19  
ST16C552/552A  
FCR BIT 4-5:  
Interrupt Status Register (ISR)  
Not Used - initialized to a logic 0.  
The 552/552A provides four levels of prioritized inter-  
rupts to minimize external software interaction. The  
Interrupt Status Register (ISR) provides the user with  
four interrupt status bits. Performing a read cycle on  
the ISR will provide the user with the highest pending  
interrupt level to be serviced. No other interrupts are  
acknowledged until the pending interrupt is serviced.  
Whenever the interrupt status register is read, the  
interrupt status is cleared. However it should be noted  
thatonlythecurrentpendinginterruptisclearedbythe  
read. A lower level interrupt may be seen after reread-  
ing the interrupt status bits. The Interrupt Source  
Table8(below)showsthedatavalues(bits0-3)forthe  
four prioritized interrupt levels and the interrupt  
sourcesassociatedwitheachoftheseinterruptlevels:  
FCR BIT 6-7: (logic 0 or cleared is the default condi-  
tion, RX trigger level = 1)  
These bits are used to set the trigger level for the  
receive FIFO interrupt.  
An interrupt is generated when the number of charac-  
ters in the FIFO equals the programmed trigger level.  
However the FIFO will continue to be loaded until it is  
full.  
BIT-7  
BIT-6  
RX FIFO trigger level  
0
0
1
1
0
1
0
1
01  
04  
08  
14  
Table8, INTERRUPTSOURCETABLE  
Priority  
Level  
[ISR BITS]  
Bit-3 Bit-2 Bit-1 Bit-0 Source of the interrupt  
1
2
2
3
4
0
0
1
0
0
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
LSR (Receiver Line Status Register)  
RXRDY (Received Data Ready)  
RXRDY (Receive Data time out)  
TXRDY (Transmitter Holding Register Empty)  
MSR (Modem Status Register)  
Rev.3.40  
20  
ST16C552/552A  
ISR BIT-0:  
BIT-2  
Word length  
Stop bit  
length  
(Bit time(s))  
Logic 0 = An interrupt is pending and the ISR contents  
may be used as a pointer to the appropriate interrupt  
service routine.  
Logic 1 = No interrupt pending. (normal default condi-  
tion)  
0
1
1
5,6,7,8  
5
6,7,8  
1
1-1/2  
2
ISRBIT1-3:(logic0orclearedisthedefaultcondition)  
These bits indicate the source for a pending interrupt  
at interrupt priority levels 1, 2, and 3 (See Interrupt  
Source Table).  
LCR BIT-3:  
Parity or no parity can be selected via this bit.  
Logic 0 = No parity. (normal default condition)  
Logic 1 = A parity bit is generated during the transmis-  
sion, receiver checks the data and parity for transmis-  
sion errors.  
ISRBIT4-5:(logic0orclearedisthedefaultcondition)  
Not Used - initialized to a logic 0.  
ISRBIT6-7:(logic0orclearedisthedefaultcondition)  
These bits are set to a logic 0 when the FIFO’s are not  
beingusedinthe16C450mode.Theyaresettoalogic  
1 when the FIFO’s are enabled in the 16C552/552A  
mode.  
LCR BIT-4:  
If the parity bit is enabled with LCR bit-3 set to a logic  
1, LCR BIT-4 selects the even or odd parity format.  
Logic 0 = ODD Parity is generated by forcing an odd  
number of logic 1’s in the transmitted data. The  
receiver must be programmed to check the same  
format. (normal default condition)  
Logic 1 = EVEN Parity is generated by forcing an even  
the number of logic 1’s in the transmitted. The receiver  
must be programmed to check the same format.  
Line Control Register (LCR)  
The Line Control Register is used to specify the  
asynchronous data communication format. The word  
length, the number of stop bits, and the parity are  
selected by writing the appropriate bits in this register.  
LCR BIT 0-1: (logic 0 or cleared is the default condi-  
LCR BIT-5:  
tion)  
If the parity bit is enabled, LCR BIT-5 selects the  
forced parity format.  
LCR BIT-5 = logic 0, parity is not forced. (normal  
default condition)  
These two bits specify the word length to be transmit-  
ted or received.  
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit  
is forced to a logical 1 for the transmit and receive  
data.  
BIT-1 BIT-0  
Word length  
0
0
1
1
0
1
0
1
5
6
7
8
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit  
is forced to a logical 0 for the transmit and receive  
data.  
LCR BIT-2: (logic 0 or cleared is the default condition)  
The length of stop bit is specified by this bit in  
conjunction with the programmed word length.  
Rev.3.40  
21  
ST16C552/552A  
loop-back mode this bit is use to write the state of the  
modem -RI interface signal.  
LCR  
LCR  
LCR  
Parity selection  
Bit-5 Bit-4 Bit-3  
MCR BIT-3: (Used to control the modem -CD signal  
in the loop-back mode.)  
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
No parity  
Odd parity  
Even parity  
Force parity odd parity  
Forced even parity  
Logic 0 = Forces INT (A-B) outputs to the three state  
mode. (normal default condition) In the Loop-back  
mode, sets -CD internally to a logic 1.  
Logic 1 = Forces the INT (A-B) outputs to the active  
mode. In the Loop-back mode, sets -CD internally to  
a logic 0.  
LCR BIT-6:  
MCR BIT-4:  
When enabled the Break control bit causes a break  
condition to be transmitted (the TX output is forced to  
a logic 0 state). This condition exists until disabled by  
setting LCR bit-6 to a logic 0.  
Logic 0 = Disable loop-back mode. (normal default  
condition)  
Logic 1 = Enable local loop-back mode (diagnostics).  
Logic 0 = No TX break condition. (normal default  
condition)  
MCR BIT 5-6:  
Logic 1 = Forces the transmitter output (TX) to a logic  
0 for alerting the remote receiver to a line break  
condition.  
Not Used - initialized to a logic 0.  
MCR BIT-7:  
Logic 0 = Disable power down mode. (normal, default  
condition, 552 only)  
LCR BIT-7:  
The internal baud rate counter latch and Enhance  
Feature mode enable.  
Logic 1 = Enable power down mode (IER bit-5 must  
also be a logic 1 before power down will be activated).  
Logic 0 = Divisor latch disabled. (normal default  
condition)  
Line Status Register (LSR)  
Logic 1 = Divisor latch and enhanced feature register  
enabled.  
This register provides the status of data transfers  
between. the 552/552A and the CPU.  
Modem Control Register (MCR)  
LSR BIT-0:  
This register controls the interface with the modem or  
a peripheral device.  
Logic 0 = No data in receive holding register or FIFO.  
(normal default condition)  
Logic 1 = Data has been received and is saved in the  
receive holding register or FIFO.  
MCR BIT-0:  
Logic 0 = Force -DTR output to a logic 1. (normal  
default condition)  
LSR BIT-1:  
Logic 1 = Force -DTR output to a logic 0.  
Logic 0 = No overrun error. (normal default condition)  
Logic 1 = Overrun error. A data overrun error occurred  
in the receive shift register. This happens when addi-  
tional data arrives while the FIFO is full. In this case  
the previous data in the shift register is overwritten.  
Note that under this condition the data byte in the  
receive shift register is not transferred into the FIFO,  
therefore the data in the FIFO is not corrupted by the  
error.  
MCR BIT-1:  
Logic 0 = Force -RTS output to a logic 1. (normal  
default condition)  
Logic 1 = Force -RTS output to a logic 0.  
MCR BIT-2:  
This bit is used in the Loop-back mode only. In the  
Rev.3.40  
22  
ST16C552/552A  
LSR BIT-2:  
break indication is in the current FIFO data. This bit is  
cleared when RHR register is read.  
Logic 0 = No parity error. (normal default condition)  
Logic 1 = Parity error. The receive character does not  
have correct parity information and is suspect. In the  
FIFO mode, this error is associated with the character  
at the top of the FIFO.  
Modem Status Register (MSR)  
This register provides the current state of the control  
interface signals from the modem, or other peripheral  
device that the 552/552A is connected to. Four bits of  
this register are used to indicate the changed informa-  
tion. These bits are set to a logic 1 whenever a control  
input from the modem changes state. These bits are  
set to a logic 0 whenever the CPU reads this register.  
LSR BIT-3:  
Logic 0 = No framing error. (normal default condition)  
Logic 1 = Framing error. The receive character did not  
have a valid stop bit(s). In the FIFO mode this error is  
associated with the character at the top of the FIFO.  
LSR BIT-4:  
MSR BIT-0:  
Logic 0 = No break condition. (normal default condi-  
tion)  
Logic 1 = The receiver received a break signal (RX  
was a logic 0 for one character frame time). In the  
FIFO mode, only one break character is loaded into  
the FIFO.  
Logic 0 = No -CTS Change (normal default condition)  
Logic1=The-CTSinputtothe552/552Ahaschanged  
state since the last time it was read. A modem Status  
Interrupt will be generated.  
MSR BIT-1:  
Logic 0 = No -DSR Change. (normal default condition)  
Logic 1 = The -DSR input to the 552/552A has  
changed state since the last time it was read. A  
modem Status Interrupt will be generated.  
LSR BIT-5:  
This bit is the Transmit Holding Register Empty indi-  
cator. This bit indicates that the UART is ready to  
accept a new character for transmission. In addition,  
this bit causes the UART to issue an interrupt to CPU  
when the THR interrupt enable is set. The THR bit is  
settoalogic1whenacharacteristransferredfromthe  
transmit holding register into the transmitter shift  
register. The bit is reset to logic 0 concurrently with the  
loading of the transmitter holding register by the CPU.  
In the FIFO mode this bit is set when the transmit FIFO  
is empty; it is cleared when at least 1 byte is written to  
the transmit FIFO.  
MSR BIT-2:  
Logic 0 = No -RI Change. (normal default condition)  
Logic 1 = The -RI input to the 552/552A has changed  
from a logic 0 to a logic 1. A modem Status Interrupt  
will be generated.  
MSR BIT-3:  
Logic 0 = No -CD Change. (normal default condition)  
Logic 1 = Indicates that the -CD input to the has  
changed state since the last time it was read. A  
modem Status Interrupt will be generated.  
LSR BIT-6:  
This bit is the Transmit Empty indicator. This bit is set  
to a logic 1 whenever the transmit holding register and  
the transmit shift register are both empty. It is reset to  
logic 0 whenever either the THR or TSR contains a  
data character. In the FIFO mode this bit is set to one  
whenever the transmit FIFO and transmit shift register  
are both empty.  
MSR BIT-4:  
Normally MSR bit-4 bit is the compliment of the -CTS  
input. However in the loop-back mode, this bit is  
equivalent to the RTS bit in the MCR register.  
MSR BIT-5:  
DSR (active high, logical 1). Normally this bit is the  
compliment of the -DSR input. In the loop-back mode,  
this bit is equivalent to the DTR bit in the MCR register.  
LSR BIT-7:  
Logic 0 = No Error. (normal default condition)  
Logic 1 = At least one parity error, framing error or  
Rev.3.40  
23  
ST16C552/552A  
MSRBIT-6:  
SR BIT 1-0:  
RI (active high, logical 1). Normally this bit is the  
compliment of the -RI input. In the loop-back mode  
this bit is equivalent to MCR bit-2 in the MCR register.  
Not Used - initialized to a logic 1.  
SR BIT-2:  
Logic 0 = an interrupt is pending  
MSR BIT-7:  
WhenINTSELisalogic0, SRbit-2basicallytracksthe  
-ACK input interface pin (returns to a logic 1 when the  
-ACK input returns to a logic 1). However when  
INTSEL is a logic 1, the latched mode is selected, SR  
bit-2 goes to a logic 0 with the -ACK input but does not  
return to a logic 1 until the end of the read cycle, i.e.,  
reading SR will set this bit to a logic 1.  
Logic 1 = no interrupt is pending. (normal inactive  
state)  
CD (active high, logical 1). Normally this bit is the  
compliment of the -CD input. In the loop-back mode  
this bit is equivalent to MCR bit-3 in the MCR register.  
Note: Whenever any MSR bit 0-3: is set to logic “1”, a  
MODEM Status Interrupt will be generated.  
Scratchpad Register (SPR)  
The ST16C552/552A provides a temporary data reg-  
ister to store 8 bits of user information.  
SR BIT-3:  
Logic 0 = -ERROR input is a logic 0.  
Logic 1 = -ERROR input is a logic 1. (normal inactive  
state)  
PRINTER PORT REGISTER DESCRIPTIONS  
SR BIT-4:  
Port Register (PR)  
Logic 0 = SLCT input is a logic 0. (normal inactive  
state)  
Logic 1 = SLCT input is a logic 1.  
PR BIT 0-7:  
Printer Data port (Bi-directional) - These pins are the  
eight bit data bus for transferring information to or  
from an external device (usually a printer). D0 is the  
least significant bit. PD7-PD0 are latched during a  
write cycle (output mode).  
SR BIT-5:  
Logic 0 = PE input is a logic 0. (normal inactive state)  
Logic 1 = PE input is a logic 1.  
I/O Select Register (IOSEL)  
SR BIT-6:  
Logic 0 = -ACK input is a logic 0.  
Logic 1 = -ACK input is a logic 1. (normal inactive  
state)  
This bit is used in conjunction with the state of BIDEN  
to set the direction (input/output) of the PD7-PD0 data  
bus. This register is used only when BIDEN is a logic  
0.  
Logic 55 (Hex) + BIDEN 0 = PD7-PD0 are set for  
output mode  
SR BIT-7:  
Logic 0 = BUSY input is a logic 0  
Logic 1 = BUSY input is a logic 1 (normal inactive  
state)  
Logic AA (Hex) + BIDEN 0 = PD7-PD0 are set for input  
mode  
Command Register (COM)  
Status Register (SR)  
This register provides the printer port input logical  
states and the status of the interrupt -INTP based on  
the condition of the -ACK printer port interface signal.  
The logical state of these pins is dependent on exter-  
nal interface signals.  
This register provides the printer port input logical  
states and the status of the printer interrupt INIT,  
which is based on the state of CON bit-1.  
COM BIT-0:  
-STROBE is a bi-directional signal with an open  
Rev.3.40  
24  
ST16C552/552A  
sourcedriverandinternalpull-upsothatitmaybewire-  
or’dwithotheroutputs.COMbit-1isusedtoreadstatus  
while CON bit 1 is used to set an output state. If it is to  
function as an input, CON bit-1 shall be set to a logic 1  
first.  
Logic 1 = Interrupt (-INTP output) is enabled  
COM BIT 5-7:  
Not Used - initialized to a logic 1.  
Control Register (CON)  
Logic 0 = -STROBE pin is a logic 1. (normal default  
condition)  
Logic 1 = -STROBE pin is a logic 0.  
This register provides control of the printer port output  
logical states and controls the printer interrupts INIT  
and -INTP. With the exception of PD 0-7 IN/OUT, the  
statusofthisregistermaybereadbyreadingtheCOM  
register.  
COM BIT-1:  
-AutoFDXT is a bi-directional signal with an open  
source driver and internal pull-up so that it may be  
wire-or’d with other outputs. COM bit-1 is used to read  
status while CON bit 1 is used to set an output state.  
If it is to function as an input, CON bit-1 shall be set to  
a logic 1 first.  
Logic 0 = -AutoFDXT pin is a logic 1. (normal default  
condition)  
1= -AutoFDXT pin is a logic 0.  
CON BIT-0:  
The -STROBE output control bit is under software  
control, i.e., the hardware will not generate a strobe. It  
is up to software to return the state of -STROBE to the  
inactive (logic 1) state. The hardware driver is open  
drain so that -STROBE may be wire-or’d. The state of  
this bit can be read using COM bit-0.  
COM BIT-2:  
Logic 0 = -STROBE output is set to a logic 1. (normal  
default condition)  
Logic 1 = -STROBE output is set to a logic 0.  
INIT is a bi-directional signal with an open source  
driver and internal pull-up so that it may be wire-or’d  
with other outputs. COM bit-2 is used to read status  
while CON bit 2 is used to set an output state. If it is to  
function as an input, CON bit-1 shall be set to a logic  
1 first.  
CON BIT-1:  
The -AutoFDXT output control bit is set by software  
using CON bit-1. The hardware driver is open drain so  
that -AutoFDXT may be wire-or’d. The state of this bit  
can be read using COM bit-1.  
Logic 0 = INIT pin is a logic 0. (normal default  
condition)  
Logic 1 = INIT pin is a logic 1.  
Logic 0 = -AutoFDXT output is set to a logic 1. (normal  
default condition)  
COM BIT-3:  
Logic 1 = -AutoFDXT output is set to a logic 0.  
-SLCTIN is a bi-directional signal with an open source  
driver and internal pull-up so that it may be wire-or’d  
with other outputs. COM bit-1 is used to read status  
while CON bit 1 is used to set an output state. If it is to  
function as an input, CON bit-1 shall be set to a logic  
1 first.  
CON BIT-2:  
The INIT output control bit is set by software using  
CON bit-2. The hardware driver is open drain so that  
INIT may be wire-or’d. The state of this bit can be read  
using COM bit-2.  
Logic 0 = -SLCTIN pin is a logic 1 (normal default  
condition)  
Logic 0 = INIT output is set to a logic 0. (normal default  
condition)  
Logic 1 = -SLCTIN pin is a logic 0  
Logic 1 = INIT output is set to a logic 1.  
COM BIT-4:  
CON BIT-3:  
Thisbitallowsthestateof-INTPtobereadbackbythe  
external CPU.  
Logic 0 = Interrupt (-INTP output) is disabled (normal  
default condition)  
The-SLCTINoutputcontrolbitissetbysoftwareusing  
CON bit-3. The hardware driver is open drain so that  
-AutoFDXT may be wire-or’d. The state of this bit can  
be read using COM bit-3.  
Rev.3.40  
25  
ST16C552/552A  
Logic 0 = -SLCTIN output is set to a logic 1. (normal  
default condition)  
ST16C552/552A EXTERNAL RESET CONDITION  
Logic 1 = -SLCTIN output is set to a logic 0.  
REGISTERS  
(UART)  
RESET STATE  
CON BIT-4:  
This bit enables or masks the printer interrupt output  
-INTP. The state of this bit can be read using COM bit-  
IER  
BITS 0-7=0  
4.  
ISR  
ISR BIT-0=1, ISR BITS 1-7=0  
LCR BITS 0-7=0  
MCR BITS 0-7=0  
Logic 0 = Disable -INTP output. (normal default con-  
dition)  
Logic 1 = Enable -INTP output.  
LCR  
MCR  
LSR  
LSR BITS 0-4=0,  
LSR BITS 5-6=1 LSR, BIT 7=0  
MSR BITS 0-3=0,  
MSR BITS 4-7=input signals  
FCR BITS 0-7=0  
CON BIT-5:  
MSR  
FCR  
This bit is used in conjunction with the state of BIDEN  
to set the direction (input/output) of the PD7-PD0 data  
bus.  
Logic 0 + BIDEN 1 = PD7-PD0 are set for output mode  
(normal default condition)  
Logic 1 + BIDEN 1 = PD7-PD0 are set for input mode  
REGISTERS  
Printer Port  
RESET STATE  
CON BIT 6-7:  
Not Used - initialized to a logic 1.  
IOSEL  
SR  
IOSEL BITS-0-7=0  
SR BITS 0-1=1, BITS 2-7=input  
signals  
COM  
CON  
COM BITS 0-4=0, BITS 5-7=1  
CON BITS 0-5=0, BITS 6-7=1  
SIGNALS  
RESET STATE  
TX A/B  
High  
-RTS A/B  
-DTR A/B  
INT A/B, P  
-RXRDY A/B  
-TXRDY A/B  
PD0-PD7  
-STROBE  
-AutoFDXT  
INIT  
High  
High  
Three state mode  
High  
Low  
Low, output mode  
High, output mode  
High, output mode  
Low, output mode  
High, output mode  
-SLCTIN  
Rev.3.40  
26  
ST16C552/552A  
AC ELECTRICAL CHARACTERISTICS  
TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.  
Symbol  
Parameter  
Limits  
3.3  
Limits  
5.0  
Units Conditions  
Min  
Max  
Min  
Max  
T1w,T2w Clock pulse duration  
17  
17  
ns  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
T3w  
T6s  
Oscillator/Clock frequency  
Address setup time  
8
24  
5
0
T7d  
T7w  
-IOR delay from chip select  
-IOR strobe width  
10  
35  
0
10  
25  
0
T7h  
T9d  
Chip select hold time from -IOR  
Read cycle delay  
40  
30  
T12d  
T12h  
T13d  
T13w  
T13h  
T15d  
T16s  
T16h  
T17d  
T18d  
Delay from -IOR to data  
Data disable time  
-IOW delay from chip select  
-IOW strobe width  
Chip select hold time from -IOW  
Write cycle delay  
Data setup time  
35  
25  
25  
15  
10  
40  
0
40  
20  
5
10  
25  
0
30  
15  
5
Data hold time  
Delay from -IOW to output  
Delay to set interrupt from MODEM  
input  
50  
40  
40  
35  
ns  
ns  
100 pF load  
100 pF load  
T19d  
T20d  
T21d  
T22d  
T23d  
Delay to reset interrupt from -IOR  
Delay from stop to set interrupt  
Delay from -IOR to reset interrupt  
Delay from stop to interrupt  
Delay from initial INT reset to transmit  
start  
40  
1
45  
45  
24  
35  
1
40  
40  
24  
ns  
Rclk  
ns  
ns  
Rclk  
100 pF load  
100 pF load  
8
8
T24d  
T25d  
T26d  
T27d  
T28d  
T39w  
T40s  
T41h  
T42d  
T43d  
TR  
Delay from -IOW to reset interrupt  
Delay from stop to set -RxRdy  
Delay from -IOR to reset -RxRdy  
Delay from -IOW to set -TxRdy  
Delay from start to reset -TxRdy  
-ACK pulse width  
PD7 - PD0 setup time  
PD7 - PD0 hold time  
Delay from -ACK low to interrupt low  
Delay from -IOR to reset interrupt  
Reset pulse width  
45  
1
45  
45  
8
40  
1
40  
40  
8
ns  
Rclk  
ns  
ns  
Rclk  
ns  
ns  
ns  
ns  
ns  
75  
15  
30  
10  
10  
40  
1
75  
10  
25  
5
5
40  
1
ns  
Rclk  
N
Baud rate devisor  
216-1  
216-1  
Rev.3.40  
27  
ST16C552/552A  
ABSOLUTE MAXIMUM RATINGS  
Supply range  
7 Volts  
GND - 0.3 V to VCC +0.3 V  
-40° C to +85° C  
Voltage at any pin  
Operating temperature  
Storage temperature  
Package dissipation  
-65° C to 150° C  
500 mW  
DC ELECTRICAL CHARACTERISTICS  
TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=2.97 - 5.5V unless otherwise specified.  
Symbol  
Parameter  
Limits  
3.3  
Limits  
5.0  
Units  
Conditions  
Min  
Max  
Min  
Max  
VILCK  
VIHCK  
VIL  
VIH  
VIH  
VOL  
VOL  
VOH  
VOH  
IIL  
Clock input low level  
Clock and printer port input high level  
Inputlowlevel  
Inputhighlevel(Rev"E"andolder)  
Inputhighlevel(Rev"F"andnewer)  
Output low level on all outputs  
Output low level on all outputs  
Output high level  
Output high level  
Input leakage  
Clock leakage  
Avgpowersupplycurrent  
-0.3  
2.4  
-0.3  
2.0  
2.0  
0.6  
VCC  
0.8  
VCC  
5.5  
-0.5  
3.0  
-0.5  
2.2  
2.2  
0.6  
VCC  
0.8  
VCC  
5.5  
V
V
V
V
V
V
V
V
V
µA  
µA  
mA  
pF  
kΩ  
0.4  
IOL= 4 mA  
IOL= 4 mA  
IOH= -4 mA  
IOH= -1 mA  
0.4  
2.4  
2.0  
±10  
±10  
1.5  
5
±10  
±10  
3
5
22  
ICL  
ICC  
CP  
Inputcapacitance  
Internal pull-up resistance  
RIN  
9
Note: See the Symbol Description Table, for a listing of pins having internal pull-up resistors.  
Rev.3.40  
28  
ST16C552/552A  
Va lid  
Add ress  
Va lid  
Add ress  
A0-A 2  
-CS  
T7 h  
T7 h  
T6s  
T6s  
T7w  
A ctive  
A ctive  
T7w  
T9 d  
-IO R  
A ctive  
T12 h  
T12 d  
T12 d  
T12 h  
Va lid  
Da ta  
Va lid Da ta  
D0 -D7  
X 552 -RD-2  
General read timing  
Valid  
A ddr ess  
Valid  
A ddr ess  
A0-A2  
-C S  
T7h  
T7h  
T 6s  
T 6s  
A ctive  
A ctive  
T13w  
T13w  
T15d  
-IOW  
D 0-D7  
A ctive  
T16h  
T 16s  
T 16s  
T16h  
D ata  
D ata  
X552-R D -2  
General write timing  
Rev.3.40  
29  
ST16C552/552A  
T1w  
T2w  
EXTERNAL  
CLOCK  
EX-CK-1  
T3w  
External clock timing  
Active  
-IOW  
T17d  
-RTS  
-DTR  
Change of state  
Change of state  
-CD  
-CTS  
Change of state  
Change of state  
-DSR  
T18d  
T18d  
INT  
Active  
Active  
Active  
Active  
T19d  
Active  
Active  
-IOR  
T18d  
Change of state  
X552-MD-1  
-RI  
Modem input/output timing  
Rev.3.40  
30  
ST16C552/552A  
START  
BIT  
STOP  
BIT  
DATA BITS (5-8)  
RX  
D0  
D1  
D2  
D3  
D4  
D5  
D6 D7  
PARITY  
BIT  
NEXT  
DATA  
START  
BIT  
5 DATA BITS  
6 DATA BITS  
7 DATA BITS  
T20d  
Active  
INT  
T21d  
Active  
-IOR  
16 BAUD RATE CLOCK  
X552-RX-1  
Receive timing  
Rev.3.40  
31  
ST16C552/552A  
START  
BIT  
STOP  
BIT  
DATA BITS (5-8)  
RX  
D0  
D1  
D2  
D3  
D4  
D5  
D6 D7  
PARITY  
BIT  
NEXT  
DATA  
START  
BIT  
T25d  
Active  
Data  
Ready  
-RXRDY  
-IOR  
T26d  
Active  
X552-RX-2  
Receive ready timing in none FIFO mode  
Rev.3.40  
32  
ST16C552/552A  
START  
BIT  
STOP  
BIT  
DATA BITS (5-8)  
RX  
D0  
D1  
D2  
D3  
D4  
D5  
D6 D7  
PARITY  
BIT  
First byte  
that reaches  
the trigger  
level  
T25d  
Active  
Data  
Ready  
-RXRDY  
-IOR  
T26d  
Active  
X552-RX-3  
Receive timing in FIFO mode  
Rev.3.40  
33  
ST16C552/552A  
START  
BIT  
STOP  
BIT  
DATA BITS (5-8)  
TX  
D0  
D1  
D2  
D3  
D4  
D5  
D6 D7  
PARITY  
BIT  
NEXT  
DATA  
START  
BIT  
5 DATA BITS  
6 DATA BITS  
7 DATA BITS  
T22d  
Active  
Tx Ready  
INT  
T24d  
T23d  
-IOW  
Active  
Active  
16 BAUD RATE CLOCK  
X552-TX-1  
Transmit timing  
Rev.3.40  
34  
ST16C552/552A  
START  
BIT  
STOP  
BIT  
DATA BITS (5-8)  
TX  
D0  
D1  
D2  
D3  
D4  
D5  
D6 D7  
PARITY  
BIT  
NEXT  
DATA  
START  
BIT  
-IOW  
Active  
T28d  
D0-D7  
BYTE #1  
T27d  
Active  
Transmitter ready  
-TXRDY  
Transmitter  
not ready  
X552-TX-2  
Transmit ready timing in none FIFO mode  
Rev.3.40  
35  
ST16C552/552A  
START BIT  
DATA BITS (5-8)  
STOP BIT  
TX  
D0  
D1  
D2  
D3  
D4  
D5  
D6 D7  
5 DATA BITS  
PARITY BIT  
6 DATA BITS  
7 DATA BITS  
-IOW  
Active  
T28d  
D0-D7  
BYTE #16  
T27d  
-TXRDY  
FIFO Full  
X552-TX-3  
Transmit ready timing in FIFO mode  
Rev.3.40  
36  
ST16C552/552A  
T39w  
-ACK  
INTP  
T40d  
T42d  
T43d  
-IOR  
T40s  
NORMAL MODE  
INTERRUPT LATCHED MODE SELECT  
INTSEL  
T41h  
VALID DATA  
PD0-PD7  
X552-PR-1  
Printer port timing (552 only)  
Rev.3.40  
37  
ST16C552/552A  
T39w  
-ACK  
T40d  
T42d  
INTP  
T43d  
-IOR  
T40s  
NORMAL MODE  
INTERRUPT LATCHED MODE SELECT  
INTSEL  
T41h  
VALID DATA  
PD0-PD7  
X552-PR-2  
Printer port timing (552A only)  
Rev.3.40  
38  
ST16C552/552A  
EXPLANATIONOFDATASHEETREVISIONS:  
FROM  
3.30  
TO  
CHANGES  
DATE  
3.40  
Added revision history. Added Device Status in Ordering Information.  
Device revisions of "F" and newer have 5V tolerant inputs except for  
XTAL1 and printer port inputs. Device revisions of "E" and older do not  
have 5V tolerant inputs.  
Dec2003  
NOTICE  
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to  
improvedesign,performanceorreliability.EXARCorporationassumesnoresponsibilityfortheuseofanycircuits  
describedherein,conveysnolicenseunderanypatentorotherright,andmakesnorepresentationthatthecircuits  
arefreeofpatentinfringement.Chartsandschedulescontainedhereinareonlyforillustrationpurposesandmay  
vary depending upon a user's specific application. While the information in this publication has been carefully  
checked; no responsibility, however, is assumed for inaccuracies.  
EXARCorporationdoesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailure  
of the product can reasonably be expected to cause failure of the life support system or to significantly affect its  
safetyoreffectiveness.ProductsarenotauthorizedforuseinsuchapplicationsunlessEXARCorporationreceives,  
in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user  
assumesallsuchrisks;(c)potentialliabilityofEXARCorporationisadequatelyprotectedunderthecircumstances.  
Copyright 2003 EXARCorporation  
Datasheet September2003  
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com  
Reproduction, in part or whole, without prior written consent of EXAR Corporation is prohibited.  
Rev.3.40  
39  
配单直通车
ST16C552IJ68-F产品参数
型号:ST16C552IJ68-F
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Obsolete
IHS 制造商:EXAR CORP
零件包装代码:LCC
包装说明:QCCJ, LDCC68,1.0SQ
针数:68
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.31.00.01
风险等级:8.48
其他特性:ALSO OPERATES AT 2.97 V MINIMUM SUPPLY
地址总线宽度:3
边界扫描:NO
最大时钟频率:24 MHz
通信协议:ASYNC, BIT
数据编码/解码方法:NRZ
最大数据传输速率:0.1875 MBps
外部数据总线宽度:8
JESD-30 代码:S-PQCC-J68
JESD-609代码:e3
长度:24.23 mm
低功率模式:YES
串行 I/O 数:2
端子数量:68
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ
封装等效代码:LDCC68,1.0SQ
封装形状:SQUARE
封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260
电源:3.3/5 V
认证状态:Not Qualified
座面最大高度:5.08 mm
子类别:Serial IO/Communication Controllers
最大供电电压:5.5 V
最小供电电压:4.5 V
标称供电电压:5 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)
端子形式:J BEND
端子节距:1.27 mm
端子位置:QUAD
处于峰值回流温度下的最长时间:40
宽度:24.23 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches:1
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