ST16C552/552A
FIFO Operation
P(Programmedwordlength)+12. Toconvertthetime
outvaluetoacharactervalue, theuserhastoconsider
the complete word length, including data information
length, start bit, parity bit, and the size of stop bit, i.e.,
1X, 1.5X, or 2X bit times.
The 16 byte transmit and receive data FIFO’s are
enabledbytheFIFOControlRegister(FCR)bit-0. The
user can set the receive trigger level via FCR bits 6/
7 but not the transmit trigger level. The transmit
interrupt trigger level is set to 16 following a reset. The
receiver FIFO section includes a time-out function to
ensure data is delivered to the external CPU. An
interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the load-
ing of a character or the receive trigger level has not
been reached.
Example -A: If the user programs a word length of 7,
with no parity and one stop bit, the time out will be:
T=4X7(programmedwordlength)+12=40bittimes.
The character time will be equal to 40 / 9 = 4.4
characters, or as shown in the fully worked out ex-
ample: T = [(programmed word length = 7) + (stop bit
= 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) =
4.4 characters.
Hardware/Software and Time-out Interrupts
Example -B: If the user programs the word length = 7,
with parity and one stop bit, the time out will be:
T=4X7(programmedwordlength)+12=40bittimes.
Character time = 40 / 10 [ (programmed word length
= 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4
characters.
TheinterruptsareenabledbyIERbits0-3.Caremustbe
takenwhenhandlingtheseinterrupts.Followingareset
the transmitter interrupt is enabled, the 552/552A will
issue an interrupt to indicate that transmit holding
register is empty. This interrupt must be serviced prior
tocontinuingoperations.TheLSRregisterprovidesthe
current singular highest priority interrupt only. It could
be noted that CTS and RTS interrupts have lowest
interrupt priority. A condition can exist where a higher
priorityinterruptmaymaskthelowerpriorityCTS/RTS
interrupt(s). Only after servicing the higher pending
interruptwillthelowerpriorityCTS/RTSinterrupt(s)be
reflected in the status register. Servicing the interrupt
without investigating further interrupt conditions can
result in data errors.
Programmable Baud Rate Generator
The 552/552A supports high speed modem technolo-
giesthathaveincreasedinputdataratesbyemploying
data compression schemes. For example a 33.6Kbps
modem that employs data compression may require a
115.2Kbpsinputdatarate. A128.0KbpsISDNmodem
that supports data compression may need an input
data rate of 460.8Kbps. The 552/552A can support a
standard data rate of 921.6Kbps.
When two interrupt conditions have the same priority,
it is important to service these interrupts correctly.
Receive Data Ready and Receive Time Out have the
same interrupt priority (when enabled by IER bit-3).
The receiver issues an interrupt after the number of
characters have reached the programmed trigger
level. In this case the 552/552A FIFO may hold more
characters than the programmed trigger level. Follow-
ingtheremovalofadatabyte, theusershouldrecheck
LSR bit-0 for additional characters. A Receive Time
OutwillnotoccurifthereceiveFIFOisempty.Thetime
out counter is reset at the center of each stop bit
receivedoreachtimethereceiveholdingregister(RHR)
isread(seeFigure4,ReceiveTime-outInterrupt).The
actual time out value is T (Time out length in bits) = 4 X
Single baud rate generator is provided for the trans-
mitter and receiver, allowing independent TX/RX
channel control. The programmable Baud Rate Gen-
erator is capable of accepting an input clock up to 24
MHz, as required for supporting a 1.5Mbps data rate.
The 552/552A requires that an external clock source
be connected to the CLK input pin to clock the internal
baudrategeneratorforstandardorcustomrates. (see
Baud Rate Generator Programming below).
Thegeneratordividestheinput16Xclockbyanydivisor
from1to216 -1.The552/552Adividesthebasicexternal
clockby16.Thebasic16Xclockprovidestableratesto
support standard and custom applications using the
Rev.3.40
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