TAS5412-Q1
ZHCSBP3A –AUGUST 2013–REVISED OCTOBER 2013
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scenario. The user may restart the affected channel via I2C. An OCSD event activates the fault pin, with the
I2C fault register recording the affected channels. If the supply or ground short is strong enough to exceed
the peak current threshold but not severe enough to trigger the OCSD, the peak current limiter prevents
excess current from damaging the output FETs, and operation returns to normal after the short is removed.
3. DC Detect—This circuit detects a dc offset continuously during normal operation at the output of the
amplifier. If the dc offset reaches the level defined in the I2C registers for the specified time period, the circuit
triggers. By default, a dc detection event does not shut the output down. One can enable or disable the
shutdown function via I2C. If enabled, the triggered channel shuts down, but the others remain playing, and
the device asserts the FAULT pin. The I2C registers define the dc level.
4. Clip Detect—The clip-detect circuit alerts the user to the presence of a 100% duty-cycle PWM due to a
clipped waveform. When this occurs, the device passes to the CLIP_OTW pin a signal that remains asserted
until the 100% duty-cycle PWM signal is no longer present. Through I2C, one can change the CLIP_OTW
signal to clip-only, OTW-only, or both. A fourth mode, used only during diagnostics, is the option to report
detected tweeter-detection events on these pins (see the Tweeter Detection section). The microcontroller in
the system can monitor the signal at the CLIP_OTW pin. The microcontroller configuration may be such as to
reduce the volume on the channel in an active clipping-prevention circuit.
5. Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD), and Thermal Foldback—The
device asserts the CLIP_OTW pin when the die temperature reaches 125°C. The OTW has three
temperature thresholds with a 10°C hysteresis. Indication of the thresholds is in I2C register 0x04 bits 5, 6,
and 7. The device still functions until the temperature reaches the OTSD threshold, 155°C, at which time it
places the outputs into Hi-Z mode and asserts the FAULT pin. I2C is still active in the event of an OTSD,
which allows reading the registers for faults, but all audio ceases abruptly. The OTSD resets at 145°C, to
allow the turning the TAS5412-Q1 back on through I2C. The OTW indication persists until the temperature
drops below 115°C. All temperatures are nominal values. The thermal foldback decreases the channel gain.
6. Undervoltage (UV) and Power-On Reset (POR)—The undervoltage (UV) protection detects low voltages
on PVDD, AVDD, and CP. In the event of an undervoltage, the device asserts the FAULT pin and updates
the I2C register for the voltage which caused the event. Power-on-reset (POR) occurs when PVDD drops low
enough. A POR event causes the I2C to go into a high-impedance state. After the device recovers from the
POR event, re-initialization of the device via I2C is necessary.
7. Overvoltage (OV) and Load Dump—The OV protection detects high voltages on PVDD. If PVDD reaches
the overvoltage threshold, the device asserts the FAULT pin and updates the I2C register. If the voltage
increases beyond the load dump threshold of 29 Vdc, the device shuts down and must undergo a restart
once the voltage returns to a safe value. After the device recovers from a load-dump event, the device
requires re-initialization via I2C. The TAS5412-Q1 can withstand 50-V load-dump voltage spikes. Load
Diagnostics shows the regions of operating voltage and the profile of the load-dump event.
Power Supply
A car battery that can have a large voltage swing most commonly provides the power for the device. PVDD is a
filtered battery voltage, and is the supply for the output FETS and the low-side FET gate driver. A charge pump
(CP) supply provides power to the high-side FET gate driver. The charge pump supplies the gate-drive voltages.
AVDD, which comes from an internal linear regulator, powers the analog circuitry. This supply requires a 0.1-µF,
10-V external bypass capacitor at the A_BYP pin. TI recommends attaching no external components except the
bypass capacitor to this pin. DVDD, which comes from an internal linear regulator, powers the digital circuitry.
The D_BYP pin requires a 0.1-µF, 10-V external bypass capacitor. TI recommends that no external components
except the bypass capacitor be attached to this pin.
The device can withstand fortuitous open-ground and -power conditions. Fortuitous open-ground usually occurs
when a speaker wire is shorted to ground, allowing for a second ground path through the body diode in the
output FETs. The uniqueness of the diagnostic capabilities allows debugging of the speakers and speaker wires,
eliminating the need to remove the amplifier to diagnose the problem.
I2C Serial Communication Bus
The device communicates with the system processor via the I2C serial communication bus. It is an I2C slave-only
device. The processor can poll the device via I2C to determine the operating status. Reporting of all fault
conditions and detections is via I2C. The setting of numerous features and operating conditions is also via I2C.
The I2C bus allows control of the following configurations:
•
Control the gain each channel independently. The gain settings are 12 dB, 20 dB, 26 dB, and 32 dB.
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