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TEA1751T; TEA1751LT

GreenChip III SMPS control IC

Rev. 02 — 23 December 2009

Product data sheet

1. General description

The GreenChip III is the third generation of green Switched Mode Power Supply (SMPS)

controller ICs. The TEA1751(L)T (TEA1751T and TEA1751LT) combines a controller for

Power Factor Correction (PFC) and a flyback controller. Its high level of integration allows

the design of a cost-effective power supply with a very low number of external

components.

The special built-in green functions provide high efficiency at all power levels. This applies

to quasi-resonant operation at high power levels, quasi-resonant operation with valley

skipping, as well as to reduced frequency operation at lower power levels. At low power

levels, the PFC switches off to maintain high efficiency.

During low power conditions, the flyback controller switches to frequency reduction mode

and limits the peak current to 25 % of its maximum value. This will ensure high efficiency

at low power and good standby power performance while minimizing audible noise from

the transformer.

The TEA1751(L)T is a MultiChip Module, (MCM), containing two chips. The proprietary

high voltage BCD800 process which makes direct start-up possible from the rectified

universal mains voltage in an effective and green way. The second low voltage SIlicon On

Insulator (SIOI) is used for accurate, high speed protection functions and control.

The TEA1751(L)T enables highly efficient and reliable supplies with power requirements

up to 250 W, to be designed easily and with a minimum number of external components.

2. Features

2.1 Distinctive features

Integrated PFC and flyback controller.

Universal mains supply operation (70 V (AC) to 276 V (AC)).

Dual boost PFC with accurate maximum output voltage (NXP patented).

High level of integration, resulting in a very low external component count and a

cost-effective design.

2.2 Green features

On-chip start-up current source.

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

2.3 PFC green features

Valley/zero voltage switching for minimum switching losses (NXP patented).

Frequency limitation to reduce switching losses.

PFC is switched off when a low load is detected at the flyback output.

2.4 Flyback green features

Valley switching for minimum switching losses (NXP patented).

Frequency reduction with fixed minimum peak current at low power operation to

maintain high efficiency at low output power levels.

2.5 Protection features

Safe restart mode for system fault conditions.

Continuous mode protection by means of demagnetization detection for both

converters (NXP patented).

UnderVoltage Protection (UVP) (foldback during overload).

Accurate OverVoltage Protection (OVP) for both converters (adjustable for flyback

converter).

Mains voltage independent OverPower Protection (OPP)

Open control loop protection for both converters. The open loop protection on the

flyback converter is latched on the TEA1751L and safe restart on the TEA1751.

IC overtemperature protection.

Low and adjustable OverCurrent Protection (OCP) trip level for both converters.

General purpose input for latched protection, e.g. to be used for system

OverTemperature Protection (OTP).

3. Applications

The device can be used in all applications that require an efficient and cost-effective

power supply solution up to 250 W. Notebook adapters in particular can benefit from

the high level of integration.

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

SO16

Description

Version

TEA1751T

plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

TEA1751LT

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

2 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

5. Block diagram

PFCDRIVER

12

FBDRIVER

13

PFC DRIVER

PFC GATE

FB DRIVER

FB GATE

80 μA

1.12 V

3.5 V

DRV

5

LATCH

EXT PROT

LOW

VIN

1.25 V

VINSENSE

PFCCOMP

7

6

PROT

BOOST

R

S

R

S

PFC PROT

PROT

ENABLE PFC

MAX

3.7 V

LATCH

RESET

Q

2.5 V

3.5 V

Freq

Red.

ENABLE

FB

LOW

POWER

30 μA

LOW

POWER

1.25 V

PFC

OSC

FB

OSC

TIME

OUT

3

FBCTRL

2.50 V

VOSENSE

9

TON MAX

2.7 V

15 μA

VCC GOOD

VoSTART FB

LOW POWER

EXT PROT

Freq. Red.

SMPS

CONTROL

MIN

STARTFB

START STOP

PFC

OPP

FB

BOOST

OCP

LOW VIN

VoOVP

PFC

PROT

TIMEOUT

EXT PROT

OTP

OvpFB

LATCH RESET

S (TEA1751L only)

BLANK

S

R

DRIVER

VoSTART FB

VoSHORT

LATCHED

PROTECTION

10

FBSENSE

PROT

OCP

TIMEOUT

TON MAX

VoSHORT

S

(TEA1751 only)

SAFE

RESTART

60 μA

ENABLE FB

START FB

PFC DRIVER

ENABLE PFC

BLANK

500 mV

PFCSENSE 11

V

UVLO

R

START

SOFT

PROTECTION

PROT

EXT PROT

60 μA

VCC GOOD

CHARGE

SOFT START

START STOP PFC

CHARGE

CONTROL

V

startup

th(UVLO)

V

OPP

VALLEY

DETECT

TIMER 4 μs

OVP

VALLEY

DETECT

COUNTER

OvpFB

INTERNAL

SUPPLY

PFCAUX

8

OTP

4

FBAUX

PFCGATE

ZCS

CHARGE

V

startup

FB GATE

ZCS

TIMER 50 μs

TEMP

OTP

V

th(UVLO)

80 mV

100 mV

2

16

HV

1

V

GND

CC

014aaa299

Remark:

For the TEA1751L the time-out is latched.

For the TEA1751 the time-out is safe restart.

Fig 1. Block diagram

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

3 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

6. Pinning information

6.1 Pinning

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

HV

CC

GND

FBCTRL

FBAUX

HVS

FBDRIVER

PFCDRIVER

PFCSENSE

FBSENSE

VOSENSE

TEA1751(L)T

LATCH

PFCCOMP

VINSENSE

PFCAUX

014aaa300

Fig 2. Pin configuration: TEA1751(L)T (SOT109-1)

6.2 Pin description

Table 2.

Pin description

Symbol

V_CC

1

Description

supply voltage

ground

GND

2

FBCTRL

FBAUX

3

control input for flyback

4

input from auxiliary winding for demagnetization timing and

overvoltage protection for flyback

LATCH

5

general purpose protection input

PFCCOMP

VINSENSE

PFCAUX

VOSENSE

FBSENSE

PFCSENSE

PFCDRIVER

FBDRIVER

HVS

6

frequency compensation pin for PFC

sense input for mains voltage

7

8

input from auxiliary winding for demagnetization timing for PFC

sense input for PFC output voltage

9

10

11

12

13

14, 15

16

programmable current sense input for flyback

programmable current sense input for PFC

gate driver output for PFC

gate driver output for flyback

high voltage safety spacer, not connected

high voltage start-up and valley sensing of flyback part

HV

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

4 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

7. Functional description

7.1 General control

The TEA1751(L)T contains a controller for a power factor correction circuit as well as a

controller for a flyback circuit. A typical configuration is shown in Figure 3.

12 11

8

9

16 13

10

6

TEA1751(L)T

7

3

4

1

2

014aaa301

Fig 3. Typical configuration

7.1.1 Start-up and UnderVoltage LockOut (UVLO)

Initially the capacitor on the V_CCpin is charged from the high voltage mains via the HV pin.

As long as V_CCis below V_trip, the charge current is low. This protects the IC if the V_CCpin

is shorted to ground. For a short start-up time the charge current above V_tripis increased

until V_CCreaches V_th(UVLO). If V_CCis between V_th(UVLO)and V_startup, the charge current is

low again, ensuring a low duty cycle during fault conditions.

The control logic activates the internal circuitry and switches off the HV charge current

when the voltage on pin V_CCpasses the V_startuplevel. First, the LATCH pin current source

is activated and the soft start capacitors on the PFCSENSE and FBSENSE pins are

charged. When the LATCH pin voltage exceeds the V_en(LATCH)voltage and the soft start

capacitor on the PFCSENSE pin is charged, the PFC circuit is activated. Also the flyback

converter is activated (providing the soft start capacitor on the FBSENSE pin is charged).

The output voltage of the flyback converter is then regulated to its nominal output voltage.

The IC supply is taken over by the auxiliary winding of the flyback converter. See Figure 4.

If during start-up the LATCH pin does not reach the V_en(LATCH)level before V_CCreaches

V

_th(UVLO), the LATCH pin output is deactivated and the charge current is switched on

again.

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

5 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

As soon as the flyback converter is started, the voltage on the FBCTRL pin is monitored. If

the output voltage of the flyback converter does not reach its intended regulation level in a

predefined time, the voltage on the FBCTRL pin reaches the V_to(FBCTRL)level and an error

is assumed. The TEA1751 then initiates a safe restart, while in the TEA1751L the

protection is latched.

When one of the protection functions is activated, both converters stop switching and the

V

_CCvoltage drops to V_th(UVLO). A latched protection recharges the capacitor C_VCCvia the

HV pin, but does not restart the converters. For a safe restart protection, the capacitor is

recharged via the HV pin and the device restarts (see block diagram, Figure 1).

In the event of an overvoltage protection of the PFC circuit, V_VOSENSE> V_ovp(VOSENSE)

,

only the PFC controller stops switching until the VOSENSE pin voltage drops below

V

_OVP(VOSENSE)again. Also, if a mains undervoltage is detected

V_VINSENSE< V_{stop(VINSENSE)}, only the PFC controller stops switching until

V_VINSENSE> V_{start(VINSENSE)}again.

When the voltage on pin V_CCdrops below the undervoltage lockout level, both controllers

stop switching and reenter the safe restart mode. In the safe restart mode the driver

outputs are disabled and the V_CCpin voltage is recharged via the HV pin.

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

6 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

I

HV

V

startup

V

th(UVLO)

trip

V

CC

V

start(VINSENSE)

EN(LATCH)

VINSENSE

V

LATCH

PROTECTION

soft start

PFCSENSE

PFCDRIVER

soft start

FBSENSE

FBDRIVER

FBCTRL

V

to(FBCTRL)

start(fb)

VOSENSE

V

O

charging VCC

capacitor

starting

converters

normal

operation

protection

restart

014aaa156

Fig 4. Start-up sequence, normal operation and restart sequence

7.1.2 Supply management

All internal reference voltages are derived from a temperature compensated and trimmed

on-chip band gap circuit. Internal reference currents are derived from a temperature

compensated and trimmed on-chip current reference circuit.

7.1.3 Latch input

Pin LATCH is a general purpose input pin, which can be used to switch off both

converters. The pin sources a current I_O(LATCH)(80 μA typical). Switching off both

converters is stopped as soon as the voltage on this pin drops below 1.25 V.

At initial start-up the switching is inhibited until the capacitor on the LATCH pin is charged

above 1.35 V (typical). No internal filtering is done on this pin. An internal zener clamp of

2.9 V (typical) protects this pin from excessive voltages.

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

7 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

7.1.4 Fast latch reset

In a typical application the mains can be interrupted briefly to reset the latched protection.

The PFC bus capacitor, C_bus, does not have to discharge for this latched protection to

reset.

Typically the PFC bus capacitor, C_bus, has to discharge for the V_CCto drop to this reset

level. When the latched protection is set, the clamping circuit of the VINSENSE circuit is

disabled. (see also Section 7.2.9) As soon as the VINSENSE voltage drops below

750 mV (typical) and after that is raised to 870 mV (typical), the latched protection is reset.

The latched protection is also reset by removing both the voltage on pin V_CCand on

pin HV.

7.1.5 Overtemperature protection

An accurate internal temperature protection is provided in the circuit. When the junction

temperature exceeds the thermal shutdown temperature, the IC stops switching. As long

as OTP is active, the capacitor C_VCCis not recharged from the HV mains. The OTP circuit

is supplied from the HV pin if the V_CCsupply voltage is not sufficient.

OTP is a latched protection. It can be reset by removing both the voltage on pin V_CCand

on pin HV or by the fast latch reset function. (See Section 7.1.4)

7.2 Power factor correction circuit

The power factor correction circuit operates in quasi-resonant or discontinuous

conduction mode with valley switching. The next primary stroke is only started when the

previous secondary stroke has ended and the voltage across the PFC MOSFET has

reached a minimum value. The voltage on the PFCAUX pin is used to detect transformer

demagnetization and the minimum voltage across the external PFC MOSFET switch.

7.2.1 t_oncontrol

The power factor correction circuit is operated in t_oncontrol. The resulting mains harmonic

reduction of a typical application is well within the class-D requirements.

7.2.2 Valley switching and demagnetization (PFCAUX pin)

The PFC MOSFET is switched on after the transformer is demagnetized. Internal circuitry

connected to the PFCAUX pin detects the end of the secondary stroke. It also detects the

voltage across the PFC MOSFET. The next stroke is started when the voltage across the

PFC MOSFET is at its minimum in order to reduce switching losses and ElectroMagnetic

Interference (EMI) (valley switching).

If no demagnetization signal is detected on the PFCAUX pin, the controller generates a

zero current signal (ZCS), 50 μs (typical) after the last PFCGATE signal.

If no valley signal is detected on the PFCAUX pin, the controller generates a valley signal

4 μs (typical) after demagnetization was detected.

To protect the internal circuitry during lightning events, for example, it is advisable to add a

5 kΩ series resistor to this pin. To prevent incorrect switching due to external disturbance,

the resistor should be placed close to the IC on the printed-circuit board.

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

8 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

7.2.3 Frequency limitation

To optimize the transformer and minimize switching losses, the switching frequency is

limited to f_sw(PFC)max. If the frequency for quasi-resonant operation is above the f_sw(PFC)max

limit, the system switches over to discontinuous conduction mode. Also here, the PFC

MOSFET is only switched on at a minimum voltage across the switch (valley switching).

7.2.4 Mains voltage compensation (VINSENSE pin)

The mathematical equation for the transfer function of a power factor corrector contains

the square of the mains input voltage. In a typical application this results in a low

bandwidth for low mains input voltages, while at high mains input voltages the Mains

Harmonic Reduction (MHR) requirements may be hard to meet.

To compensate for the mains input voltage influence, the TEA1751(L)T contains a

correction circuit. Via the VINSENSE pin the average input voltage is measured and the

information is fed to an internal compensation circuit. With this compensation it is possible

to keep the regulation loop bandwidth constant over the full mains input range, yielding a

fast transient response on load steps, while still complying with class-D MHR

requirements.

In a typical application, the bandwidth of the regulation loop is set by a resistor and two

capacitors on the PFCCOMP pin.

7.2.5 Soft start-up (pin PFCSENSE)

To prevent audible transformer noise at start-up or during hiccup, the transformer peak

current, I_DM, is increased slowly by the soft start function. This can be achieved by

inserting R_SS1and C_SS1between pin PFCSENSE and current sense resistor R_SENSE1

An internal current source charges the capacitor to V_PFCSENSE= I_{start(soft)PFC}× R_SS1. The

voltage is limited to V_{start(soft)PFC}

.

The start level and the time constant of the increasing primary current level can be

adjusted externally by changing the values of R_SS1and C_SS1

.

τsoftstart = 3 × R

× C

SS1

The charging current I_{start(soft)PFC}flows as long as the voltage on pin PFCSENSE is

below 0.5 V (typ). If the voltage on pin PFCSENSE exceeds 0.5 V, the soft start current

source starts limiting current I_{start(soft)PFC}. As soon as the PFC starts switching, the

I_{start(soft)PFC}current source is switched off; see Figure 5.

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

9 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

I

≤ 60 μA

S1

startup(soft)PFC

SOFT START

CONTROL

R

C

SS1

11

OCP

PFCSENSE

0.5 V

R

SENSE1

014aaa157

Fig 5. Soft start-up of PFC

7.2.6 Low power mode

When the output power of the flyback converter (see Section 7.3) is low, the flyback

converter switches over to frequency reduction mode. When frequency reduction mode is

entered by the flyback controller, the power factor correction circuit is switched off to

maintain high efficiency.

During low power mode operation the PFCCOMP pin is clamped to a minimal voltage of

2.7 V (typical) and a maximum voltage of 3.9 V (typical). The lower clamp voltage limits

the maximum power that is delivered when the PFC is switched on again. The upper

clamp voltage ensures that the PFC can return to its normal regulation point in a limited

amount of time when returning from low power mode.

As soon as the flyback converter leaves the frequency reduction mode, the power factor

correction circuit restores normal operation. To prevent continuous switching on and off of

the PFC circuit, a small hysteresis is build in, (60 mV (typical) on the FBCTRL pin).

7.2.7 Dual boost PFC

The PFC output voltage is modulated by the mains input voltage. The mains input voltage

is measured via the VINSENSE pin. The current is sourced from the VOSENSE pin if the

voltage on the VINSENSE pin drops below 2.2 V (typical). To ensure the stability of the

switch-over 200 mV is inserted around the 2.2 V, see Figure 6.

For low VINSENSE input voltages, the output current is 15 μA (typical). This output

current, in combination with the resistors on the VOSENSE pin, sets the lower PFC output

voltage level at low mains voltages. At high mains input voltages the current is switched to

zero. The PFC output voltage will then be at its maximum. As this current is zero in this

situation, it does not effect the accuracy of the PFC output voltage.

For proper switch-off behavior, the VOSENSE current is switched to its maximum value,

(15 μA (typical)), as soon as the voltage on pin VOSENSE drops below 2.1 V (typical).

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

10 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

2.2 V

V

VINSENSE

−15 μA

I

I(VOSENSE)

014aaa097

Fig 6. Voltage to current transfer function for dual boost PFC

7.2.8 Overcurrent protection (PFCSENSE pin)

The maximum peak current is limited cycle-by-cycle by sensing the voltage across an

external sense resistor, R_SENSE1, on the source of the external MOSFET. The voltage is

measured via the PFCSENSE pin.

7.2.9 Mains undervoltage lockout / brownout protection (VINSENSE pin)

To prevent the PFC from operating at very low mains input voltages, the voltage on the

VINSENSE pin is sensed continuously. As soon as the voltage on this pin drops below the

V

_{stop(VINSENSE)}level, switching of the PFC is stopped.

The voltage on pin VINSENSE is clamped to a minimum value,

V_{start(VINSENSE)}+ ΔV_pu(VINSENSE), for a fast restart as soon as the mains input voltage is

restored after a mains dropout.

7.2.10 Overvoltage protection (VOSENSE pin)

To prevent output overvoltage during load steps and mains transients, an overvoltage

protection circuit is built in.

As soon as the voltage on the VOSENSE pin exceeds the V_ovp(VOSENSE)level, switching

of the power factor correction circuit is inhibited. Switching of the PFC recommences as

soon as the VOSENSE pin voltage drops below the V_ovp(VOSENSE)level again.

When the resistor between pin VOSENSE and ground is open, the overvoltage protection

is also triggered.

7.2.11 PFC open loop protection (VOSENSE pin)

The power factor correction circuit does not start switching until the voltage on the

VOSENSE pin is above the V_{th(ol)(VOSENSE)}level. This protects the circuit from open loop

and VOSENSE short situations.

7.2.12 Driver (pin PFCDRIVER)

The driver circuit to the gate of the power MOSFET has a current sourcing capability of

typically −500 mA and a current sink capability of typically 1.2 A. This permits fast turn-on

and turn-off of the power MOSFET for efficient operation.

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

11 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

7.3 Flyback controller

The TEA1751(L)T includes a controller for a flyback converter. The flyback converter

operates in quasi-resonant or discontinuous conduction mode with valley switching. The

auxiliary winding of the flyback transformer provides demagnetization detection and

powers the IC after start-up.

7.3.1 Multimode operation

The TEA1751(L)T flyback controller can operate in several modes; see Figure 7.

PFC off

PFC on

f

sw(fb)max

frequency

reduction

switching frequency

discontinuous

with valley

switching

quasi resonant

output power

014aaa158

Fig 7. Multimode operation flyback

At high output power the converter switches to quasi-resonant mode. The next converter

stroke is started after demagnetization of the transformer current. In quasi-resonant mode

switching losses are minimized as the converter only switches on when the voltage across

the external MOSFET is at its minimum (valley switching, see also Section 7.3.2).

To prevent high frequency operation at lower loads, the quasi-resonant operation changes

to discontinuous mode operation with valley skipping in which the switching frequency is

limited for EMI to f_sw(fb)max(125 kHz typical). Again, the external MOSFET is only switched

on when the voltage across the MOSFET is at its minimum.

At very low power and standby levels the frequency is controlled down by a Voltage

Controlled Oscillator (VCO). The minimum frequency can be reduced to zero. During

frequency reduction mode, the primary peak current is kept at a minimal level of Ipkmax/4

to maintain a high efficiency. (Ipkmax is the maximum primary peak current set by the

sense resistor and the maximum sense voltage.) As the primary peak current is low in

frequency reduction operation (Ipk = Ipkmax/4), no audible noise is noticeable at

switching frequencies in the audible range. Valley switching is also active in this mode.

In frequency reduction mode the PFC controller is switched off and the flyback maximum

frequency changes linearly with the control voltage on the FBCTRL pin (see Figure 8 ).

For stable on and off switching of the PFC, the FBCTRL pin has a 50 mV (typical)

hysteresis. At no load operation the switching frequency can be reduced to (almost) zero.

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

12 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

PFC off

PFC on

f

sw(fb)max

frequency

reduction

switching frequency

discontinuous

with valley

switching

quasi resonant

1.5 V

V

FBCTRL

014aaa159

Fig 8. Frequency control of flyback part

7.3.2 Valley switching (HV pin)

Refer to Figure 9. A new cycle starts when the external MOSFET is activated. After the

on-time (determined by the FBSENSE voltage and the FBCTRL voltage), the MOSFET is

switched off and the secondary stroke starts. After the secondary stroke, the drain voltage

1

---------------------------------------------------

shows an oscillation with a frequency of approximately

where L_pis

(2 × π × (L × C ))

p

d

the primary self-inductance of the flyback transformer and C_dis the capacitance on the

drain node.

As soon as the internal oscillator voltage is high again and the secondary stroke has

ended, the circuit waits for the lowest drain voltage before starting a new primary stroke.

Figure 9 shows the drain voltage, valley signal, secondary stroke signal and the internal

oscillator signal.

Valley switching allows high frequency operation as capacitive switching losses are

reduced, see Equation 1. High frequency operation makes small and cost-effective

magnetics possible.

1

2

⎛

⎝

⎞

--

P = × C × V × f

(1)

d

⎠

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

13 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

primary

stroke

secondary

stroke

secondary

ringing

drain

valley

secondary

stroke

(2)

(1)

oscillator

014aaa027

(1) Start of new cycle at lowest drain voltage.

(2) Start of new cycle in a classical Pulse Width Modulation (PWM) system without valley detection.

Fig 9. Signals for valley switching

7.3.3 Current mode control (FBSENSE pin)

Current mode control is used for the flyback converter for its good line regulation.

The primary current is sensed by the FBSENSE pin across an external resistor and

compared with an internal control voltage.The internal control voltage is proportional to

the FBCTRL pin voltage, see Figure 10.

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

14 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

V

sense(fb)max

(V)

PFC off

PFC on

0.52 V

flyback

frequency

reduction

flyback

discontinuous

or QR

FBSENSE peak voltage

flyback

cycle skip

mode

0.13 V

1.4 V 1.5 V 2.0 V V

(V)

FBCTRL

014aaa160

Fig 10. Peak current control of flyback part

The driver output is latched in the logic, preventing multiple switch-on.

7.3.4 Demagnetization (FBAUX pin)

The system is always in quasi-resonant or discontinuous conduction mode. The internal

oscillator does not start a new primary stroke until the previous secondary stroke has

ended.

Demagnetization features a cycle-by-cycle output short circuit protection by immediately

lowering the frequency (longer off-time), thereby reducing the power level.

Demagnetization recognition is suppressed during the first t_{sup(xfmr_ring)}time (2 μs typical).

This suppression may be necessary at low output voltages and at start-up and in

applications where the transformer has a large leakage inductance.

If pin FBAUX is open circuit or not connected, a fault condition is assumed and the

converter stops operating immediately. Operation restarts as soon as the fault condition is

removed.

7.3.5 Flyback control / time-out (FBCTRL pin)

The pin FBCTRL is connected to an internal voltage source of 3.5 V via an internal

resistor (typical resistance is 3 kΩ). As soon as the voltage on this pin is above

2.5 V (typical), this connection is disabled. Above 2.5 V the pin is biased with a small

current. When the voltage on this pin rises above 4.5 V (typical), a fault is assumed and

switching is inhibited. In the TEA1751 a restart will then be made, while in the TEA1751L

the protection will be latched.

When a small capacitor is connected to this pin, a time-out function can be created to

protect against an open control loop situation. (see Figure 11 and Figure 12) The time-out

function can be disabled by connecting a resistor (100 kΩ) to ground on the FBCTRL pin.

If the pin is shorted to ground, switching of the flyback controller is inhibited.

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

15 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

In normal operating conditions, when the converter is regulating the output voltage, the

voltage on the FBCTRL pin is between 1.4 V and 2.0 V (typical values) from minimum to

maximum output power.

2.5 V

3.5 V

30 μA

4.5 V

3 kΩ

FBCTRL

TIME-OUT

014aaa049

Fig 11. Time-out protection circuit

4.5 V

2.5 V

V

FBCTRL

output

voltage

intended output

voltage not

reached within

time-out time.

restart

intended output voltage

reached within time-out

time.

014aaa050

Fig 12. Time-out protection (signals), safe restart in the TEA1751

4.5 V

2.5 V

V

FBCTRL

output

voltage

intended output

voltage not

latched

reached within

time−out time.

014aaa298

Fig 13. Time-out protection (signals), latched in the TEA1751L

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

16 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

7.3.6 Soft start-up (pin FBSENSE)

To prevent audible transformer noise during start-up, the transformer peak current, I_DMis

slowly increased by the soft start function. This can be achieved by inserting a resistor and

a capacitor between pin 10, FBSENSE, and the current sense resistor.

An internal current source charges the capacitor to V = I_{start(soft)fb}× R_SS2, with a maximum

of approximately 0.5 V.

The start level and the time constant of the increasing primary current level can be

adjusted externally by changing the values of R_SS2and C_SS2

.

τsoftstart = 3 × R × C

SS2

The soft start current I_{start(soft)fb}is switched on as soon as V_CCreaches V_startup. When the

voltage on pin FBSENSE has reached 0.5 V, the flyback converter starts switching.

The charging current I_{start(soft)(PFC)}flows as long as the voltage on pin FBSENSE is below

approximately 0.5 V. If the voltage on pin FBSENSE exceeds 0.5 V, the soft start current

source starts limiting the current. After the flyback converter has started, the soft start

current source is switched off.

S2

I

start(soft)fb ≤ 60 μA

SOFT START

CONTROL

R

C

SS2

10

OCP

FBSENSE

+

0.5 V

R

SENSE2

014aaa020

Fig 14. Soft start-up of flyback.

7.3.7 Maximum on-time

The flyback controller limits the ‘on-time’ of the external MOSFET to 40 μs (typical). When

the ‘on-time’ is longer than 40 μs, the IC stops switching and enters the safe restart mode.

7.3.8 Overvoltage protection (FBAUX pin)

An output overvoltage protection is implemented in the GreenChip III series. This works

for the TEA1751(L)T by sensing the auxiliary voltage via the current flowing into

pin FBAUX during the secondary stroke. The auxiliary winding voltage is a well-defined

replica of the output voltage. Voltage spikes are averaged by an internal filter.

If the output voltage exceeds the OVP trip level, an internal counter starts counting

subsequent OVP events. The counter has been added to prevent incorrect OVP detection

which might occur during ESD or lightning events. If the output voltage exceeds the OVP

trip level a few times and not again in a subsequent cycle, the internal counter counts

down at twice the speed it uses when counting up. However, when typically eight cycles of

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

17 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

subsequent OVP events are detected, the IC assumes a true OVP and the OVP circuit

switches the power MOSFET off. As the protection is latched, the converter only restarts

after the internal latch is reset. In a typical application the mains should be interrupted to

reset the internal latch.

The output voltage V_o(OVP)at which the OVP function trips, can be set by the

demagnetization resistor, R_FBAUX

:

N

s

-----------

V

=

(I

× R

+ V

)

clamp(FBAUX)

o(OVP)

ovp(FBaux)

FBaux

N

aux

where N_sis the number of secondary turns and N_auxis the number of auxiliary turns of the

transformer. Current I_ovp(FBAUX)is internally trimmed.

The value of R_FBAUXcan be adjusted to the turns ratio of the transformer, thus making an

accurate OVP detection possible.

7.3.9 Overcurrent protection (FBSENSE pin)

The primary peak current in the transformer is measured accurately cycle-by-cycle using

the external sense resistor R_sense2. The OCP circuit limits the voltage on pin FBSENSE to

an internal level (see also Section 7.3.3). The OCP detection is suppressed during the

leading edge blanking period, t_leb, to prevent false triggering caused by switch-on spikes.

LEB (t

)

leb

OCP LEVEL

V

FBSENSE

t

014aaa022

Fig 15. OCP leading edge blanking

7.3.10 Overpower protection

During the primary stroke of the flyback converter the input voltage of the flyback

converter is measured by sensing the current that is drawn from the pin FBAUX.

The current information is used to adjust the peak drain current of the flyback converter,

which is measured via pin FBSENSE. The internal compensation is such that an almost

input voltage independent maximum output power can be realized.

The OPP curve is given in Figure 16.

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

18 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

014aaa096

0.6

V

FBSENSE

(V)

0.52

0.5

0.4

0.37

0.3

−400

−300

−200

−100

0

(μA)

−360

I

FBAUX

Fig 16. Overpower protection curve

7.3.11 Driver (pin FBDRIVER)

The driver circuit to the gate of the external power MOSFET has a current sourcing

capability of typically −500 mA and a current sink capability of typically 1.2 A. This permits

fast turn-on and turn-off of the power MOSFET for efficient operation.

8. Limiting values

Table 3.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Voltages

V_CC

Parameter

Conditions

Min

Max

Unit

supply voltage

−0.4

−25

+38

+5

V

V_LATCH

V_FBCTRL

voltage on pin LATCH

voltage on pin FBCTRL

current limited

+5

V_PFCCOMPvoltage on pin PFCCOMP

V_VINSENSEvoltage on pin VINSENSE

V_VOSENSEvoltage on pin VOSENSE

+5

V_PFCAUX

voltage on pin PFCAUX

+25

+5

V_FBSENSEvoltage on pin FBSENSE

V_PFCSENSEvoltage on pin PFCSENSE

current limited

−0.4

+5

V_HV

voltage on pin HV

+650

Currents

I_FBCTRL

I_FBAUX

current on pin FBCTRL

current on pin FBAUX

−3

0

mA

A

−1

+1

+10

+2

I_PFCSENSEcurrent on pin PFCSENSE

I_FBSENSEcurrent on pin FBSENSE

I_FBDRIVERcurrent on pin FBDRIVER

−1

duty cycle < 10 %

−0.8

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

19 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

Table 3.

Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

−0.8

-

Max

+2

5

Unit

A

I_PFCDRIVERcurrent on pin PFCDRIVER duty cycle < 10 %

I_HV

current on pin HV

mA

General

P_tot

total power dissipation

storage temperature

junction temperature

T_amb< 75 °C

-

0.6

W

T_stg

−55

−40

+150

°C

T_j

ESD

V_ESD

electrostatic discharge

voltage

class 1

human body

model

[1]

[2]

pins 1 to 13

pin 16 (HV)

-

2000

1500

200

V

machine model

charged device

model

500

[1] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

[2] Equivalent to discharging a 200 pF capacitor through a 0.75 μH coil and a 10 Ω resistor.

9. Thermal characteristics

Table 4.

Thermal characteristics

Parameter

thermal resistance from in free air; JEDEC test

junction to ambient board

Symbol

Conditions

Typ

Unit

R_th(j-a)

124

K/W

10. Characteristics

Table 5.

Characteristics

T_amb= 25 °C; V_CC= 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into

the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Start-up current source (pin HV)

I_HV

current on pin HV

V_HV> 80 V

V_CC< V_trip

;

-

1.0

-

mA

V_th(UVLO)< V_CC< V_startup

V_trip< V_CC< V_th(UVLO)

with auxiliary supply

-

5.4

20

-

mA

μA

V

8

40

-

V_BR

breakdown voltage

650

Supply voltage management (pin V_CC

)

V_trip

trip voltage

0.55

21

0.65

22

0.75

23

V

V_startup

start-up voltage

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

20 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

Table 5.

Characteristics …continued

T_amb= 25 °C; V_CC= 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into

the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_th(UVLO)

undervoltage lockout threshold

voltage

14

15

16

V

V_start(hys)

V_hys

hysteresis of start voltage

hysteresis voltage

during start-up phase

-

300

7

-

mV

V

V_startup− V_th(UVLO)

6.3

−1.2

7.7

−0.8

I_ch(low)

low charging current

V_HV> 80 V; V_CC< V_tripor

V_th(UVLO)< V_CC< V_startup

−1.0

mA

I_ch(high)

high charging current

V_HV> 80 V; V_trip< V_CC< V_th(UVLO)

−4.6

−5.4

−6.3

mA

I_CC(oper)

operating supply current

no load on pin FBDRIVER and

PFCDRIVER

2.25

3

3.75

Input voltage sensing PFC (pin VINSENSE)

V_{stop(VINSENSE)}

V_{start(VINSENSE)}

ΔV_pu(VINSENSE)

stop voltage on pin VINSENSE

start voltage on pin VINSENSE

0.86

1.11

-

0.89

1.15

−100

0.92

1.19

-

V

pull-up voltage difference on

pin VINSENSE

active after V_{stop(VINSENSE)}is

detected

mV

I_pu(VINSENSE)

pull-up current on pin

VINSENSE

active after V_{stop(VINSENSE)}is

detected

−55

−47

−40

μA

V_{mvc(VINSENSE)max}maximum mains voltage

compensation voltage on pin

VINSENSE

4.0

-

V

V_flr

fast latch reset voltage

active after V_th(UVLO)is detected

-

0.75

0.12

-

V

V_flr(hys)

hysteresis of fast latch reset

voltage

I_I(VINSENSE)

V_bst(dual)

input current on pin VINSENSE V_VINSENSE> V_{stop(VINSENSE)}after

5

33

100

nA

V_{start(VINSENSE)}is detected

dual boost voltage

current switch-over point

switch-over region

-

2.2

-

V

200

mV

Loop compensation PFC (pin PFCCOMP)

g_m

transconductance

V_VOSENSEto I_O(PFCCOMP)

V_VOSENSE= 3.3 V

60

80

100

45

μA/V

μA

V

I_O(PFCCOMP)

output current on pin

PFCCOMP

33

39

V_VOSENSE= 2.0 V

−45

2.5

−39

2.7

−33

2.9

[1]

V_{clamp(PFCCOMP)}

clamp voltage on pin

PFCCOMP

Low power mode; PFC off; lower

clamp voltage

Upper clamp voltage

-

3.9

3.5

-

V

V_{ton(PFCCOMP)zero}zero on-time voltage on pin

PFCCOMP

3.4

3.6

V_{ton(PFCCOMP)max}maximum on-time voltage on

pin PFCCOMP

1.20

1.25

1.30

V

Pulse width modulator PFC

t_on(PFC)

PFC on-time

V_VINSENSE= 3.3 V;

V_PFCCOMP= V_{ton(PFCCOMP)max}

3.6

30

4.5

40

5.0

53

μs

V_VINSENSE= 0.9 V;

V_PFCCOMP= V_{ton(PFCCOMP)max}

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

21 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

Table 5.

Characteristics …continued

T_amb= 25 °C; V_CC= 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into

the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Output voltage sensing PFC (pin VOSENSE)

V_{th(ol)(VOSENSE)}

V_reg(VOSENSE)

V_ovp(VOSENSE)

I_bst(dual)

open-loop threshold voltage on

pin VOSENSE

-

1.15

-

V

regulation voltage on pin

VOSENSE

for I_O(PFCCOMP)= 0

2.475 2.500 2.525

V

overvoltage protection voltage

on pin VOSENSE

2.60

2.63

-15

2.67

V

dual boost current

V_VINSENSE< V_bst(dual)or

V_VOSENSE< 2.1 V

-

μA

nA

V_VINSENSE> V_bst(dual)

-30

Overcurrent protection PFC (pin PFCSENSE)

V_{sense(PFC)max}

maximum PFC sense voltage ΔV/Δt = 50 mV/μs

ΔV/Δt = 200 mV/μs

0.49

0.52

250

0.52

0.55

310

0.55

0.57

370

V

t_leb(PFC)

PFC leading edge blanking

time

ns

I_{prot(PFCSENSE)}

protection current on pin

PFCSENSE

−50

-

−5

nA

Soft start PFC (pin PFCSENSE)

I_{start(soft)PFC}

PFC soft start current

−75

0.46

12

−60

0.50

-

−45

0.54

-

μA

V

V_{start(soft)PFC}

R_{start(soft)PFC}

Oscillator PFC

f_sw(PFC)max

PFC soft start voltage

enabling voltage

PFC soft start resistance

kΩ

maximum PFC switching

frequency

100

1.1

125

1.4

150

1.7

kHz

t_off(PFC)min

minimum PFC off-time

μs

Valley switching PFC (pin PFCAUX)

(ΔV/Δt)_vrec(PFC)

PFC valley recognition voltage

change with time

-

1.7

V/μs

[2]

[3]

t_vrec(PFC)

PFC valley recognition time

V_PFCAUX= 1 V peak-to-peak

demagnetization to ΔV/Δt = 0

-

300

50

6

ns

μs

-

t_to(vrec)PFC

PFC valley recognition time-out

time

3

4

Demagnetization management PFC (pin PFCAUX)

V_{th(comp)PFCAUX}

t_to(demag)PFC

I_prot(PFCAUX)

comparator threshold voltage

on pin PFCAUX

−150 −100 −50

mV

μs

PFC demagnetization time-out

time

40

50

-

60

protection current on pin

PFCAUX

V_PFCAUX= 50 mV

−75

−5

nA

Driver (pin PFCDRIVER)

I_{src(PFCDRIVER)}

source current on pin

PFCDRIVER

V_PFCDRIVER= 2 V

-

−0.5

-

A

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

22 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

Table 5.

Characteristics …continued

T_amb= 25 °C; V_CC= 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into

the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

0.7

1.2

11

Max

Unit

A

I_{sink(PFCDRIVER)}

sink current on pin

PFCDRIVER

V_PFCDRIVER= 2 V

V_PFCDRIVER= 10 V

-

A

V_{O(PFCDRIVER)max}maximum output voltage on pin

PFCDRIVER

12

V

Overvoltage protection flyback (pin FBAUX)

I_ovp(FBAUX)

overvoltage protection current

on pin FBAUX

279

6

300

8

321

12

μA

N_cy(ovp)

number of overvoltage

protection cycles

Demagnetization management flyback (pin FBAUX)

V_{th(comp)FBAUX}

comparator threshold voltage

on pin FBAUX

60

80

-

110

mV

nA

I_prot(FBAUX)

protection current on pin

FBAUX

V_FBAUX= 50 mV

−50

−5

V_clamp(FBAUX)

clamp voltage on pin FBAUX

I_FBAUX= −500 μA

I_FBAUX= 500 μA

−1.0

0.5

−0.8

0.7

2

−0.6

0.9

V

t_{sup(xfmr_ring)}

transformer ringing

suppression time

1.5

2.5

μs

Pulse width modulator flyback

t_on(fb)min

minimum flyback on-time

-

t_leb

40

-

ns

t_on(fb)max

maximum flyback on-time

32

48

μs

Oscillator flyback

f_sw(fb)max

maximum flyback switching

frequency

100

125

1.5

60

150

kHz

V

V_{start(VCO)FBCTRL}

V_hys(FBCTRL)

VCO start voltage on pin

FBCTRL

1.3

1.7

[4]

hysteresis voltage on pin

FBCTRL

-

mV

V

ΔV_VCO(FBCTRL)

VCO voltage difference on pin

FBCTRL

-0.1

Peak current control flyback (pin FBCTRL)

V_FBCTRL

voltage on pin FBCTRL

for maximum flyback peak current

enable voltage

1.85

2.0

2.5

4.5

3

2.15

V

V_to(FBCTRL)

time-out voltage on pin

FBCTRL

-

V

trip voltage

4.2

-

4.8

-

V

R_int(FBCTRL)

I_O(FBCTRL)

internal resistance on pin

FBCTRL

kΩ

output current on pin FBCTRL V_FBCTRL= 0 V

V_FBCTRL= 2 V

−1.4

−0.6

−36

−1.19 −0.93 mA

−0.5

−30

−0.4

−24

mA

I_to(FBCTRL)

time-out current on pin

FBCTRL

V_FBCTRL= 2.6 V

V_FBCTRL= 4.1 V

μA

−34.5 −28.5 −22.5 μA

Valley switching flyback (pin HV)

(ΔV/Δt)_vrec(fb)

flyback valley recognition

voltage change with time

−75

-

+75

V/μs

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

23 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

Table 5.

Characteristics …continued

T_amb= 25 °C; V_CC= 20 V; all voltages are measured with respect to ground (pin 2); currents are positive when flowing into

the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

[5]

t_d(vrec-swon)

valley recognition to switch-on

delay time

-

150

-

ns

Soft start flyback (pin FBSENSE)

I_{start(soft)fb}

V_{start(soft)fb}

R_{start(soft)fb}

flyback soft start current

−75

0.43

12

−60

0.49

-

−45

0.54

-

μA

V

flyback soft start voltage

enable voltage

flyback soft start resistance

kΩ

Overcurrent protection flyback (pin FBSENSE)

V_sense(fb)max

maximum flyback sense

voltage

ΔV/Δt = 50 mV/μs

ΔV/Δt = 200 mV/μs

0.49

0.52

255

0.52

0.55

305

0.55

0.58

355

V

t_leb(fb)

flyback leading edge blanking

time

ns

I_{start(OPP)FBAUX}

I_{opp(red)(FBAUX)}

OPP start current on pin

FBAUX

-

−100

−360

-

μA

reduced overpower protection V_sense(fb)maxhas reduced to

current on pin FBAUX

Driver (pin FBDRIVER)

I_{src(FBDRIVER)}source current on pin

FBDRIVER

0.37 V

V_FBDRIVER= 2 V

-

−0.5

-

A

I_{sink(FBDRIVER)}

sink current on pin FBDRIVER V_FBDRIVER= 2 V

V_FBDRIVER= 10 V

-

0.7

1.2

11

-

A

V

-

V_{O(FBDRIVER)(max)}maximum output voltage on pin

FBDRIVER

12

LATCH input (pin LATCH)

V_prot(LATCH)

protection voltage on pin

LATCH

1.23

1.25

1.27

V

I_O(LATCH)

output current on pin LATCH

enable voltage on pin LATCH

V_prot(LATCH)< V_LATCH< V_oc(LATCH)

at start-up

−85

1.30

80

−80

1.35

100

−75

1.40

140

μA

V

V_en(LATCH)

V_hys(LATCH)

hysteresis voltage on pin

LATCH

V_en(LATCH)− V_prot(LATCH)

mV

V_oc(LATCH)

open-circuit voltage on pin

LATCH

2.65

2.9

3.15

V

Temperature protection

T_pl(IC)

IC protection level temperature

130

-

140

10

150

-

°C

T_pl(IC)hys

hysteresis of IC protection level

temperature

[1] For a typical application with a compensation network on pin PFCCOMP, like the example in Figure 3.

[2] Minimum required voltage change time for valley recognition on pin PFCAUX.

[3] Minimum time required between demagnetization detection and ΔV/Δt = 0 on pin PFCAUX.

[4] Hysteresis for PFC on/off control.

[5] Guaranteed by design.

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

24 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

11. Application information

A power supply with the TEA1751(L)T consists of a power factor correction circuit

followed by a flyback converter. See Figure 16.

Capacitor C_VCCbuffers the IC supply voltage, which is powered via the high voltage

rectified mains during start-up and via the auxiliary winding of the flyback converter during

operation. Sense resistors R_SENSE1and R_SENSE2convert the current through the

MOSFETs S1 and S2 into a voltage at pins PFCSENSE and FBSENSE. The values of

R

_SENSE1and R_SENSE2define the maximum primary peak current in MOSFETs S1 and S2.

In the example given, the LATCH pin is connected to a Negative Temperature Coefficient

V_prot(LATCH)

I_O(LATCH)

-------------------------------

(NTC) resistor. When the resistance drops below

= 15.6 kΩ (typ), the

protection is activated. A capacitor C_TIMEOUTis connected to the FBCTRL pin. For a

120 nF capacitor, typically after 10 ms the time-out protection is activated. R_LOOPis added

so that the time-out capacitor does not interfere with the normal regulation loop.

R

_S1and R_S2are added to prevent the soft start capacitors from being charged during

normal operation due to negative voltage spikes across the sense resistors.

Resistor R_AUX1is added to protect the IC from damage during lightning events.

D1

C

bus

S1

C

R

SS1

D2

T2

C

OUT

R

SENSE1

R

AUX1

R

S2

S1

12

8

11

9 16 13

R

SS2

S2

10

COMPENSATION

6

C

SS2

TEA1751(L)T

R

AUX2

SENSE2

7

4

1

5

C

3

VCC

2

R

LOOP

Θ

C

TIMEOUT

014aaa302

Fig 17. Typical application diagram TEA1751(L)T

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

25 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

12. Package outline

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

v

c

y

H

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.39

0.014 0.0075 0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig 18. Package outline SOT109-1 (SO16)

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

26 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

13. Revision history

Table 6.

Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

TEA1751T_LT_2

Modifications:

20091223

Product data sheet

-

TEA1751T_LT_1

• Value for junction temperature (T_j) changed in Table 3.

TEA1751T_LT_1

20090210

Product data sheet

-

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

27 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

14. Legal information

14.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

14.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between information in this document and such

terms and conditions, the latter will prevail.

14.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

14.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

GreenChip — is a trademark of NXP B.V.

15. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

TEA1751T_LT_2

Product data sheet

Rev. 02 — 23 December 2009

28 of 29

TEA1751T; TEA1751LT

NXP Semiconductors

GreenChip III SMPS control IC

16. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

7.3.10

7.3.11

Overpower protection. . . . . . . . . . . . . . . . . . . 18

Driver (pin FBDRIVER) . . . . . . . . . . . . . . . . . 19

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Distinctive features . . . . . . . . . . . . . . . . . . . . . . 1

Green features . . . . . . . . . . . . . . . . . . . . . . . . . 1

PFC green features . . . . . . . . . . . . . . . . . . . . . 2

Flyback green features. . . . . . . . . . . . . . . . . . . 2

Protection features . . . . . . . . . . . . . . . . . . . . . . 2

8

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 19

Thermal characteristics . . . . . . . . . . . . . . . . . 20

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20

Application information . . . . . . . . . . . . . . . . . 25

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 26

Revision history . . . . . . . . . . . . . . . . . . . . . . . 27

2.1

2.2

2.3

2.4

2.5

9

10

11

12

13

3

4

5

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

14

Legal information . . . . . . . . . . . . . . . . . . . . . . 28

Data sheet status. . . . . . . . . . . . . . . . . . . . . . 28

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 28

14.1

14.2

14.3

14.4

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7

7.1

7.1.1

Functional description . . . . . . . . . . . . . . . . . . . 5

General control. . . . . . . . . . . . . . . . . . . . . . . . . 5

Start-up and UnderVoltage LockOut

15

16

Contact information . . . . . . . . . . . . . . . . . . . . 28

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

(UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Supply management. . . . . . . . . . . . . . . . . . . . . 7

Latch input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Fast latch reset. . . . . . . . . . . . . . . . . . . . . . . . . 8

Overtemperature protection . . . . . . . . . . . . . . . 8

Power factor correction circuit . . . . . . . . . . . . . 8

t_oncontrol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Valley switching and demagnetization

7.1.2

7.1.3

7.1.4

7.1.5

7.2

7.2.1

7.2.2

(PFCAUX pin). . . . . . . . . . . . . . . . . . . . . . . . . . 8

Frequency limitation . . . . . . . . . . . . . . . . . . . . . 9

Mains voltage compensation

7.2.3

7.2.4

(VINSENSE pin) . . . . . . . . . . . . . . . . . . . . . . . . 9

Soft start-up (pin PFCSENSE) . . . . . . . . . . . . . 9

Low power mode . . . . . . . . . . . . . . . . . . . . . . 10

Dual boost PFC . . . . . . . . . . . . . . . . . . . . . . . 10

Overcurrent protection (PFCSENSE pin) . . . . 11

Mains undervoltage lockout / brownout

7.2.5

7.2.6

7.2.7

7.2.8

7.2.9

protection (VINSENSE pin) . . . . . . . . . . . . . . 11

Overvoltage protection (VOSENSE pin). . . . . 11

PFC open loop protection (VOSENSE pin) . . 11

Driver (pin PFCDRIVER) . . . . . . . . . . . . . . . . 11

Flyback controller . . . . . . . . . . . . . . . . . . . . . . 12

Multimode operation. . . . . . . . . . . . . . . . . . . . 12

Valley switching (HV pin) . . . . . . . . . . . . . . . . 13

Current mode control (FBSENSE pin) . . . . . . 14

Demagnetization (FBAUX pin) . . . . . . . . . . . . 15

Flyback control / time-out (FBCTRL pin) . . . . 15

Soft start-up (pin FBSENSE) . . . . . . . . . . . . . 17

Maximum on-time. . . . . . . . . . . . . . . . . . . . . . 17

Overvoltage protection (FBAUX pin) . . . . . . . 17

Overcurrent protection (FBSENSE pin) . . . . . 18

7.2.10

7.2.11

7.2.12

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.3.6

7.3.7

7.3.8

7.3.9

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 23 December 2009

Document identifier: TEA1751T_LT_2

型号:	TEA1751T
生命周期：	Active
IHS 制造商：	NXP SEMICONDUCTORS
零件包装代码：	SOIC
包装说明：	3.90 MM, PLASTIC, MS-012, SOT-109-1, SOP-16
针数：	16
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.73
Is Samacsys：	N
模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	CURRENT-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	650 V
最小输入电压：	9 V
标称输入电压：	20 V
JESD-30 代码：	R-PDSO-G16
长度：	9.9 mm
功能数量：	1
端子数量：	16
标称输出电压：	2.5 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
认证状态：	Not Qualified
座面最大高度：	1.75 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	SINGLE
最大切换频率：	150 kHz
技术：	BCDMOS
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
宽度：	3.9 mm
Base Number Matches：	1

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