好用的Verilog串口UART程序

==========================================================================//-----------------------------------------------------/⁄Design Name : uart /⁄File module uart (reset ,txclk ,ld_tx_data ,tx_data ,tx_enable ,tx_out ,tx_empty ,rxclk ,uld_rx_data ,rx_data ,rx_enable ,rx_in ,rx_empty);/⁄Port declarationsinput reset ;input txclk ;input ld_tx_data ;input [7:0] tx_data ;input tx_enable ;output tx_out ;output tx_empty ;input rxclk ;input uld_rx_data ;output [7:0] rx_data ;input rx_enable ;input rx_in ;output rx_empty ;/⁄Internal Variables reg [7:0] tx_reg ;reg tx_empty ;reg tx_over_run ;reg [3:0] tx_cnt ;reg tx_out ;reg [7:0] rx_reg ;reg [7:0] rx_data ;reg [3:0] rx_sample_cnt ;reg [3:0] rx_cnt ; reg rx_frame_err ;reg rx_over_run ;reg rx_empty ;reg rx_d1 ;reg rx_d2 ;reg rx_busy ;/⁄UART RX Logicalways @ (posedge rxclk only when rx is enabledif (rx_enable) begin /⁄Check if just received start Start with rest target=_blank>星梦居