LatticeXP2标准评估板主要特性与电路图

日期：2012-8-16~~标签：~~ （来源：互联网）

LATTICE 公司的LatticeXP2器件包括基于查找表(LUT)的 FPGA以及非易失闪存单元(flexiFLASH)。LatticeXP2系列器件的LUT从5K到40K，分布是RAM从10K到83Kb，EBR SRAM从166Kb到885Kb，EBR SRAM区块从9到48个，sysDSP从3个到8个，18x18乘法器从12个到32个，可用的I/O从172个到540个，GPLL从2个到4个。工作电压1.2V，主要用在对成本敏感的市场如消费类电子，汽车电子，医疗和工业，网络和计算。本文介绍了LatticeXP2系列主要特性，LatticeXP2-17器件简化方框图，LatticeXP2标准评估板主要特性和LatticeXP2标准评估板电路图。

LatticeXP2 DEVICES combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an architec-ture referred to as flexiFLASH. The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with FlashBAK embedded block MEMORY and Serial TAG memory and design security. The parts also SUPPORT Live Update TECHNOLOGY with TransFR, 128-bit AES Encryption and Dual-boot technologies. The LatticeXP2 FPGA fabric was optimized for the new technology from the outset with high performance and low cost in mind. LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support and enhanced sysDSP blocks. The ispLEVER? design tool from Lattice allows large and complex DESIGNS to be efficiently implemented using the LatticeXP2 family of FPGA devices. Synthesis library support for LatticeXP2 is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool OUTPUT along with the constraints from its floor planning tools to place and route the design in the LatticeXP2 device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification. Lattice provides many pre-designed Intellectual Property (IP) ispLeverCORE? MODULES for the LatticeXP2 family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity.

Each LatticeXP2 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM? Embedded Block RAM (EBR) and a row of sys- DSP? DIGITAL Signal Processing blocks as shown in Figure 2-1. On the left and right sides of the Programmable Functional Unit (PFU) array, there are Non-volatile Memory Blocks. In configuration mode the nonvolatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIG? peripheral port. On power up, the configuration data is transferred from the Non-volatile Memory Blocks to the configuration SRAM. With this technology, expensive external configuration memory is not required, and designs are secured from unauthorized read-back. This transfer of data from non-volatile memory to configuration SRAM via wide busses happens in microseconds, providing an “instant-on” capability that allows easy interfacing in many applications. LatticeXP2 devices can also transfer data from the sysMEM EBR blocks to the Non-volatile Memory Blocks at user request. There are two kinds of logic blocks, the PFU and the PFU without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for flexibility allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. Only one type of block is used per row. LatticeXP2 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large dedicated 18Kbit memory blocks. Each sysMEM block can be configured in a variety of depths and widths of RAM or ROM. In addition, LatticeXP2 devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and adder/accumulators, which are the building blocks for complex signal processing capabilities. Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO buffers. The sysIO buffers of the LatticeXP2 devices are arranged into eight banks, allowing the implementation of a wide variety of I/O standards. PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic also includes pre-engineered support to aid in the implementation of high speed source synchronous standards such as 7:1 LVDS interfaces, found in many DISPLAY applications, and memory interfaces including DDR and DDR2. Other blocks provided include PLLs and configuration functions. The LatticeXP2 architecture provides up to four GENERAL Purpose PLLs (GPLL) per device. The GPLL blocks are located in the corners of the device. The configuration block that supports features such as configuration bit-stream de-encryption, transparent updates and dual boot support is located between banks two and three. Every device in the LatticeXP2 family supports a sysCONFIG port, muxed with bank seven I/Os, which supports serial device configuration. A JTAG port is provided between banks two and three. This family also provides an on-chip oscillator and Soft Error Detect (SED) capability. LatticeXP2 devices use 1.2V as their core voltage.

LatticeXP2 devices are ideal for a variety of applications in cost sensitive markets such as Consumer, Automotive, Medical & Industrial, Networking and Computing。

LatticeXP2主要特性：

LatticeXP2系列产品：

图1。LatticeXP2-17器件简化方框图(顶视图)

LatticeXP2 devices are ideal for a variety of applications in cost sensitive markets such as Consumer, Automotive, Medical & Industrial, Networking and Computing

LatticeXP2标准评估板

LatticeXP2 Standard EVALUATION Board

The LatticeXP2? Standard Evaluation Board provides a convenient platform to EVALUATE, test and debug user designs. The board features a LatticeXP2-17 FPGA in a 484 fpBGA package. The LatticeXP2 I/Os are connected to a rich variety of interfaces described later in this document.

This document (including the schematics in the appendix) describes LatticeXP2 Standard Evaluation BOARDS marked as Rev 000. This MARKING can be seen on the etching on the back of the printed CIRCUIT board, under the Lattice SEMICONDUCTOR logo.

The LatticeXP2 is a third-generation non-volatile FPGA device. It combines a Look-up Table (LUT) based FPGA fabric with Flash Non-volatile cells in a flexiFLASH? architecture. The flexiFLASH approach provides benefits such as instant-on, small footprint, on chip storage with FlashBAK? embedded block memories and Serial TAG memory and design security. The LatticeXP2 also supports live updates with TransFR?, 128-bit AES Encryption and Dual-Boot technologies. The LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O and enhanced sysDSP? blocks.