本文介绍了TC90407XBG的主要性能,方框图以及软件架构图

东芝公司的TC90407XBG.html" target="_blank" title="TC90407XBG">TC90407XBG单片解决方案是中低档数字电视的第二代产品.和第一代产品相比,它集成了两个模拟和一个数字输出,并集成了用于ATSC和有线码流解调器的VSB/QAM逻辑.

TC90407XBG有多个引擎,能对多媒体进行计算,以减轻主CPU的任务,使其更有效地对DTV应用进行系统管理.

本文介绍了TC90407XBG的主要性能,方框图以及软件架构图.

TC90407XBG/FG Single-chip Solutions for DIGITAL TV

The TC90407XBG/FG is the second generation product from TOSHIBA targeted for mid- to low-end digital TV applications.

Compared to previous DESIGNS, it integrates more functional blocks on chip reducing SYSTEM cost and supports new algorithms for improved picture quality. The DEVICE incorporates VSB/QAM logic on chip for ATSC and Cable streams demodulation.

The TC90407XBG/FG is capable of decoding single SD or HD stream and DISPLAY content in standard-definition resolution (720 x 480 pixels) or half high definition resolution (960 x 1080 pixels).

With two ANALOG and one 8/16-bit digital outputs, the TC90407XBG is a very cost effectivesolution for CRT TV, LCD TV or digital-to-analog CONVERTER set-top box applications.

The TC90407XBG/FG DEVICES use multiple DSP engines to perform compute-intensive,MULTIMEDIA operations to offload the main CPU for efficient system management of demanding digital TV applications. The TC90407XBG architecture also supports a unified 16-bit DDR MEMORY system, as well as a NAND and a NOR flash memory CONTROLLER to reduce overall system cost.

Features

162 MHz TX49/L3 64-bit MIPS RISC core

8 KB each I & D cache

Unified memory system

DDR SDRAM controller (16-bit, 162 MHz)

NAND & NOR Flash support

Transport Stream Processor

Fully compliant to ATSC and cable transport streams

Video DECODER (SD decoding)

MPEG-2 decoding (MP@ML and MP@SL) and MPEG-1 decoding

Single-MPEG-2 decoding

Video Decoder (HD decoding)

MPEG-2 decoding for MP@HL for ATSC

Display in HD resolution up to 960 x 1080

720p or 1080i compliant

HD-to-SD down-conversion

Display in SD resolution

Highlights

Highly INTEGRATED systemon-chip (SoC) for digital TVs that incorporates a high- performance 64-bit

RISC processor and two highly optimized DSP processors

Specifically designed for North American TV standards (ATSC & digital cable)

Integrated VSB/QAM DEMODULATOR for ATSC TV

Complete reference system with SOFTWARE and middleware support for quick product deployment

Software and middleware based on Linux? OS

COMMON API support for middleware and application development

Decode single-standard definition stream or single high-definition stream

Decode one audio stream

Two 480i or one 720p/1080i analog video outputs and one SD/HD digital video output

Unified memory architecture for optimum system cost

Built-in MPEG-2 decoder, high-performance scalar and graphics controller for high-quality video output

Low-power SoC with power-down modes

PACKAGE: 292-pin PBGA and 256-PIN.html" target="_blank" title="256-PIN">256-PIN LQFP

Audio Processor

MPEG- Audio, Dolby AC-3 decoding

I2S and S/P-DIF Transmitter (IEC-60958/61937)

Graphics Engine

Two planes (YUV/Graphics)

Alpha blending and video scaling

Progressive scan (I/P conversion by line-interpolation)

Video Output

Dual NTSC Video Encoder

4 DACs (supports two 480i analog outputs for SD and one 720p/1080i output for HD)

4:2:2 YUV Digital-Output (ITU R656/R601)

VBI re-insertion (closed-caption and CGMS-A)

Interlaced or progressive output

Interfaces and Peripherals

8/16-bit local bus for NAND/NOR flash and other I/O devices (40.5 MHz), DMA controller (2 ch), SIO (2 ch), PIO (10), timer/counter (three 24-bit), I2C (2 ch), IR-decoding and IR-blaster

Power-down and Standby Operations

Package

TC90407XBG