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THS8135

TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO

(ITU-R.BT601)—COMPLIANT FULL SCALE RANGE

SLAS343A – MAY 2001 – REVISED JUNE 2002

D

Bi-Level (EIA) or Tri-Level (SMPTE) Sync

Generation

features

D

Triple 10-Bit D/A Converters

240-MSPS Operation

Integrated Sync-On-Green/Luminance or

Sync-On-All Composite Sync Insertion

D

YPbPr/RGB Configurable Blanking Levels,

Correctly Positioned for Either Full

(0–1023) or Video (ITU–R.BT601) –

Compliant Input Code Ranges

D

Internal Voltage Reference

D

Low-Power Operation From 3.3-V Analog

and 1.8-V Digital Suply Levels

D

Generic Triple DAC Mode for Non-Video

Applications

applications

D

High-Definition Television (HDTV) Set-Top

Boxes/Receivers/Displays

Direct Drive of Double-Terminated 75-Ω

Load Into Standard Video Levels

D

High-Resolution Image Processing

3x10 Bit 4:4:4, 2x10 Bit 4:2:2 or 1x10 Bit

4:2:2 (ITU–R.BT656) Multiplexed

YCbCr/GBR Input Data Formats

description

The THS8135 is a general-purpose triple high-speed D/A converter optimized for use in video/graphics

applications. The device operates from 3.3-V analog and 1.8-V digital supplies. The THS8135 performance is

assuredatasamplingrateupto240MSPS. TheTHS8135consistsofthree10-bitD/Aconvertersandadditional

circuitry for bi-level/tri-level sync and blanking level generation. By providing a dc offset for the lowest video

amplitude output in video DAC mode, the device can insert a (negative) bi-level or (negative/positive) tri-level

sync on either only the green/luminance (sync-on-green/sync-on-Y) channel or on all channels for video

applications. A generic DAC mode avoids this dc offset, making this device suitable for non-video applications

as well.

The THS8135 is a footprint-compatible functional upgrade to the THS8133. In addition, the THS8135 allows

a higher update rate for oversampled video digitizing for all PC graphics formats up to UXGA (1600x1200)

resolution at 85 Hz and all practical digital TV formats including HDTV. The support for oversampling

significantly reduces the complexity of the analog reconstruction filter required behind the DAC.

Standard video levels can be generated for the full 10-bit input code range. Alternatively, the same levels can

be reached from a reduced input code range compliant to the video sampling standard ITU-R.BT-601. In that

case, the full-scale range of the DAC is dependent on the RGB or YCbCr color space configuration of the device.

When configured for RGB operation, full video output swing is reached for input codes 64-940 on all channels.

When configured for YCbCr operation, code range 64-940 on Y and code range 64-960 on Cb and Cr channels

generate full output swing using internal amplitude scaling on these color components. The device provides

headroom to accommodate under-/over-shoot outside the ITU-R.BT601 range to allow the generation of

ITU-R.BT601 illegal colors or super-black / super-white levels.

A digital control input for insertion of a reference (blanking) level on the analog outputs is included. The

amplitudeoftheblankinglevelisconfigurableforeitherRGBorYPbPrcomponentoutputsandforfullorreduced

input code ranges. The inserted sync output amplitude(s) always has the required 7:3 ratio to the full-scale video

amplitude.

The current-steering DACs can be directly terminated in resistive loads to produce voltage outputs. The device

provides a flexible configuration of maximum output current drive. The devices output drivers have been

specifically designed to produce standard video output levels when directly connected to a single-ended

double-terminated 75-Ω coaxial cable.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS8135

TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO

(ITU-R.BT601)—COMPLIANT FULL SCALE RANGE

SLAS343A – MAY 2001 – REVISED JUNE 2002

description (continued)

The input data format can be either 3x10 bit 4:4:4, 2x10 bit 4:2:2, or 1x10 bit 4:2:2. This enables a direct interface

to a wide range of video DSP/ASICs including parts generating ITU-R.BT656 formatted output data. However,

the THS8135 needs specific input synchronization signals to properly insert a composite sync onto its outputs

as it does not extract embedded SAV/EAV synchronization codes from the ITU-R.BT656 input. Along with other

extra functionality, this feature is available on a derivative device (THS8200).

AVAILABLE OPTIONS

T

A

PACKAGED DEVICES: TQFP-48 PowerPAD

0°C to 70°C

THS8135PHP

TQFP-48 PowerPAD PACKAGE

(TOP VIEW)

48 47 46 45 44 43 42 41 40 39 38 37

36

35

34

33

32

31

30

29

28

27

26

25

GY0

BCb9

BCb8

BCb7

BCb6

BCb5

BCb4

BCb3

BCb2

BCb1

1

2

3

4

5

6

7

8

9

GY1

GY2

GY3

GY4

GY5

GY6

GY7

GY8

GY9

CLK

BCb0 10

DV

11

12

SS

DD

SYNC_T

DV

13 14 15 16 17 18 19 20 21 22 23 24

PowerPAD is a trademark of Texas Instruments.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS8135

TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO

(ITU-R.BT601)—COMPLIANT FULL SCALE RANGE

SLAS343A – MAY 2001 – REVISED JUNE 2002

functional block diagram

DV

VREF

COMP FSADJ

DD

SS

Bandgap

Reference

R/Cr

Register

RCr[9:0]

GY[9:0]

DAC

ARPr

G/Y

Register

Input

Formatter

AGY

B/Cb

Register

BCb[9:0]

ABPb

CLK

M1

M2

Configuration

Control

SYNC/BLANK

Control

SYNC

BLANK

AV

DD

AV

SS

SYNC_T

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS8135

TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO

(ITU-R.BT601)—COMPLIANT FULL SCALE RANGE

SLAS343A – MAY 2001 – REVISED JUNE 2002

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

ABPb

NO.

45

O

I

Analog blue or Pb current output, capable of directly driving a double terminated 75-Ω coaxial cable

Analog green or Y current output, capable of directly driving a double terminated 75-Ω coaxial cable

Analog red or Pr current output, capable of directly driving a double terminated 75-Ω coaxial cable

AGY

41

ARPr

43

AV

40, 44

42, 46

10–1

23

Analog power supply (3.3 V). All AV

pins must be connected.

DD

SS

AV

I

Analog ground

BCb0–BCb9

I

Blue or Cb pixel data input. Signals with index 0 denote the least significant bits.

BLANK

I

Blanking control input, active low. A rising edge on CLK latches BLANK. When asserted, the ARPr, AGY, and

ABPb outputs are driven to the blanking level, irrespective of the value on the data inputs. SYNC takes

precedence over BLANK, so asserting SYNC (low) while BLANK is active (low) results in sync generation.

The amplitude of the DAC outputs during BLANK active are determined by the color space and input code

range configurations of the device. BLANK control is available in both video and generic DAC modes.

CLK

26

I

Clock input. A rising edge on CLK latches RCr0–9, GY0–9, BCb0–9, BLANK, SYNC, and SYNC_T.

InvideoDACmode, theM1andM2inputsarelatchedbyarisingedgeonCLKaswellbutonlywhenadditional

conditions are satisfied as explained in their terminal description.

In generic DAC mode, M1 and M2 are continuously interpreted i.e. independent of additional conditions, to

determine color space and input data formats. This allows easier configuration.

COMP

39

12

11

38

O

I

Compensation terminal. A 0.1-µF capacitor must be connected between COMP and AV

.

DD

DV

Digital power supply (1.8 V)

Digital ground

DD

SS

I

FSADJ

I

Full-scaleadjustcontrol. Thefull-scalecurrentdriveoneachoftheoutputchannelsisdeterminedbythevalue

of a resistor R connected between this terminal and AV . Figure 5 shows the relationship between

FS SS

full-scale output voltage compliance and R for the nominal DAC termination of 37.5 Ω.

FS

GY0–GY9

36–27

I

Green or Y pixel data input. Signals with index 0 denote the least significant bits.

M1

47

Operation mode control 1.

In video DAC mode, the second rising edge on CLK after a transition on SYNC latches M1. The interpretation

is dependent on the polarity of the last SYNC transition:

SYNC L → H: latched as M1_INT

SYNC H → L: latched as BLNK_INT.

Together with M2_INT, M1_INT configures the device as shown in Table 2 for video DAC mode. BLNK_INT

determines if the device operates with the full- or reduced-scale input code range. Together with the color

space configuration, this sets the amplitude of the blanking level on the analog output(s) as shown in Table 5.

In generic DAC mode, M1 is continuously interpreted as M1_INT, BLNK_INT control is not available and the

device always assumes full-scale input code range for blank level positioning.

M2

48

I

Operation mode control 2.

In video DAC mode, the second rising edge on CLK after a transition on SYNC latches M2. The interpretation

is dependent on the polarity of the last SYNC transition:

SYNC L → H: latched as M2_INT

SYNC H → L: latched as INS3_INT

Together with M1_INT, M2_INT configures the device as shown in Table 3 for video DAC mode. When

INS3_INT is high, the device inserts sync on all DAC outputs; when low, sync is inserted only on the AGY

output.

In generic DAC mode, M2 is continuously interpreted as M2_INT, INS3_INT control is not applicable, since

sync insertion is not available in generic DAC mode.

RCr0–RCr9

13–22

I

Red or Cr pixel data input. Signals with index 0 denote the least significant bits.

SYNC

24

Sync control input, active low. A rising edge on CLK latches SYNC. When asserted, only the AGY output

(when INS3_INT=L, see terminal M2) for sync-on-G/Y, or ARPr, AGY, and ABPb outputs (whenINS3_INT=H,

see terminal M2) for sync-on-all, are driven to the sync level, irrespective of the values on the data or BLANK

inputs. Therefore, SYNC should remain low for the whole duration of sync, which is in the case of a tri-level

sync both the negative and positive portion. See Figure 10 for timing control. SYNC control is only available in

video DAC mode.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS8135

TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO

(ITU-R.BT601)—COMPLIANT FULL SCALE RANGE

SLAS343A – MAY 2001 – REVISED JUNE 2002

Terminal Functions (Continued)

TERMINAL

NAME

SYNC_T

I/O

DESCRIPTION

NO.

25

I

Sync tri-level control, active high. A rising edge on CLK latches SYNC_T. When asserted (high), a positive

sync(higherthanblankinglevel)isgeneratedwhenSYNC is low. Whendisabled(low), anegativesync(lower

than blanking level) is generated when SYNC is low. When generating a tri-level (negative-to-positive) sync,

an L->H transition on this signal positions the start of the positive transition. See Figure 10 for timing control.

SYNC_T is also used to put the device in generic DAC mode: SYNC=H AND SYNC_T = H -> generic DAC

mode. Therefore, the user should always drive SYNC_T low outside the sync period when video DAC mode

operation is intended.

V

REF

37

O

Voltage reference for DACs. An internal voltage reference of nominally 1.2 V is provided, which requires an

external 0.1-µF ceramic capacitor between VREF and AV

.

SS

detailed description

The THS8135 is a fast well-matched triple DAC with current outputs optimized for video applications without

sacrificing its usefulness as a general-purpose triple DAC, thanks to a generic DAC mode. For video

applications, the device can embed an analog output (composite) bi-level or tri-level sync on only the

green/luma channel or on all three DAC output channels. The THS8135 offers compatibility with several popular

video data formats and provides standard analog output compliance levels for component video digitized

according to the ITU-R.BT601 sampling standard. The DAC full-scale range is also adjustable.

sync generation

The SYNC and SYNC_T control inputs enable the superposition of an additional current onto the AGY channel

or onto all three channels, depending on the setting of INS3_INT. Using a combination of the SYNC and

SYNC_T control inputs, either bi-level negative going pulses or tri-level pulses can be generated. By driving

these terminals with the correct timing inputs, the user can insert onto the analog output(s) any composite sync

format consisting of horizontal sync, vertical sync, pre- and post-serration, and equalization pulses. Assertion

of SYNC (active low) identifies the sync period, while assertion of SYNC_T (active high) within this period

identifies the positive excursion of a tri-level sync.

blanking generation

TheBLANKcontrolinputfixestheoutputamplitudeonallchannelstotheblankinglevel, irrespectiveofthevalue

on the data input ports. The position of the blanking level on each channel and its relation to active video is

different depending on the RGB versus YCbCr color space configuration: bottom-range blanking level for R,

G, B, and Y outputs versus mid-range blanking level for Pb and Pr outputs. This also depends on the full-scale

versus reduced-scale (ITU-R.BT601) input code range configuration: bottom-range blanking levels correspond

to input code 0 when in full-scale, or to code 64 when in reduced-scale input code range configuration;

mid-range blanking levels remain at 512 in all cases.

generic DAC mode versus video DAC mode

In video DAC mode, the device provides additional dc bias on R, G, B, and Y channels to provide headroom

for negative sync insertion, as shown on Figure 1 and Figure 3.

Such bias might be undesirable in applications where no sync embedding is needed, since it causes additional

power consumption and might prevent dc coupling of the DAC outputs. In such cases, only a triple DAC

operation without dc bias (i.e., DAC input code 0 corresponding to 0-V output) might be preferred as there is

no need for sync insertion. Therefore, the THS8135 includes a generic DAC mode that does not add any dc

bias. Sync insertion is not supported in generic DAC mode. Also, in this mode, only full-scale operation is

available. Other features are still available in generic DAC mode: different input data formats, RGB versus

YCbCr color space selection, and blanking level override option.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS8135

TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO

(ITU-R.BT601)—COMPLIANT FULL SCALE RANGE

SLAS343A – MAY 2001 – REVISED JUNE 2002

generic DAC mode versus video DAC mode (continued)

Because of the eliminated dc bias, the DAC output compliance for full-range video input can be higher in generic

DACmode:upto1.286Vppatnominaldouble75-Ω terminationload. ThisishighenoughfortheD/Aconversion

of composite video (NTSC/PAL/SECAM), where the signal fed to the device contains the complete digital

composite waveform, including sync and color-burst.

Selection between generic DAC versus video DAC mode is controlled through a combination of SYNC and

SYNC_T settings. Since in video DAC mode, SYNC_T only determines the sync polarity, this signal has don’t

care status when no sync insertion takes place i.e., when SYNC is high. The THS8135 uses the logic level on

the SYNC_T input when SYNC is high to enter generic DAC mode: SYNC_T and SYNC are high → generic

DAC mode. Therefore, the user must make sure to keep SYNC_T low outside the sync insertion period (when

SYNC is high) to prevent entering generic DAC mode, when he intends to use the device in video DAC mode.

Table 1 shows how to select between video DAC and generic DAC mode.

Table 1. Video vs Generic Mode Selection

SYNC

BLANK

SYNC_T

OPERATION MODE AND DAC OUTPUT

Generic DAC mode. Blanking override inactive.

1

0

1

Generic DAC mode. Blanking override active. Blanking level position is according to the codes of Table 5,

however no dc bias is present on the Y, R, G, and B outputs

1

0

Video DAC mode. Blanking override inactive

VideoDACmode. Blankingoverrideactive. BlankinglevelpositionisaccordingtothecodesofTable5, withdc

bias present on the Y, R, G, and B outputs as shown in Figure 1 and Figure 3.

0

X

0

1

Video DAC mode. Negative sync inserted

Video DAC mode. Positive sync inserted

device configuration using M1 and M2 in video DAC mode

In the video DAC mode, the configuration signals M1 and M2 are both sampled on the second rising edge of

the CLK input signal after a L → H or H → L transition on SYNC. Depending on the polarity of this last transition

on SYNC, M1 and M2 are interpreted differently by the THS8135, as shown in Table 2.

NOTE:

In the THS8133, only M2 is a sampled signal while M1 is continuously interpreted. By doing so here,

the additional input control signal BLNK_INT is generated. See the backward compatibility with the

THS8133 section.

Table 2. Interpretation of M1 in Video DAC Mode

Then M1 is interpreted on

If last event on

SYNC is:

the second CLK rising edge

following this event as:

DESCRIPTION

Sets operation with full or video (ITU–R.BT601) – input code range i.e., the full-scale

rangeisreachedfromeitherthe0–102310-bitinputcoderangeortheinputcoderangeof

Table 6, see also Table 5 for blanking level positions.

H → L

L →H

BLNK_INT

M1_INT

Sets device operation mode. See Table 4 and Table 5.

Table 3. Interpretation of M2 in VIdeo DAC Mode

Then M2 is interpreted on

If last event on

SYNC is:

the second CLK rising edge

following this event as:

DESCRIPTION

SetssyncInsertionmode:SYNClowenablessyncgenerationonone(INS3_INT=L)orall

three (INS3_INT=H) DAC outputs. SYNC_T determines the sync polarity.

H →L

L →H

INS3_INT

M2_INT

Sets device operation mode. See Table 4 and Table 5.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS8135

TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO

(ITU-R.BT601)—COMPLIANT FULL SCALE RANGE

SLAS343A – MAY 2001 – REVISED JUNE 2002

device configuration using M1 and M2 in generic DAC mode

To simplify device configuration in the generic DAC mode, the M1 and M2 configuration pins are continuously

interpreted as M1_INT and M2_INT respectively, i.e., their interpretation is not dependent on the last event on

SYNC and is not only sampled on the second rising CLK edge after a transition on SYNC. BLNK_INT and

INS3_INT controls are not available in generic mode. As a result, in generic DAC mode, the device always

operates with full-scale input range and no sync insertion is available.

M1_INT and M2_INT can be tied high or low externally to determine the input formatter setting and color space

forblanklevelpositions. BlankingoverrideisstillavailableingenericDACmodeusingtheBLANKinput. Generic

DAC mode only disables the dc bias for R, G, B, and Y component outputs.

Table 1 shows all combinations of these control signals. Note that when SYNC is low, it takes precedence over

BLANK.

selection of color space and input formatter configuration (available in video DAC and generic DAC modes)

Input data to the device can be supplied from a 3x10b GBR or YCbCr input port. If the device is configured to

take data from all three channels, the data is clocked in at each rising edge of CLK. All three DACs operate at

the full clock speed of CLK.

In the case of 4:2:2 sampled data (for YCbCr data), the device can be fed over either a 2x10 bit or 1x10 bit

multiplexed input port. An internal demultiplexer routes the input samples to the appropriate DAC: Y at the rate

of CLK, Cb and Cr each at rate of 1/2 CLK.

According to ITU-R.BT-656, the sample sequence is Cb-Y-Cr-Y over a 1x10-bit interface (Y-port). The sample

sequence starts at the first rising edge of CLK after BLANK has been taken high (inactive). Note that in this case

the frequency of CLK is 2x the Y conversion speed and 4x the conversion speed of both Cr and Cb.

In the case of a 2x10 bit input interface, both the Y-port and the Cr-port are sampled on every CLK rising edge.

The Cr-port carries the sample sequence Cb-Cr. The sample sequence starts at the first rising edge of CLK after

BLANK has been taken high (inactive). Note that in this case the frequency of CLK is equal to the conversion

speed of Y and 2x the conversion speed of both Cr and Cb.

Table 4 shows the possible configurations of the input formatter, as determined by the internal M1_INT and

M2_INT signals. The color space selection also determines the position of the blanking level and is explained

in the next section.

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS8135

TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO

(ITU-R.BT601)—COMPLIANT FULL SCALE RANGE

SLAS343A – MAY 2001 – REVISED JUNE 2002

Table 4. THS8135 RGB/YCbCr Color Space and Input Formatter Configuration

M1_INT M2_INT

CONFIGURATION

DESRIPTION

L

GBR 3x10b–4:4:4 GBR mode 4:4:4. Data clocked in on each rising edge of CLK from G, B, and R input channels.

H

YCbCr 3x10b–4:4:4 YCbCr mode 4:4:4. Data clocked in on each rising edge of CLK from Y, Cb, and Cr inputchannels.

YCbCr mode 4:2:2 2x10 bit. Data clocked in on each rising edge of CLK from Y channel. A sample

YCbCr 2x10b–4:2:2 sequence of Cb-Cr should be applied to the Cr port. At the first rising edge of CLK after BLANK is

taken high, Cb should be present on this port.

H

L

YCbCrmode4:2:21x10bit(ITU-R.BT-656compliant).DataclockedinoneachrisingedgeofCLK

YCbCr 1x10b–4:2:2 fromYchannel. AsamplesequenceofCb-Y-Cr-YshouldbeappliedtotheYport. Atthefirstrising

edge of CLK after BLANK is taken high, Cb should be present on this port.

H

selection of full- or reduced-scale ITU-R.BT601 modes (available in video DAC mode only)

In video DAC mode, BLNK_INT sets the blanking level generated on the DAC outputs as shown in Table 5. This

allows imposing a blanking level on the analog outputs corresponding to either full-scale code range or a

reduced-scale code range compliant to ITU-R.BT601. The blanking level is correctly positioned for either RGB

or YCbCr configurations, determined from the M1/M2 setting.

For generic DAC mode, BLNK_INT control is not available and the device always generates an output level

during BLANK low assuming full-scale input code range.

Table 5. Full-Scale or ITU.BT601 Reduced-Scale Mode Selection and

Impact on Blanking Level Positioning

CHANNEL OUTPUT LEVEL

DURING BLANK ACTIVE

CORRESPONDING TO DAC

INPUT CODE:

AVAILABLE IN

VIDEO DAC (V)

AND

GENERIC DAC

(G) MODES?

M1_INT M2_INT BLNK_INT

OPERATION MODE

AGY

0

ABPb

0

ARPr

0

L

H

L

V, G

V

GBR 3x10b 4:4:4, full scale range

GBR 3x10b 4:4:4, ITU–R.BT601-compliant range

YCbCr 3x10b 4:4:4, full scale range

64

0

64

L

H

L

V, G

V

512

L

H

L

YCbCr 3x10b 4:4:4, ITU–R.BT601-compliant range

YCbCr 2x10b 4:2:2, ITU–R.BT601-compliant range

YCbCr 2x10b 4:2:2, full scale range

64

0

H

V

L

H

L

V, G

V

H

YCbCr 1x10b 4:2:2, ITU–R.BT601-compliant range

YCbCr 1x10b 4:2:2, full scale range

64

0

H

V, G

In full-scale range, the DAC is driven with input codes 0-1023 to the desired video level, set by the resistor

connected to the FSADJ terminal (e.g., a full-scale video amplitude of 700 mV when terminated into 37.5 Ω and

when using the nominal R value).

FS

In reduced-scale ITU-R.BT601 range, it is the intention that full-scale video amplitude is reached when the

device is driven with digital inputs within the input code range shown in Table 6. Note that the code range is

unequal between RGBY on one hand and CbCr on the other hand. Figure 1 through Figure 4 illustrates the

difference between ITU-R.BT601 reduced-scale and full-scale code range operation. In reduced-range

configuration, the B/Cb and R/Cr components are digitally amplitude scaled internally. Note that there is no

scaling on the G/Y component. Therefore, to accommodate the 700-mV video compliance on all components,

the DAC full-scale output current needs to be increased between full-scale and reduced scale modes by a factor

of 1023/(940-64) by decreasing R in that proportion.

FS

This implementation has the advantage of avoiding amplitude scaling on the most critical G/Y component, while

still providing the possibility for instantaneous overshoot/undershoot on the analog component video output

when illegal signals according to ITU-R.BT601, such as super-black or super-white, are applied to the device.

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS8135

TRIPLE 10-BIT, 240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO

(ITU-R.BT601)—COMPLIANT FULL SCALE RANGE

SLAS343A – MAY 2001 – REVISED JUNE 2002

selection of full or reduced-scale ITU.BT601 modes (available in video DAC mode only) (continued)

When using reduced-scale range, the output sync:video amplitude ratio is still 7:3, but now takes into account

the reduced code range, not the full-scale range, to determine this ratio. Therefore, proper sync amplitudes are

preserved in either mode, when the full-scale current is modified as explained higher. When changing DAC

full-scale current using R , the sync amplitude level always scales proportionally with the video output

FS

compliance.

Note that even when using reduced-scale range, the midscale blanking level on ABPb and ARPr channels still

corresponds to code 512 = [64+(960-64)/2] when using YCbCr color space configuration. Table 6 shows the

valid reduced input code ranges for RGB and YCbCr operation on each of the input data buses. While the

THS8135 allows reduced-scale code range with RGB data, video systems normally use it only with YCbCr type

data.

Table 6. Input Code Ranges for ITU.BT601 Modes

OPERATING MODE

GY[]

RPr[]

64–940

64–960

BPb[]

64–940

64–960

RGB

64–940

YCbCr

DAC operation

The analog output drivers generate a current of which the drive level can be user-modified by choosing an

appropriate resistor value R , connected to the FSADJ pin.

FS

All current source amplitudes (video, blanking, and sync) are derived from an internal voltage reference such

that the relative amplitudes of sync, blank, and video are always equal to their nominal relationships.

Figure 1 through Figure 4 show the nominal output voltage levels for full- or reduced-range input code range

configurations on R, G, B, and Y versus Cb and Cr channels.

Note that in full-scale input code range configuration, the blanking level is at 350 mV on all outputs; while in

reduced-scale operation it is at 400 mV on all outputs.

Inreducedscalemodes,afterproperadjustmentofR ,thenominal700-mVoutputcomplianceisreachedfrom

FS

an input code range of only 876 (=940-64) codes on G/Y, and of only 896 (=960-64) codes on R/Pr and B/Pr

output channels. The maximum excursions are ~817mV (= 1023/876 x 700 mV) on G/Y and ~800 mV (=

876/896 x 817 mV) on B/Pb and R/Pr channels. Figure 4 shows that when using reduced-scale input code

range, the blanking level needs to be at 400 mV to accommodate the maximum negative excursion on B/Pr and

R/Pr channels.

The figures also show the excursions for the sync level positions in either full-scale or reduced-scale

configurations. These levels are internally adjusted and assure 300-mV sync excursions when using nominal

termination loads and properly adjusting R , as explained before.

FS

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V

Input

O

Codes mV

1023 1050

700 mV

300 mV

0

350

50

NOTE: Choose R

for 700 mV from input codes 0–1023 on Y

FS

Figure 1. YRGB Outputs, Full-Scale Input Code Range

V

Input

O

Codes mV

1023

700

300 mV

700 mV

512 350

0

Figure 2. CbCr Outputs, Full-Scale Input Code Range

V

Input

O

Codes mV

Super-Black/Super-White

Excursions (Reduced-Scale

Input Code Range)

1023

940

1167

1100

700 mV

817 mV

300 mV

64

0

400

350

100

NOTE: Choose R

for 700 mV from input codes 64–940 on Y

FS

Figure 3. YRGB Outputs, Reduced-Scale Input Code Range

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V

Input

O

Illegal Color

Difference Outputs

Codes mV

1023

960

800

700

400

800 mV

700 mV

300 mV

512

64

0

50

0

Figure 4. CbCr Outputs, Reduced-Scale Input Code Range

output amplitude control

The current drive on all three output channels (including sync) is controlled by a resistor R that must be

FS

connected between FSADJ and AVSS. In all operation modes the relative amplitudes of these current drivers

are maintained irrespective of the R value, as long as a maximum current drive capability is not exceeded.

FS

Therefore, a 7:3 video to sync ratio is preserved when adjusting R

FS.

The sync generator is composed of different current sources that are internally routed to a corresponding DAC

output. Since they are additional to the video DACs, full 10-bit DAC resolution is preserved for video. Depending

on the setting of INS3_INT during SYNC low, the sync current drive is added to either only the green channel

output (sync-on-G/Y) if INS3_INT=L or all three channel outputs (sync-on-all) if INS3_INT=H. Sync insertion

is only available in video DAC mode.

Figure 5 shows the relationship between R and the current drive level on each channel for full-range DAC

FS

input. When using reduced-scale range, the codes on the G/Y channel are not internally scaled (only BCb and

RCr channels are scaled). Therefore, the user should increase the DAC full-scale current by decreasing R

FS

by a factor of 1023/(940-64) to map the reduced-scale Y input code range to the same output current drive level.

Since these are the current drive levels for the video DACs they do not take into account the additional dc bias

for sync insertion when using video DAC mode. The voltage compliance outputs in Figure 5 assume termination

with a 37.5-Ω resistor.

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OUTPUT VOLTAGE

vs

FULL-SCALE RESISTANCE

1450

Full-Scale DAC Output

Current Adjustment at

1350

37.5-Ω DAC Termination

1250

1150

1050

950

850

750

650

550

450

350

1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8 6.3 6.8 7.3

R

– Full-Scale Resistance – kΩ

(FS)

Figure 5. V

vs R

FS

out

The user is free to connect another resistor value, but care should be taken not to exceed the maximum current

level on each of the DAC outputs as shown in the specifications section.

backward compatibility with the THS8133

power supply

The THS8135 is a functional superset to the THS8133 and is footprint compatible i.e. a board designed for the

THS8133 can also be used with the THS8135. Both devices come in the same package and have identical

pinouts. Only the power supply levels need to be adjusted as shown in Table 7.

Table 7. Power Supply Changes THS8133 vs THS8135

THS8133

5 V

THS8135

3.3 V

AV

DD

DV

3.3 V to 5 V

1.8 V

DD

device configuration

The THS8135 samples both M1 and M2 on the second rising edge of CLK after a transition on SYNC in video

modes. Depending on the polarity of the transition, M1 is interpreted as either M1_INT or BLK_INT. In the

THS8133 the M1 signal is not sampled but continuously interpreted, and is only interpreted as M1_INT. The

THS8133 does not offer a reduced-scale input code range configuration and therefore does not require

BLNK_INT.

Only when this additional functionality, which is typical for video systems, is desired, a small change in the

configuration of the device is required by supplying a dynamically changing signal on M1, generated in a similar

way as M2, as shown in Table 8.

Note that this backward compatibility is due to the selection of full-scale versus reduced-scale configurations

in Table 5. All configurations that have equal logic levels for BLNK_INT and M1_INT produce full-scale input

code range, which are compatible with the THS8133. This allows the use of a signal tied high or low on M1, as

on the THS8133, for these backward compatible full-scale configurations.

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DAC outputs

ThepositionoftheblankinglevelsintheTHS8135differsfromthepositionoftheblankinglevelsintheTHS8133.

This is to accommodate both full- and reduced-scale configurations on this device, while the THS8133 only

supported full-scale. When the DAC output is ac-coupled, as is typically the case, there is no change to the

output video waveform. Typically a clamp circuit at the receiving side will restore the signal to the proper dc level.

video DAC vs generic DAC modes

The THS8133 does not offer a generic DAC mode. The THS8135 uses only the same number of control signals

than the THS8133 but additionally introduces a generic video mode by specific use of a don’t care signal

combination of these control signals on the THS8133.

2

programming example for M2

Configuration of the device is normally static in a given application, although it is theoretically possible to

reconfigure the device during operation.

If M2_INT and INS3_INT need to be either low or high, the M2 pin is simply tied low or high. If M2_INT and

INS3_INT need to have different levels, these can be easily derived from the signal on the SYNC pin, as shown

in Table 8 and Figure 6.

Table 8. Generating M2 From SYNC

IN ORDER TO HAVE:

M2_INT

INS3_INT

APPLY TO M2:

L

H

L

... SYNC delayed by two CLK periods

... inverted SYNC delayed by two CLK periods

H

M1 can be generated similarly. Therefore, at most one inverter and two flip flops are needed to configure any

of the THS8135 modes using M1 and M2.

CLK

SYNC

M2

(= SYNC_delayed)

INS3_INT

if (M2 = SYNC_delayed) → M2_INT = L and INS3_INT = H

M2_INT

M2

(= Not SYNC_delayed)]

INS3_INT

M2_INT

if (M2 = NOT SYNC_delayed) → M2_INT = H and INS3_INT = L

Figure 6. Generating INS3_INT and M2_INT From M2

2

Programming M1 is analogous.

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CLK

T0

T1

T2

T3

T4

T5

T6

T7

T8

RCr(0)

RCr(1)

RCr(2)

RCr(3)

RCr(4)

RCr(5)

RCr(6)

RCr(7)

RCr(8)

GY(0)

GY(1)

GY(2)

GY(3)

GY(4)

GY(5)

GY(6)

GY(7)

GY(8)

BCb(0)

BCb(1)

BCb(2)

BCb(3)

BCb(4)

BCb(5)

BCb(6)

BCb(7)

BCb(8)

Data Path Latency = 7.5 CLK Cycles

RCr(0), GY(0), BCb(0) Registered

ARPr, AGY, ABPb Output

Corresponding to RCr(0), GY(0), BCb(0)

Figure 7. Input Format and Latency YCbCr 4:4:4 and GBR 4:4:4 Modes

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

BLANK

RCr[9:0]

GY[9:0]

First Registered Sample on RCr[9:0] after L

H on BLANK is Interpreted as Cb[9:0]

Cb(0)

Cr(0)

Y(1)

Cb(2)

Y(2)

Cr(2)

Y(3)

Cb(4)

Y(4)

Cr(4)

Y(5)

Cb(6)

Y(6)

Cr(6)

Y(7)

Cb(8)

Y(8)

Cr(8)

Cb(10)

Cr(10)

Y(0)

Y(9)

Y(10)

Y(11)

BCb[9:0]

Data Path Latency = 9.5 CLK Cycles

Cb(0), Y(0) Registered

ARPr, AGY, ABPb Output

Corresponding to Cr(0),Y(0), Cb(0)

Cr(0), Y(1) Registered

Figure 8. Input Format and Latency YCbCr 4:2:2 2x10-Bit Mode

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

CLK

BLANK

First Registered Sample on GY[9:0] after L

H on BLANK is Interpreted as Cb[9:0]

RCr[9:0]

GY[9:0]

BCb[9:0]

Cb(0)

Y(0)

Cr(0)

Y(2)

Cb(4)

Y(4)

Cr(4)

Y(6)

Cb(8)

Y(8)

Cr(8)

Y(10)

Data Path Latency = 10.5 CLK Cycles

Cr(0) Registered

Y(0) Registered

Cb(0) Registered

ARPr, AGY, ABPb Output

Corresponding to Cr(0),Y(0), Cb(0)

Figure 9. Input Format and Latency YCbCr 4:2:2 1x10-Bit Mode

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Figure 10 shows how to control the SYNC, SYNC_T, and BLANK signals to generate tri-level sync levels and

blanking at the DAC output in video mode. A bi-level (negative) sync can be generated similarly by avoiding the

positive transition on SYNC_T during SYNC low.

Note that on the THS8135 it is required to keep SYNC_T low outside the sync interval in order to avoid entering

the generic DAC mode.

CLK

t

s

t

h

SYNC

t

d(D)

SYNC_T

BLANK

D(0) D(1)

DATA[9:0]

Value

Corresponds

to D(0)

Figure 10. Sync and Blanking Generation

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage:

AV

DV

to AV

to DV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 2 V

DD

SS

Supply voltage: AV

Digital input voltage range to DV

Operating free-air temperature range, T

Storage temperature range, T

to DV , AV to DV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to 0.5 V

DD

SS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to DV

+ 0.5 V

SS

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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recommended operating conditions over operating free-air temperature range, T

A

power supply

MIN NOM

MAX

UNIT

AV

DD

3

3.3

1.8

3.6

2

Supply voltage

V

DV

1.65

DD

digital and reference inputs

MIN NOM

MAX

UNIT

V

High-level input voltage, V

IH

1.2

DV

DD

0.7

Low-level input voltage, V

DV

V

IL

SS

0

Clock frequency, f

clk

240

MHz

Clock high pulse duration, t

40%

60%

CLK

period

w(CLKH)

Clock low pulse duration, t

40%

60%

CLK

period

w(CLKL)

FSADJ resistor, R , See Note 1

FS

3.8

kΩ

NOTE 1:

R

should be chosen such that the maximum full-scale DAC output current (I ) does not exceed their maximum stated levels. This

FS

yields the nominal output voltage compliance at the nominal load termination of 37.5 Ω.

electrical characteristics over recommended operating conditions with f

= 240 MSPS and use

CLK

of internal reference voltage (unless otherwise noted) V

termination

, with R = R

and 37.5-Ω load

REF

FS

FS(nom)

power supply (1 MHz, –1 dBFS digital sine simultaneously applied to all three channels)

PARAMETER

TEST CONDITIONS

MIN

89

TYP

95

MAX

100

80

UNIT

RGB

YCbCr

71

76

IAV

DD

Operating supply current, analog

Operating supply current, digital

Power dissipation

Generic (700 mV)

RGB

63

66

69

mA

14.5

15.1

15.7

12.7

15.7

350

280

252

100

69

AV

DD

= 3.3 V,

= 1.8 V,

YCbCr

11.7 12.15

IDV

DD

DV

DD

CLK = 80 MSPS

Generic (700 mV) 14.64

15.1

338

270

245

95

RGB

328

262

237

89

YCbCr

P

D

mW

Generic (700 mV)

RGB

IAV

DD

Operating supply current, analog

Operating supply current, digital

Power dissipation

Generic (700 mV)

RGB

63

66

mA

AV

DD

= 3.3 V,

= 1.8 V,

38

40

41

IDV

DV

DD

Generic (700 mV)

RGB

38

40

41.1

394

298

CLK = 240 MSPS

373

281

384

290

114

16

P

D

mW

Generic (700 mV)

IAV

IDV

Operating supply current, analog

Operating supply current, digital

Power dissipation

DD

AV

DD

= 3.3 V,

= 1.8 V,

mA

DV

DD

Generic (1.3 V)

DD

CLK = 80 MSPS

P

D

405

114

41

mW

IAV

IDV

Operating supply current, analog

Operating supply current, digital

Power dissipation

DD

AV

DD

= 3.3 V,

= 1.8 V,

mA

DV

DD

CLK = 240 MSPS

P

D

450

mW

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electrical characteristics over recommended operating conditions with f

= 240 MSPS and use

CLK

of internal reference voltage V

, with R = R

(unless otherwise noted) (continued)

REF

FS

FS(nom)

digital inputs—dc characteristics

PARAMETER

TEST CONDITIONS

= 3.3 V, DV = 1.8 V,

MIN

TYP

MAX

1

UNIT

I

High-level input current

Low-level input current

IH

AV

DD

–1

IL

µA

Digital inputs and CLK at 0 V for I

Digital inputs and CLK at 2 V for I

;

IL

IH

Low-levelinput current, CLK and I

High-level input current, CLK

IH(CLK)

I

–1

1

IL(CLK)

C

Input capacitance

T

A

= 25_C

5

pF

ns

ps

I

t

s

Data and control inputs setup time

Data and control inputs hold time

2

t

h

500

RGB and YCbCr 4:4:4

YCbCr 4:2:2 2 x 10 bit

YCbCr 4:2:2 1 x 10 bit

7.5

9.5

Digital process delay from first registered

color component of pixel

CLK

periods

t

d(D)

†

10.5

†

This parameter is assured by design. The digital process delay is defined as the number of CLK cycles required for the first registered color

component of a pixel, starting from the time of registering it on the input bus, to propagate through all processing and appear at the DAC output

drivers. The remaining delay through the IC is the analog delay t

of the analog output drivers.

d(A)

analog (DAC) outputs

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DAC resolution

10

Bits

–1.1/

0.9

–2/

1.5

Static, best-fit, sync-on–all, video mode, RGB full-scale

Static, best-fit, sync-on-all, video mode,

RGB ITU.R–BT601

–1.2/

0.8

–2/

1.5

INL

Integral nonlinearity

LSB

–1.61/

0.94

–2/

1.5

Static, best fit, generic mode, 1.3 V

Static, sync-on-all, video mode, RGB full-scale

±0.4

±0.5

±1

Static, sync-on-all, video mode, RGB ITU.R–BT601

DNL

Differential nonlinearity

–0.32/

0.24

Static, generic mode, 1.3 V

f = DC, See Note 2

Power supply ripple rejection

ratio of DAC output (full scale)

PSRR

38.5

dB

f = 1 MHz

See Note 3

–63

–39

1.15

284

XTALK

Crosstalk between channels

f = 30 MHz

V

refo

Voltage reference output

VREF output resistance

1.13

1.16

294

V

R

276.5

Ω

R

Video mode,

–2%

–3%

1.8%

2.8%

0.7

2%

3%

RGB full-scale

CLK = 80 MSPS, See Note 4

Video mode,

K

Imbalance between DACs

IMBAL

RGB ITU-R.BT601

Video mode,

RGB full-scale

DAC output compliance voltage

(video only)

Video mode, RGB

ITU-R.BT601

V

OC

See Note 5

V

0.817

1.3

Generic mode

NOTES: 2. PSRRismeasuredwitha0.1µFcapacitorbetweentheCOMPandAVDDpin;witha0.1–µFcapacitorconnectedbetweentheVREF

pin and AVSS. The ripple amplitude is within the range 100 mVp–p to 500 mVp–p with the DAC output set to full scale and a

double-terminated 75 Ω (= 37.5 Ω) load. PSRR is defined as 20 x log(ripple voltage at DAC output/ripple voltage at AVDD input).

Limits from characterization only.

3. Crosstalk spec applies to each possible pair of the three DAC outputs. Limits are from characterization only.

4. The imbalance between DACs applies to all possible pairs of the three DACs.

5. Values at R =R

FS FS(nom)

; limits from characterization only.

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analog (DAC) outputs (continued)

PARAMETER

TEST CONDITIONS

AGY

MIN

27

TYP

28

MAX

29.3

19.5

32.0

32.3

32.1

22.5

4.2

UNIT

Video mode, full-scale RGB,

sync-on-all

ABPb and ARPr

AGY

27

28

27

28

Video mode, full-scale YCbCr,

sync-on-all

ABPb and ARPr

AGY

18 18.67

30 31.18

20 21.39

I

CLK = 80 MSPS, See Note 6

mA

FS

Video mode, ITU-R.BT601RGB,

sync-on-all

ABPb and ARPr

AGY

Video mode, ITU-R.BT601

YCbCr, sync-on-all

ABPb and ARPr

t

DAC output current rise time

DAC output current fall time

CLK = 80 MSPS, 10 to 90% of full-scale

3.2

3.5

ns

RDAC

4.2

FDAC

Measured from CLK = V

transition, See Note 7

to 50% of full-scale

IH(min)

t

Analog output delay

4

ns

d(A)

S

Measured from 50% of full scale transition on output to

output settling, within 2%, See Note 8

t

Analog Output Settling Time

15

SFDR

BW

Spurious-free dynamic range

Bandwidth

1 MHz, –1 dBFS digital sine input

55

50

dB

1 dB

MHz

3 dB

100

25

E

glitch

Glitch energy

Full-scale code transition at 240 MSPS

pVs

NOTES: 6. Values at R =R

.

FS FS(nom)

7. This value excludes the digital process delay, t

Limit are from characterization only.

8. Limit from characterization only. Measured on Y channel with other channels not driven.

D(D).

400

390

380

370

360

350

340

330

320

310

300

0

50

100

150

200

250

300

f – Frequency – MHz

Figure 11. Power vs Clock Frequency, RGB mode, 1-MHz Input Tone on All Channels

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600

500

400

300

200

100

0

50

100

150

200

250

300

f – Frequency – MHz

Figure 12. Power vs Clock Frequency, Generic DAC Mode 1.3-V Output,

Full-Scale Input Toggle on All Channels

0.5

0.4

0.3

0.2

0.1

–

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

1

76

151 226 301 376 451 526 601 676 751 826 901 976 1051

Input Code

Figure 13. DNL, Generic DAC Mode (1.3-V Output Compliance)

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1.5

1.0

0.5

0.0

–0.5

–1.0

–1.5

1

103

205

307

409

511

613

715

817

919

1021

Input Code

Figure 14. Best-Fit INL, Generic DAC Mode (1.3-V Output Compliance)

0

–1

–2

–3

–4

–5

–6

0

10

20

30

40

50

60

70

80

90 100 110 120 130 140 150

f – Frequency – MHz

Figure 15. Amplitude Response vs Input Frequency at 240 MSPS

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MECHANICAL DATA

PHP (S-PQFP-G48)

PowerPAD PLASTIC QUAD FLATPACK

0,27

M

0,50

36

0,08

0,17

25

37

24

Thermal Pad

(see Note D)

48

13

0,13 NOM

1

12

5,50 TYP

Gage Plane

7,20

SQ

6,80

0,25

9,20

8,80

SQ

0,15

0,05

0°–ā7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4146927/A 01/98

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.

This pad is electrically and thermally connected to the backside of the die and possibly selected leads.

E. Falls within JEDEC MS-026

PowerPAD is a trademark of Texas Instruments Incorporated.

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

30-Mar-2005

PACKAGING INFORMATION

Orderable Device

THS8135PHP

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

HTQFP

PHP

48

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

THS8135PHPG4

HTQFP

PHP

48

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

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Use of such information may require a license from a third party under the patents or other intellectual property

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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

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Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

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