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  • TLC3541IDR图
  • 深圳市恒益昌科技有限公司

     该会员已使用本站6年以上
  • TLC3541IDR 现货库存
  • 数量4500 
  • 厂家Texas Instruments 
  • 封装8-SOIC(0.154 
  • 批号25+ 
  • 原装现货 特价销售
  • QQ:3336148967QQ:3336148967 复制
    QQ:974337758QQ:974337758 复制
  • 0755-82723761 QQ:3336148967QQ:974337758
  • TLC3541IDR图
  • 深圳市广百利电子有限公司

     该会员已使用本站6年以上
  • TLC3541IDR 现货库存
  • 数量18500 
  • 厂家TI(德州仪器) 
  • 封装SOIC-8_150mil 
  • 批号23+ 
  • ★★全网低价,原装原包★★
  • QQ:1483430049QQ:1483430049 复制
  • 0755-83235525 QQ:1483430049
  • TLC3541IDR图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • TLC3541IDR 现货库存
  • 数量26800 
  • 厂家TEXAS INSTRUMENTS 
  • 封装22+ 
  • 批号8SOIC 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:1435424310QQ:1435424310 复制
  • 0755-84507451 QQ:1435424310
  • TLC3541IDR图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • TLC3541IDR 现货库存
  • 数量150 
  • 厂家TEXAS INSTRUMENTS 
  • 封装8SOIC 
  • 批号 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:2881512844QQ:2881512844 复制
  • 075584507705 QQ:2881512844
  • TLC3541IDR图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • TLC3541IDR
  • 数量85000 
  • 厂家TI/德州仪器 
  • 封装SOIC 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495753QQ:2881495753 复制
  • 0755-23605827 QQ:2881495753
  • TLC3541IDR图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • TLC3541IDR
  • 数量13880 
  • 厂家TI/德州仪器 
  • 封装SOIC-8_150mil 
  • 批号21+ 
  • 公司只售原装 支持实单
  • QQ:2881495751QQ:2881495751 复制
  • 0755-88917743 QQ:2881495751
  • TLC3541IDR图
  • 深圳市旺能芯科技有限公司

     该会员已使用本站4年以上
  • TLC3541IDR
  • 数量15000 
  • 厂家TI/德州仪器 
  • 封装SOIC 
  • 批号22+ 
  • 深圳全新原装库存现货
  • QQ:2881495751QQ:2881495751 复制
  • 13602549709 QQ:2881495751
  • TLC3541IDR图
  • 深圳市龙腾新业科技有限公司

     该会员已使用本站17年以上
  • TLC3541IDR
  • 数量10000 
  • 厂家TI/德州仪器 
  • 封装8-SOIC 
  • 批号23+ 
  • 进口原装现货
  • QQ:562765057QQ:562765057 复制
    QQ:370820820QQ:370820820 复制
  • 0755-84509636 QQ:562765057QQ:370820820
  • TLC3541IDR图
  • 千层芯半导体(深圳)有限公司

     该会员已使用本站9年以上
  • TLC3541IDR
  • 数量44300 
  • 厂家TI 
  • 封装SOP8 
  • 批号2019+ 
  • TI一级代理专营品牌绝对进口原装假一赔十
  • QQ:2685694974QQ:2685694974 复制
    QQ:2593109009QQ:2593109009 复制
  • 0755-83978748,0755-23611964,13760152475 QQ:2685694974QQ:2593109009
  • TLC3541IDR图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站16年以上
  • TLC3541IDR
  • 数量6500 
  • 厂家TI 
  • 封装SOP8 
  • 批号25+ 
  • 全新原装公司现货销售
  • QQ:867789136QQ:867789136 复制
    QQ:1245773710QQ:1245773710 复制
  • 0755-82723761 QQ:867789136QQ:1245773710
  • TLC3541IDRG4图
  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • TLC3541IDRG4
  • 数量6000 
  • 厂家TI 
  • 封装SOP8 
  • 批号25+ 
  • 全新原装现货,欢迎询购!
  • QQ:867789136QQ:867789136 复制
    QQ:1245773710QQ:1245773710 复制
  • 0755-82772189 QQ:867789136QQ:1245773710
  • TLC3541IDR图
  • 深圳市和诚半导体有限公司

     该会员已使用本站11年以上
  • TLC3541IDR
  • 数量5600 
  • 厂家TI 
  • 封装SOIC 
  • 批号23+ 
  • 只做原装正品,深圳现货
  • QQ:2276916927QQ:2276916927 复制
    QQ:1977615742QQ:1977615742 复制
  • 18929336553 QQ:2276916927QQ:1977615742
  • TLC3541IDR图
  • 深圳市中杰盛科技有限公司

     该会员已使用本站14年以上
  • TLC3541IDR
  • 数量12000 
  • 厂家TI 
  • 封装SOIC-8 
  • 批号24+ 
  • 【原装优势★★★绝对有货】
  • QQ:409801605QQ:409801605 复制
  • 0755-22968359 QQ:409801605
  • TLC3541IDR图
  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • TLC3541IDR
  • 数量4052 
  • 厂家TI/德州仪器 
  • 封装NA/ 
  • 批号23+ 
  • 原装现货,当天可交货,原型号开票
  • QQ:3007977934QQ:3007977934 复制
    QQ:3007947087QQ:3007947087 复制
  • 0755-82546830 QQ:3007977934QQ:3007947087
  • TLC3541IDR图
  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
  • TLC3541IDR
  • 数量30000 
  • 厂家TI/德州仪器 
  • 封装SOIC 
  • 批号23+ 
  • 只做原装现货假一罚十
  • QQ:2103443489QQ:2103443489 复制
    QQ:2924695115QQ:2924695115 复制
  • 0755-82702619 QQ:2103443489QQ:2924695115
  • TLC3541IDR图
  • 深圳市华斯顿电子科技有限公司

     该会员已使用本站16年以上
  • TLC3541IDR
  • 数量24661 
  • 厂家TI 
  • 封装SOIC 
  • 批号2023+ 
  • 绝对原装全新正品现货/优势渠道商、原盘原包原盒
  • QQ:364510898QQ:364510898 复制
    QQ:515102657QQ:515102657 复制
  • 0755-83777708“进口原装正品专供” QQ:364510898QQ:515102657
  • TLC3541IDR图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • TLC3541IDR
  • 数量16851 
  • 厂家TI/德州仪器 
  • 封装TI-2019 
  • 批号23+ 
  • 全新原装正品现货热卖
  • QQ:2885348339QQ:2885348339 复制
    QQ:2885348317QQ:2885348317 复制
  • 0755-82519391 QQ:2885348339QQ:2885348317
  • TLC3541IDR图
  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
  • TLC3541IDR
  • 数量802 
  • 厂家TI 
  • 封装SOIC 
  • 批号22+ 
  • ★只做原装★正品现货★原盒原标★
  • QQ:2355507165QQ:2355507165 复制
    QQ:2355507162QQ:2355507162 复制
  • 86-0755-83210909 QQ:2355507165QQ:2355507162
  • TLC3541IDR图
  • 深圳市惊羽科技有限公司

     该会员已使用本站11年以上
  • TLC3541IDR
  • 数量6328 
  • 厂家TI-德州仪器 
  • 封装SOP-8.贴片 
  • 批号▉▉:2年内 
  • ▉▉¥45.2元一有问必回一有长期订货一备货HK仓库
  • QQ:43871025QQ:43871025 复制
  • 131-4700-5145---Q-微-恭-候---有-问-秒-回 QQ:43871025
  • TLC3541IDR?图
  • 深圳市晶美隆科技有限公司

     该会员已使用本站14年以上
  • TLC3541IDR?
  • 数量16300 
  • 厂家TI 
  • 封装SOP8 
  • 批号23+ 
  • 全新原装正品现货
  • QQ:2885348317QQ:2885348317 复制
    QQ:2885348339QQ:2885348339 复制
  • 0755-83209630 QQ:2885348317QQ:2885348339
  • TLC3541IDR图
  • 深圳市硅诺电子科技有限公司

     该会员已使用本站8年以上
  • TLC3541IDR
  • 数量13879 
  • 厂家TI 
  • 封装SOP8 
  • 批号17+ 
  • 原厂指定分销商,有意请来电或QQ洽谈
  • QQ:1091796029QQ:1091796029 复制
    QQ:916896414QQ:916896414 复制
  • 0755-82772151 QQ:1091796029QQ:916896414
  • TLC3541IDR图
  • 深圳市宗天技术开发有限公司

     该会员已使用本站10年以上
  • TLC3541IDR
  • 数量2500 
  • 厂家TI 
  • 封装SOIC 
  • 批号21+ 
  • 宗天技术 原装现货/假一赔十
  • QQ:444961496QQ:444961496 复制
    QQ:2824256784QQ:2824256784 复制
  • 0755-88601327 QQ:444961496QQ:2824256784
  • TLC3541IDR图
  • 万三科技(深圳)有限公司

     该会员已使用本站2年以上
  • TLC3541IDR
  • 数量660000 
  • 厂家Texas Instruments(德州仪器) 
  • 封装8-SOIC (0.154 
  • 批号3.90mm Width) 
  • QQ:3008961398QQ:3008961398 复制
  • 0755-21006672 QQ:3008961398
  • TLC3541IDR图
  • 昂富(深圳)电子科技有限公司

     该会员已使用本站4年以上
  • TLC3541IDR
  • 数量72282 
  • 厂家TI/德州仪器 
  • 封装N/A 
  • 批号23+ 
  • 一站式BOM配单,短缺料找现货,怕受骗,就找昂富电子.
  • QQ:GTY82dX7
  • 0755-23611557【陈妙华 QQ:GTY82dX7
  • TLC3541IDR图
  • 深圳市驰天熠电子有限公司

     该会员已使用本站1年以上
  • TLC3541IDR
  • 数量33560 
  • 厂家TI(德州仪器) 
  • 封装SOIC-8 
  • 批号23+ 
  • 全新原装,优势价格,支持配单
  • QQ:3003795629QQ:3003795629 复制
    QQ:534325024QQ:534325024 复制
  • 86-15802056765 QQ:3003795629QQ:534325024
  • TLC3541IDR图
  • 深圳市芯柏然科技有限公司

     该会员已使用本站7年以上
  • TLC3541IDR
  • 数量26800 
  • 厂家TEXAS INSTRUMENTS 
  • 封装8SOIC 
  • 批号22+ 
  • 授权代理直销,原厂原装现货,假一罚十,特价销售
  • QQ:287673858QQ:287673858 复制
  • 0755-82533534 QQ:287673858
  • TLC3541IDRG4图
  • 深圳市勤思达科技有限公司

     该会员已使用本站14年以上
  • TLC3541IDRG4
  • 数量55700 
  • 厂家TI 
  • 封装SOIC-8 
  • 批号 
  • 全选原装正品 长期现货库存供应
  • QQ:2881239443QQ:2881239443 复制
  • 0755-83268779 QQ:2881239443
  • TLC3541IDR图
  • 深圳市诚达吉电子有限公司

     该会员已使用本站2年以上
  • TLC3541IDR
  • 数量7008 
  • 厂家TEXAS INSTRUMENTS 
  • 封装8SOIC 
  • 批号2024+ 
  • 原装正品 一手现货 假一赔百
  • QQ:2881951980QQ:2881951980 复制
  • 15873513267 QQ:2881951980
  • TLC3541IDR图
  • 深圳市特拉特科技有限公司

     该会员已使用本站2年以上
  • TLC3541IDR
  • 数量15000 
  • 厂家TI 
  • 封装SOIC 
  • 批号22+ 
  • 一级代理,公司优势产品,可开增值票
  • QQ:709809857QQ:709809857 复制
  • 0755-82531732 QQ:709809857
  • TLC3541IDR图
  • 深圳市双微电子科技有限公司

     该会员已使用本站10年以上
  • TLC3541IDR
  • 数量5678 
  • 厂家TI 
  • 封装SOP8 
  • 批号20+ 
  • 询货请加QQ 全新原装 现货库存
  • QQ:1965209269QQ:1965209269 复制
    QQ:1079402399QQ:1079402399 复制
  • 15889219681 QQ:1965209269QQ:1079402399
  • TLC3541IDR图
  • 万三科技(深圳)有限公司

     该会员已使用本站2年以上
  • TLC3541IDR
  • 数量6500000 
  • 厂家N/A 
  • 封装原厂原装 
  • 批号22+ 
  • 万三科技 秉承原装 实单可议
  • QQ:3008962483QQ:3008962483 复制
  • 0755-23763516 QQ:3008962483
  • TLC3541IDR图
  • 深圳市华兴微电子有限公司

     该会员已使用本站16年以上
  • TLC3541IDR
  • 数量5000 
  • 厂家TI 
  • 封装N/A 
  • 批号23+ 
  • 只做进口原装QQ询价,专营射频微波十五年。
  • QQ:604502381QQ:604502381 复制
  • 0755-83002105 QQ:604502381
  • TLC3541IDR图
  • 深圳德田科技有限公司

     该会员已使用本站7年以上
  • TLC3541IDR
  • 数量
  • 厂家新年份 
  • 封装12000 
  • 批号 
  • 原装正品现货,可出样品!!!
  • QQ:229754250QQ:229754250 复制
  • 0755-83254070 QQ:229754250
  • TLC3541IDR图
  • 深圳市捷立辉科技有限公司

     该会员已使用本站10年以上
  • TLC3541IDR
  • 数量69896 
  • 厂家TI/德州仪器 
  • 封装SOP8 
  • 批号21+ 
  • 绝对原装现货,公司真实库存
  • QQ:1803576909QQ:1803576909 复制
  • -0755-82792948 QQ:1803576909
  • TLC3541IDR图
  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
  • TLC3541IDR
  • 数量150 
  • 厂家TEXAS INSTRUMENTS 
  • 封装8SOIC 
  • 批号 
  • 新到现货、一手货源、当天发货、bom配单
  • QQ:2881512844QQ:2881512844 复制
  • 075584507705 QQ:2881512844
  • TLC3541IDR图
  • 深圳市炎凯科技有限公司

     该会员已使用本站7年以上
  • TLC3541IDR
  • 数量1602 
  • 厂家TI 
  • 封装SOIC 
  • 批号24+ 
  • 原装现货
  • QQ:354696650QQ:354696650 复制
    QQ:2850471056QQ:2850471056 复制
  • 0755-89587732 QQ:354696650QQ:2850471056
  • TLC3541IDR图
  • 深圳市欧瑞芯科技有限公司

     该会员已使用本站11年以上
  • TLC3541IDR
  • 数量10000 
  • 厂家TI(德州仪器) 
  • 封装8-SOIC(0.154,3.90mm 宽) 
  • 批号23+/24+ 
  • 绝对原装正品,可开13%专票,欢迎采购!!!
  • QQ:3354557638QQ:3354557638 复制
    QQ:3354557638QQ:3354557638 复制
  • 18565729389 QQ:3354557638QQ:3354557638

产品型号TLC3541IDR的概述

TLC3541IDR 概述 TLC3541IDR 是一款高性能的模拟比较器,旨在执行快速而精确的电压比较功能。该芯片由德州仪器(Texas Instruments, TI)制造,适用于多种工业应用,如自动控制系统、信号处理和电池监测等。TLC3541IDR 的设计考虑到了低功耗和高速度,使其在现代电子设备中具有广泛的应用场景。 详细参数 TLC3541IDR 的主要参数如表所示: - 电源电压范围:5V至36V - 输入电压范围:-0.3V至Vcc+0.3V - 输入失调电压:最大 2mV - 增益带宽积:1.5MHz - 响应时间:最大 350ns - 低功耗:静态电流典型值为 100µA - 输入阻抗:高输入阻抗,最低可达 250kΩ - 输出类型:推挽输出 - 工作温度范围:-40°C 至 125°C - 封装类型:SOIC-8 TLC3541IDR 的低输入失调电压使其在精密应...

产品型号TLC3541IDR的Datasheet PDF文件预览

SLAS345 − DECEMBER 2001  
ꢄ ꢈꢉꢇ ꢁꢊ ꢋ ꢌꢊ ꢋ ꢍꢎꢇ ꢆ ꢅ ꢈꢏꢐ ꢀꢇ ꢑ ꢒ ꢒ ꢈꢓꢔꢌ ꢔ  
ꢔꢍꢎ ꢐ ꢕꢁ ꢕꢖ ꢕꢁ ꢊꢗ ꢈꢀꢊ ꢈꢘꢐ ꢗ ꢐꢀꢕꢁ ꢂꢊ ꢖꢉꢍ ꢎꢀ ꢍꢎꢔ ꢋ ꢐꢀ ꢙ ꢕꢚꢀꢊ ꢈꢌꢊ ꢋ ꢍꢎ ꢘꢊ ꢋ ꢖ  
FEATURES  
APPLICATIONS  
D
D
D
D
D
D
D
D
200-KSPS Sampling Rate  
Built-In Conversion Clock  
D
D
D
D
ATE System  
Industrial Process Control  
Measurement  
INL: 1 LSB Max  
DNL: 1 LSB Max  
Motor Control  
SINAD = 81.5 dB, SFDR = 95 dB  
THD = 94 dB at 15 kHz f , 200 KSPS  
DESCRIPTION  
in  
SPI/DSP-Compatible Serial Interfaces With  
SCLK Input up to 15 MHz  
The TLC3541 and TLC3545 are a family of high  
performance, 14-bit, low power, miniature CMOS  
analog-to-digital converters (ADCs). These devices  
operate from a single 5-V supply. Devices are available  
with single, dual, or single pseudo-differential inputs. All  
of these devices have a chip select (CS), serial clock  
(SCLK), and serial data output (SDO) that provides a  
direct 3-wire interface to the serial port of most popular  
host microprocessors (SPI interface). When interfaced  
with a DSP, a frame sync signal (FS) is used to indicate  
the start of a serial data frame on either pin 1 (CS) or pin  
7 (FS) for the TLC3541. The TLC3545 ADC connects  
to the DSP via pin 1 only (CS).  
Single 5-V Supply  
Rail-to-Rail Analog Input With 500 kHz BW  
Two Input Options Available:  
− TLC3541 − Single Channel Input  
− TLC3545 − Single Channel,  
Pseudo-Differential Input  
D
D
(TLC3541) Optimized DSP Interface −  
Requires FS Input Only  
Low Power With Auto-Power Down  
− Operating Current: 3.5 mA  
− Auto-Powerdown Current: 5 µA  
Pin Compatible 12-/14-/16-Bit Family in 8-Pin  
SOIC and MSOP Packages  
The TLC3541 and TLC3545 are designed to operate  
with low power consumption. The power saving feature  
is further enhanced with an auto-power down mode.  
This product family features a high-speed serial link to  
modern host processors with an external SCLK up to  
15 MHz. Both families use a built-in oscillator as the  
conversion clock, providing a 2.67 µs maximum  
conversion time.  
D
TLC3541  
D OR DGK Package  
(TOP VIEW)  
TLC3545  
D OR DGK Package  
(TOP VIEW)  
CS  
REF  
GND  
AIN  
1
2
3
4
8
7
6
5
SDO  
FS  
CS  
REF  
1
2
3
4
8
7
6
5
SDO  
SCLK  
V
GND  
DD  
V
DD  
SCLK  
AIN(+)  
AIN(−)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢀꢦ  
Copyright 2001, Texas Instruments Incorporated  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ  
1
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SLAS345 − DECEMBER 2001  
AVAILABLE OPTIONS  
PACKAGED DEVICES  
T
A
8-MSOP (DGK)  
8-SOIC (D)  
TLC3541ID  
TLC3545ID  
TLC3541IDGK (PKG Code = AMG)  
TLC3545IDGK (PKG Code = AMM)  
−40°C to 85°C  
functional block diagram  
TLC3541  
TLC3545  
V
DD  
V
DD  
REF  
AIN  
REF  
AIN (+)  
LOW POWER  
SAR ADC  
LOW POWER  
SAR ADC  
S/H  
SDO  
S/H  
SDO  
AIN (−)  
OSC  
OSC  
Conversion  
Clock  
Conversion  
Clock  
SCLK  
CS  
CONTROL  
LOGIC  
CONTROL  
LOGIC  
SCLK  
CS  
FS  
GND  
GND  
2
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SLAS345 − DECEMBER 2001  
Terminal Functions  
TLC3541 single channel unipolar ADCs  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
NO.  
4
AIN  
CS  
I
I
Analog input channel  
1
Chip select. A high-to-low transition on the CS input removes SDO from a high-impedance state within a  
maximum delay time. If the TLC3541 is attached to a dedicated TMS320 DSP serial port using the FS input,  
CS can be grounded.  
FS  
7
3
8
I
I
DSP frame sync input. Indication of a start of a serial data frame. A low-to-high transition removes SDO from  
the high-impedance state and the MSB is presented. Tie this pin to V  
DD  
if not used.  
GND  
SDO  
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to  
GND.  
O
The 3-state serial data output for the A/D conversion result. SDO is kept in the high-impedance state when  
CS is high. The output format is MSB first. Remaining data bits are presented on the rising edge of SCLK.  
When FS is not active (FS = 1 at the falling edge of CS): The MSB is presented on the SDO pin on the falling  
edge of CS after a maximum delay time. Data is valid on each falling edge of SCLK until all data is read.  
When FS is active (FS = 0 at the falling edge of CS): The MSB is presented to the SDO output on the rising  
edge of FS. Data is valid on the falling edge SCLK and changes on the rising edge SCLK (this is typically  
used with an active FS from a DSP).  
SDO returns to the high-impedance state after the 17th rising edge on SCLK. If a 17th SCLK cycle is not  
presented, as is the case when using an SPI host, SDO returns to the high-impedance state on the rising  
edge of CS.  
SCLK  
REF  
5
2
6
I
I
I
Serial clock. This terminal receives the serial SCLK from the host processor.  
External voltage reference input  
V
DD  
Positive supply voltage  
TLC3545 single channel pseudo-differential ADCs  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
AIN0 (+)  
NO.  
4
I
I
I
Positive analog input for the TLC3545.  
Inverted analog input for the TLC3545.  
AIN1 (−)  
CS  
5
1
Chip select. A high-to-low transition on CS removes SDO from the high-impedance state within a maximum  
delay time. The CS input can be connected to a DSP frame sync (FS) output when a dedicated TMS320 DSP  
serial port is used.  
GND  
SDO  
3
8
I
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to  
GND.  
O
The 3-state serial data output for the A/D conversion result. SDO is kept in the high-impedance state when  
CS is high and presents output data after the CS falling edge until the LSB is presented. The output format is  
MSB first. The remaining data bits are presented on the rising edge of SCLK. Output data is valid on each  
falling edge of SCLK until all data is read. SDO returns to the high-impedance state after the 17th rising edge  
on SCLK. If a 17th SCLK cycle is not presented, as is the case when using an SPI host, SDO returns to the  
high-impedance state on the rising edge of CS.  
SCLK  
REF  
7
2
6
I
I
I
Serial clock. This terminal receives the serial SCLK from the host processor.  
External voltage reference input  
V
DD  
Positive supply voltage  
3
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SLAS345 − DECEMBER 2001  
absolute maximum ratings over operating free-air temperature (unless otherwise noted)  
Supply voltage, GND to V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5V  
DD  
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V +0.3 V  
Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V +0.3 V  
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V +0.3 V  
DD  
DD  
DD  
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C  
J
Operating free-air temperature range: T (I suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C  
A
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
stg  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
recommended operating conditions  
MIN NOM  
MAX  
5.5  
UNIT  
V
Supply voltage, V  
Frequency, SCLK  
4.5  
5
DD  
V
DD  
V
DD  
V
DD  
= 4.5 V to 5.5 V  
= 4.5 V to 5.5 V  
= 4.5 V to 5.5 V  
100  
15000  
97  
kHz  
ps  
Tolerable clock jitter, SCLK  
Aperature jitter  
100  
ps  
External reference voltage input, V  
External reference voltage input, V  
REF  
4
100  
20  
V
V
REF  
DD  
V
DD  
V
DD  
V
DD  
= 5 V, CS = 1, SCLK = 0  
MΩ  
kΩ  
mA  
V
REF  
input impedance  
= 5 V, CS = 0, SCLK = 15 MHz  
= V = 4.5 V, CS=0, SCLK = 15 MHz  
25  
External reference input current  
0.02  
1
REF  
AIN, AIN(+)  
AIN(−)  
0
−0.2  
2.1  
V
DD  
0.2  
Analog input voltage  
V
High level control input voltage, V  
V
V
IH  
Low level control input voltage, V  
IL  
0.8  
85  
Operating free-air temperature, T  
TLC3541/45I  
−40  
°C  
A
4
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SLAS345 − DECEMBER 2001  
electrical characteristics over recommended operating free-air temperature range,  
= 5 V, V = 4.096 V, SCLK frequency = 15 MHz (unless otherwise noted)  
V
DD  
REF  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
V
V
OH  
High-level output voltage  
Low-level output voltage  
V
V
V
V
= 4.5 V,  
= 4.5 V  
I
OH  
= −0.2 mA  
= 0.8 mA  
3.9  
DD  
V
OL  
I
0.4  
2.5  
V
DD  
OL  
= V  
DD  
,
CS = V  
1
−1  
Off-state output current  
(high-impedance-state)  
O
O
DD  
DD  
I
µA  
OZ  
= 0,  
CS = V  
−2.5  
2.5  
I
I
I
High-level input current  
Low-level input current  
Operating supply current  
V = V  
I DD  
0.005  
−0.005  
µA  
µA  
IH  
V = 0  
I
2.5  
IL  
CS at 0 V,  
V
DD  
= 4.5 V to 5.5 V  
3.5  
mA  
CC  
For all digital inputs, 0V 0.3 V  
I
I
Power-down supply current  
or V V  
DD  
DD  
Selected channel at V  
− 0.3 V, SCLK=V  
= 4.5 V to 5.5 V  
,
3
5
µA  
µA  
CC(PD)  
I
DD  
V
1
−1  
Selected analog input channel leakage  
current  
DD  
Selected channel at 0 V  
Analog inputs  
11  
20  
14  
C
Input capacitance  
Input resistance  
pF  
i
Control Inputs  
25  
Z
V
DD  
= 5.5 V  
500  
i
ac specifications (TLC3541/45)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
81.5  
82  
MAX  
UNIT  
dB  
SINAD Signal-to-noise ratio +distortion  
f = 15 kHz at 200 KSPS  
I
SNR  
Signal-to-noise ratio  
f = 15 kHz at 200 KSPS  
dB  
I
TLC3541  
TLC3545  
f = 15 kHz at 200 KSPS  
−94  
−94  
13.2  
−95  
−95  
1
−87  
−89  
I
THD  
Total harmonic distortion  
Effective number of bits  
dB  
f = 15 kHz at 200 KSPS  
I
ENOB  
f = 15 kHz at 200 KSPS  
I
Bits  
TLC3541  
TLC3545  
f = 15 kHz at 200 KSPS  
I
−87  
−89  
SFDR  
Spurious free dynamic range  
dB  
f = 15 kHz at 200 KSPS  
I
Full-power bandwidth, −3 dB, analog input  
Full-power bandwidth, −1 dB, analog input  
MHz  
kHz  
dB  
500  
Crosstalk  
0.25 LSB  
80  
dc specifications (TLC3541/45)  
PARAMETER  
TEST CONDITIONS  
MIN TYP  
MAX  
1
UNIT  
LSB  
LSB  
INL  
Integral linearity error (see Note 1)  
Differential linearity error  
−1  
DNL  
−1  
−3.5  
−1  
0.75  
1
TLC3541  
3.5  
1
E
Offset error (see Note 2)  
Gain error (see Note 2)  
mV  
mV  
O
G
TLC3545  
TLC3541  
TLC3545  
−2  
2
E
−1.8  
1.8  
All typical values are at V  
DD  
= 5 V, T = 25°C.  
A
NOTES: 1. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.  
2. Zero error is the difference between 0000h and the converted output for zero input voltage: full-scale error is the difference between  
ideal full-scale and the converted output for full-scale input voltage.  
5
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SLAS345 − DECEMBER 2001  
timing requirements, V  
= 5 V, V  
= 4.096 V, SCLK frequency = 15 MHz (unless otherwise specified)  
DD  
REF  
MIN  
66  
27  
27  
3
TYP  
MAX  
10000  
5000  
UNIT  
ns  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCLK cycle time, V = 4.5 V to 5.5 V (see Note 3)  
DD  
cyc(SCLK)  
Pulse duration, SCLK low  
ns  
w1  
Pulse duration, SCLK high  
5000  
ns  
w2  
Hold time, CS high after SCLK falling edge  
Setup time, CS falling edge before the first SCLK falling edge  
Hold time, CS low after 16th SCLK falling edge  
Pulse duration, CS high  
ns  
h1  
15  
5
ns  
su1  
h2  
ns  
0.5  
SCLKs  
ns  
w3  
Delay time, CS falling edge to SDO MSB valid, V  
DD  
= V  
REF  
= 4.5 V, 20 pF  
= V = 4.5 V, 20 pF  
12  
17  
15  
20  
d1  
Delay time, SCLK rising edge to next SDO data bit valid, V  
DD  
th  
Delay time, 17 SCLK rising edge to 3-stated SDO, V  
DD  
ns  
d2  
REF  
= 4.5 V, 20 pF (see Note 4)  
= V  
REF  
ns  
d3  
Setup time, CS falling edge before FS rising edge (TLC3541 only)  
Pulse duration, FS high (TLC3541 only)  
0.5  
0.5  
12.5  
5
1
1
SCLKs  
SCLKs  
ns  
su3  
w4  
Setup time, FS rising edge before SCLK falling edge (TLC3541 only)  
Hold time, FS high after SCLK falling edge (TLC3541 only)  
su4  
h4  
ns  
Setup time, FS falling edge before 1st SCLK falling edge (TLC3541 only)  
12  
ns  
su5  
d4  
Delay time, FS rising edge to SDO MSB valid, (V  
Hold time, CS low after 1st SCLK falling edge  
= V  
REF  
= 4.5 V, 20 pF TLC3541 only)  
15  
ns  
DD  
5
5
ns  
h6  
Setup time, CS rising edge before 9th (or the last) SCLK falling edge  
Hold time, FS low after 1st SCLK falling edge (TLC3541 only)  
Setup time, FS rising edge before 9th (or the last) SCLK falling edge  
Active CS/FS cycle time, SCLK falling edges required to initialize ADC  
Conversion time (20 conversion clocks based on 7.5 MHz to 12 MHz OSC)  
Sample time, 20 SCLKs, SCLK up to 15 MHz  
ns  
su6  
h7  
5
ns  
5
ns  
su7  
cyc(reset)  
conv  
s
1
8
2.67  
200  
SCLKs  
µs  
1.67  
1.33  
µs  
NOTES: 3. Timing specifications given for 40/60 to 60/40 duty cycle  
4. SDO goes into the high impedance state after detection of the 17th rising SCLK edge or a rising CS edge if a 17th SCLK is not  
presented.  
6
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SLAS345 − DECEMBER 2001  
TYPICAL CHARACTERISTICS  
FFT  
0
f = 15 kHz,  
−20  
i
V
= V = 5 V,  
REF  
DD  
200 KSPS  
−40  
−60  
−80  
−100  
−120  
−140  
−160  
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
100  
f − Input Frequency − kHz  
i
Figure 1  
FFT  
0
f = 1.5 kHz,  
i
DD REF  
200 KSPS  
−20  
−40  
V
= V = 5 V,  
−60  
−80  
−100  
−120  
−140  
−160  
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
100  
f − Input Frequency − kHz  
i
Figure 2  
DIFFERENTIAL NONLINEARITY  
1.5  
1
0.5  
0
−0.5  
−1  
−1.5  
0
5000  
10000  
15000  
Code  
Figure 3  
7
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SLAS345 − DECEMBER 2001  
TYPICAL CHARACTERISTICS  
INTEGRAL NONLINEARITY  
1.5  
1
0.5  
0
−0.5  
−1  
−1.5  
0
5000  
10000  
15000  
Code  
Figure 4  
TOTAL HARMONIC DISTORTION  
SIGNAL-TO NOISE RATIO  
vs  
vs  
INPUT FREQUENCY  
INPUT FREQUENCY  
−80  
85  
83  
V
DD  
= V = 5 V  
REF  
V
DD  
= V = 5 V  
REF  
−85  
−90  
81  
79  
−95  
77  
75  
−100  
0
20  
40  
60  
80  
100  
120  
0
20  
40  
60  
80  
100  
120  
f − Input Frequency − kHz  
i
f − Input Frequency − kHz  
i
Figure 5  
Figure 6  
8
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SLAS345 − DECEMBER 2001  
TYPICAL CHARACTERISTICS  
SIGNAL-TO-NOISE RATIO  
vs  
FREE-AIR TEMPERATURE  
TOTAL HARMONIC DISTORTION  
vs  
FREE-AIR TEMPERATURE  
83.4  
83.3  
83.2  
83.1  
−82  
−84  
−86  
f = 1 kHz  
i
f = 100 kHz  
i
f = 15 kHz  
−88  
−90  
−92  
i
83  
82.9  
82.8  
82.7  
82.6  
82.5  
f = 15 kHz  
i
−94  
−96  
f = 1 kHz  
i
−98  
−40  
25  
80  
−40  
25  
80  
T − Free-Air Temperature − °C  
A
T
A
− Free-Air Temperature − °C  
Figure 7  
Figure 8  
TOTAL HARMONIC DISTORTION  
SIGNAL-TO-NOISE RATIO  
vs  
vs  
REFERENCE VOLTAGE  
REFERENCE VOLTAGE  
−97.5  
−98.0  
83.0  
82.8  
82.6  
82.4  
82.2  
82.0  
81.8  
f = 1.5 kHz, 200 KSPS  
i
−98.5  
−99.0  
−99.5  
−100.0  
−100.5  
−101.0  
4.0  
4.5  
5.0  
4.0  
4.5  
− Reference Voltage − V  
5.0  
V
REF  
− Reference Voltage − V  
V
REF  
Figure 9  
Figure 10  
9
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SLAS345 − DECEMBER 2001  
TYPICAL CHARACTERISTICS  
MAXIMUM DIFFERENTIAL NONLINEARITY  
MINIMUM DIFFERENTIAL NONLINEARITY  
vs  
vs  
REFERENCE VOLTAGE  
REFERENCE VOLTAGE  
0.8  
0.6  
0.8  
0.6  
0.4  
0.4  
0.2  
0.2  
−0.0  
−0.2  
−0.4  
−0.6  
−0.8  
−0.0  
−0.2  
−0.4  
−0.6  
−0.8  
5.0  
5.0  
4.0  
4.5  
4.0  
4.5  
V
REF  
− Reference Voltage − V  
V
REF  
− Reference Voltage − V  
Figure 11  
Figure 12  
INTEGRAL NONLINEARITY  
vs  
REFERENCE VOLTAGE  
0.8  
0.6  
0.4  
0.2  
−0.0  
−0.2  
−0.4  
−0.6  
−0.8  
4.0  
4.5  
5.0  
V
REF  
− Reference Voltage − V  
Figure 13  
10  
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SLAS345 − DECEMBER 2001  
PRINCIPLES OF OPERATION  
control and timing  
device initialization/RESET cycle  
The TLC3541/45 each require one RESET cycle after power-on for initialization in order to operate properly.  
The RESET cycle is initiated by asserting the CS pin (pin 1) low for a minimum duration of at least one SCLK  
falling edge but no more than 8 SCLK falling edges in length. The RESET cycle is terminated by asserting CS  
high. If a valid RESET cycle is issued, the data presented on the SDO output during the following cycle is 3FC0h.  
This output code is useful in determining when a valid reset/initialization has occurred.  
The TLC3541 has separate CS and FS pins. In this case, it is also possible to initiate the RESET cycle by  
asserting FS low if CS is already asserted low. The RESET cycle can be terminated by either asserting CS high  
(as shown in the first RESET cycle in Figure 14), or by asserting FS high (as shown in the second RESET cycle  
in Figure 14), whichever happens first.  
1
8
2
1
2
8
1
16  
1
4
4
SCLK  
t
cyc(reset)  
OR  
CS  
FS  
t
FS High for Valid Initialization  
cyc(reset)  
1−8 Falling SCLK Edges−  
ADC is Initialized  
Normal Cycle−Sample  
and Convert  
Normal Cycle−Sample  
and Convert  
t
(PWRDWN)  
SDO  
MSB  
LSB+1 LSB  
1111−1111−0000−00−XX  
SDO Data−Reset of Previous Cycle’s Sample  
For TLC35xx−LSB Presented on 14th Rising SCLK Edge  
Figure 14. TLC3541/45 Initialization Timing  
sampling  
The converter sample time is 20 SCLKs in duration, beginning on the 5th SCLK received during an active signal  
on the CS input (or FS input for the TLC3541.)  
conversion  
Each device completes a conversion in the following manner. The conversion is started after the 24th falling  
SCLK edge. The CS input can be released at this point or at any time during the remainder of the conversion  
cycle. The conversion takes a maximum of 2.67 µs to complete. Enough time (for conversion) should be allowed  
before the next falling edge on the CS input (or rising edge on the FS input for the TLC3541) so that no  
conversion is terminated prematurely. If the conversion cycle is terminated early, the data presented on SDO  
during the following cycle is 3FC0h. This predefined output code is helpful in determining if the cycle time is not  
long enough to complete the conversion. The same code is also used to determine if a reset cycle is valid.  
For all devices, the SDO data presented during a cycle is the result of the conversion of the sample taken during  
the previous cycle. The output data format is shown in the following table.  
SERIAL OUTPUT DATA FORMAT  
MSB [D15:D2]  
LSB [D1:D0]  
TLC3541/45  
Conversion result (OD13−OD0)  
Don’t care  
11  
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SLAS345 − DECEMBER 2001  
PRINCIPLES OF OPERATION  
control and timing (continued)  
sampling and conversion cycle  
TLC3541:  
Control via pin 1, CS (FS = 1 at the falling edge of CS) − The falling edge of CS is the start of the cycle.  
Transitions on CS can occur when SCLK is high or low. The MSB may be read on the first falling SCLK edge  
after CS is low. Output data changes on the rising edge of SCLK. This control method is typically used for a  
microcontroller with an SPI interface, although it can also be used for a DSP. The microcontroller SPI  
interface should be programmed for CPOL = 0 (serial clock inactive low) and CPHA = 1 (data valid on the  
falling edge of serial clock).  
Control via pin 7, FS (CS is tied/held low) − The rising edge of FS is the start of the cycle. Transitions on FS  
can occur when SCLK is high or low. The MSB is presented on SDO after the rising edge of FS. The MSB  
may be read on the first falling edge of SCLK after the FS falling edge. Output data changes on the rising  
edge of SCLK. This is the typical configuration when the ADC is the only device on the TMS320 DSP serial  
port.  
Control via pin 1 and pin 7, CS and FS − Transitions on CS and FS can occur when SCLK is high or low. The  
MSB is presented after the rising edge of FS. The falling edge of FS is the start of the sampling cycle. The  
MSB may be read on the first falling edge of SCLK after the FS falling edge. Output data changes on the  
rising edge of SCLK. This is typically used for multiple devices connected to a single TMS320 DSP serial  
port.  
TLC3545:  
All control is provided using the CS input (pin 1) on the TLC3545. Transitions on CS can occur when SCLK is  
high or low. The cycle is started on the falling edge transition on the CS input. This signal can be provided by  
either a CS signal (when interfacing with an SPI microcontroller) or FS signal (when interfacing with a  
TMS320 DSP). The MSB is presented to SDO on the falling edge of the signal applied to pin 1 and may be  
read on the first falling SCLK edge after this input is low. Output data changes on the rising edge of SCLK.  
control modes  
control via pin 1 (CS, SPI interface)  
All devices are compatible with this mode of operation. A falling edge on the CS input initiates the cycle. (For  
the TLC3541, the FS input is tied to V ). The CS input remains low for the entire sampling time plus 4 SCLK  
DD  
decoding time (24 falling SCLK edges) and can then be released at any point during the remainder of the  
conversion. Enough time should be allowed before the next falling CS edge so that the conversion cycle is not  
terminated prematurely. The microcontroller SPI interface should be programmed for CPOL = 0 (serial clock  
inactive low) and CPHA = 1 (data is valid on the falling edge of serial clock).  
1
3
4
7
12  
13  
14  
15  
16  
24  
2
5
6
1
SCLK  
CS  
t
t
s
conv  
SDO Data Is the Result of the Previous Sample  
For TLC35xx, the LSB Is Presented on the Rising SCLK 14th Edge  
t
(PWRDWN)  
SDO  
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6  
LSB+2 LSB+1  
LSB LSB−1 LSB−2  
MSB MSB−1  
Figure 15. SPI Cycle TIming Using the CS Input (FS = 1 for TLC3541)  
12  
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SLAS345 − DECEMBER 2001  
PRINCIPLES OF OPERATION  
control via pin 1 (CS, DSP interface)  
All devices are compatible with this mode of operation. The FS signal from a DSP is connected directly to the  
CS input of the ADC. A falling edge on the CS input while SCLK is high or low initiates the cycle. (For TLC3541  
in this configuration, the FS input is tied to V .) Enough time should be allowed before the next rising CS edge  
DD  
so that the conversion cycle is not terminated prematurely.  
1
3
4
7
2
5
6
12  
13  
14  
15  
16  
24  
1
SCLK  
CS  
t
s
t
conv  
The CS Input Signal Is  
SDO Data Is the Result of the Previous Sample  
For TLC35xx, the LSB Is Presented on the Rising SCLK 14th Edge  
Generated by the FS Output  
From a TMS320 DSP  
SDO  
t
(PWRDWN)  
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6  
LSB+2 LSB+1  
LSB LSB−1 LSB−2  
MSB MSB−1  
Figure 16. DSP Cycle Timing Using the CS Input (FS = 1 for TLC3541 only)  
control via pin 1 and pin 7 (CS and FS or FS only, DSP interface)  
Only TLC3541 is compatible with this mode of operation. The CS input to the ADC can be controlled via a  
general-purpose I/O pin from the DSP or tied to ground. The FS signal from the DSP is connected directly to  
the FS input of the ADC. A rising FS edge releases the MSB to the SDO output. The falling edge on the FS input  
while SCLK is high or low initiates the cycle. The CS input should remain low for the entire sampling time plus  
4 SCLK decoding time after falling FS (24 falling SCLK edges) and can then be released at any time during the  
remainder of the conversion cycle. The optimum DSP interface is achieved when tying CS to ground and using  
only the FS input to control the ADC.  
24  
1
3
4
2
5
6
17  
14  
15  
16  
3
4
1
2
SCLK  
CS  
FS  
t
t
conv  
s
SDO Data Is the Result of the Previous Sample  
For TLC35xx, the LSB Is Presented on the Rising SCLK 14th Edge  
t
(PWRDWN)  
LSB LSB−1 LSB−2  
MSB MSB−1 MSB−2 MSB−3  
SDO  
LSB+1  
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5  
The MSB Is Presented on the SDO Output After  
a Rising Edge on the FS Input.  
The Device Will Go Into the Power Down State After the Conversion Is  
Complete. A Falling CS Edge or Rising FS Edge, Whichever Occurs First,  
Removes the Device From Power Down.  
Figure 17. DSP Cycle Timing Using FS Only (or Using Both CS and FS for TLC3541)  
13  
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SLAS345 − DECEMBER 2001  
PRINCIPLES OF OPERATION  
t
t
s
conv  
t
cyc(SCLK)  
1
5
1
2
14  
SCLK  
CS  
15  
16  
17,  
24  
t
t
t
(PWRDWN)  
w1  
su1  
t
h2  
t
w2  
t
w3  
t
h1  
t
d2  
t
d3  
SDO  
LSB  
MSB  
MSB  
LSB−1  
LSB−2  
t
d1  
Figure 18. Critical Timing: Control Via CS Input (FS = 1 for TLC3541)  
t
t
s
conv  
1
1
2
5
14  
15  
16  
SCLK  
17,  
24  
t
su5  
t
t
(PWRDWN)  
h2  
t
h4  
t
su4  
CS  
FS  
t
w4  
t
(PWRDWN)  
t
d2  
t
t
d3  
su3  
SDO  
LSB  
LSB−1  
LSB−2  
MSB  
MSB  
t
d4  
Figure 19. Critical Timing: Control Via CS and FS Inputs (TLC3541 Only)  
1
2
1
2
8
9
SCLK  
t
t
su6  
h6  
t
cyc(reset)  
Normal Cycle Begins  
CS  
Reset Cycle  
SDO  
MSB  
MSB−1  
MSB  
(Output = 3FC0h)  
Figure 20. Critical Timing: Reset/Initialization Cycle (FS =1 for TLC3541)  
14  
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ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢇ ꢀꢁ ꢂꢃ ꢄꢅ ꢄ  
SLAS345 − DECEMBER 2001  
PRINCIPLES OF OPERATION  
2
2
1
8
9
1
8
t
9
1
2
SCLK  
CS  
t
t
t
h7  
h7  
su7  
su6  
t
cyc(reset)  
t
cyc(reset)  
OR  
Normal Cycle Begins  
FS  
Initialization Cycle (Reset)  
MSB  
MSB  
MSB  
MSB−1  
SDO  
Figure 21. Critical Timing: Initialization Cycle (TLC3541 Only)  
detailed description  
The TLC3541/5 are successive approximation (SAR) ADCs utilizing a charge-redistribution DAC. Figure 22  
shows a simplified version of the ADC. The sampling capacitor acquires the signal on AIN (or the AIN(+) pin for  
TLC3545) during the sampling period. When the conversion process starts, the SAR control logic and charge  
redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the  
comparator into a balanced condition. When the comparator is balanced, the conversion is complete and the  
ADC output code is generated.  
Charge  
Redistribution  
DAC  
AIN/  
AIN(+)  
Control  
Logic  
ADC Code  
C
i
+
C
i
GND/  
AIN(−)  
Figure 22. Simplified SAR Circuit  
15  
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ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢀ ꢁ ꢂ ꢃꢄ ꢅꢄ  
SLAS345 − DECEMBER 2001  
PRINCIPLES OF OPERATION  
pseudo-differential inputs  
The TLC3545 operates in pseudo-differential mode. The inverted input is available on pin 5. The inverted input  
can tolerate a maximum input ripple of 0.2 V. It is normally used for zero-scale offset cancellation or ground  
noise rejection.  
serial interface  
Output data format is binary (unipolar straight binary).  
binary  
D
Zero-Scale Code = 0000h, V  
= GND  
AIN  
D
Full-Scale Code = 3FFFh, V  
= V  
– 1 LSB  
AIN  
REF  
reference voltage  
An external reference must be applied via pin 2, V  
limit of the analog inputs to produce a full-scale reading. The value of V  
exceed the positive supply or be less than GND, consistent with the specified absolute maximum ratings. The  
. The voltage level applied to this pin establishes the upper  
REF  
, and the analog input should not  
REF  
digital output is at full scale when the input signal is equal to or higher than V  
signal is equal to or less than GND.  
and at zero when the input  
REF  
auto-power down and power up  
Auto-power down is built into the devices in order to reduce power consumption. The wake-up time is fast  
enough to provide power down between each conversion cycle. The power-down state is initiated at the end  
of conversion and wakes up on a falling CS edge (or rising FS edge, whichever occurs first, for TLC3541 only).  
16  
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ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢇ ꢀꢁ ꢂꢃ ꢄꢅ ꢄ  
SLAS345 − DECEMBER 2001  
APPLICATION INFORMATION  
5 V  
DSP to Single TLC3541  
0.1 µF  
REF  
0.1 µF  
10 kΩ  
10 kΩ  
V
DD  
FS  
REF  
FSX0  
SD0  
SCLK  
CS  
DR0  
DSP  
TLC3541  
GND  
AIN  
CLKX0  
CLKR0  
5 V  
DSP to Single TLC3545  
0.1 µF  
REF  
0.1 µF  
10 kΩ  
10 kΩ  
V
DD  
CS  
REF  
FSX0  
SD0  
SCLK  
DR0  
DSP  
TLC3545  
GND  
AIN(+)  
AIN(−)  
CLKX0  
CLKR0  
DSP to Multiple TLC3541s  
XF0  
FSX0  
DR0  
REF  
DSP  
CLKX0  
CLKR0  
XF1  
EXT REF  
INPUT  
0.1 µF  
5 V  
5 V  
0.1 µF  
0.1 µF  
10 kΩ  
10 kΩ  
CS  
10 kΩ  
10 kΩ  
V
V
DD  
REF  
DD  
CS  
FS  
REF  
AIN  
FS  
TLC3541  
#1  
TLC3541  
#2  
AIN  
SDO  
SCLK  
SDO  
SCLK  
GND  
GND  
Figure 23. Typical ADC Interface to a TMS320 DSP  
17  
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ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢀ ꢁ ꢂ ꢃꢄ ꢅꢄ  
SLAS345 − DECEMBER 2001  
MECHANICAL DATA  
D (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0.050 (1,27)  
0.020 (0,51)  
0.014 (0,35)  
0.010 (0,25)  
M
14  
8
0.008 (0,20) NOM  
0.244 (6,20)  
0.228 (5,80)  
0.157 (4,00)  
0.150 (3,81)  
Gage Plane  
0.010 (0,25)  
1
7
0°ā8°  
0.044 (1,12)  
A
0.016 (0,40)  
Seating Plane  
0.004 (0,10)  
0.010 (0,25)  
0.004 (0,10)  
0.069 (1,75) MAX  
PINS **  
8
14  
16  
DIM  
0.197  
(5,00)  
0.344  
(8,75)  
0.394  
(10,00)  
A MAX  
0.189  
(4,80)  
0.337  
(8,55)  
0.386  
(9,80)  
A MIN  
4040047/D 10/96  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).  
D. Falls within JEDEC MS-012  
18  
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ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢇ ꢀꢁ ꢂꢃ ꢄꢅ ꢄ  
SLAS345 − DECEMBER 2001  
MECHANICAL DATA  
DGK (R-PDSO-G8)  
PLASTIC SMALL-OUTLINE PACKAGE  
0,38  
0,25  
M
0,65  
8
0,25  
5
0,15 NOM  
3,05  
2,95  
4,98  
4,78  
Gage Plane  
0,25  
0°ā6°  
1
4
0,69  
3,05  
2,95  
0,41  
Seating Plane  
0,10  
0,15  
0,05  
1,07 MAX  
4073329/B 04/98  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion.  
D. Falls within JEDEC MO-187  
19  
www.ti.com  
PACKAGE OPTION ADDENDUM  
www.ti.com  
19-May-2005  
PACKAGING INFORMATION  
Orderable Device  
TLC3541ID  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SOIC  
D
8
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLC3541IDGK  
TLC3541IDGKR  
TLC3541IDGKRG4  
TLC3541IDR  
MSOP  
MSOP  
MSOP  
SOIC  
DGK  
DGK  
DGK  
D
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLC3545ID  
SOIC  
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLC3545IDGK  
TLC3545IDGKR  
TLC3545IDGKRG4  
TLC3545IDR  
MSOP  
MSOP  
MSOP  
SOIC  
DGK  
DGK  
DGK  
D
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLC3545IDRG4  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process  
in which TI products or services are used. Information published by TI regarding third-party products or services  
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.  
Use of such information may require a license from a third party under the patents or other intellectual property  
of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without  
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction  
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for  
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that  
product or service voids all express and any implied warranties for the associated TI product or service and  
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.  
Following are URLs where you can obtain information on other Texas Instruments products and application  
solutions:  
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Applications  
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Amplifiers  
amplifier.ti.com  
www.ti.com/audio  
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dataconverter.ti.com  
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dsp.ti.com  
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Military  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
Logic  
interface.ti.com  
logic.ti.com  
Power Mgmt  
Microcontrollers  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
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www.ti.com/video  
microcontroller.ti.com  
Telephony  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address:  
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Post Office Box 655303 Dallas, Texas 75265  
Copyright 2005, Texas Instruments Incorporated  
配单直通车
TLC3541IDR产品参数
型号:TLC3541IDR
Brand Name:Texas Instruments
是否无铅:不含铅
是否Rohs认证:符合
生命周期:Active
IHS 制造商:TEXAS INSTRUMENTS INC
零件包装代码:SOIC
包装说明:SOIC-8
针数:8
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
Factory Lead Time:6 weeks
风险等级:5.14
Is Samacsys:N
最大模拟输入电压:5.5 V
最小模拟输入电压:
最长转换时间:2.67 µs
转换器类型:ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码:R-PDSO-G8
JESD-609代码:e4
长度:4.9 mm
最大线性误差 (EL):0.0061%
湿度敏感等级:1
模拟输入通道数量:1
位数:14
功能数量:1
端子数量:8
最高工作温度:85 °C
最低工作温度:-40 °C
输出位码:BINARY
输出格式:SERIAL
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装等效代码:SOP8,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260
电源:5 V
认证状态:Not Qualified
采样速率:0.2 MHz
采样并保持/跟踪并保持:SAMPLE
座面最大高度:1.75 mm
子类别:Analog to Digital Converters
最大压摆率:3.5 mA
最小供电电压:4.5 V
标称供电电压:5 V
表面贴装:YES
技术:CMOS
温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING
端子节距:1.27 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.91 mm
Base Number Matches:1
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