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产品型号TLC372IPE4的Datasheet PDF文件预览

ꢀꢁ ꢂꢃ ꢄꢅ  
ꢋꢌꢍ ꢁ ꢋꢎ ꢏꢏ ꢐꢑ ꢐꢒꢀ ꢎꢍ ꢁ ꢂꢉ ꢈ ꢓꢍ ꢑꢍꢀꢉ ꢑꢊ  
SLCS114E − NOVEMBER 1983 − REVISED JULY 2008  
TLC372C, TLC372I, TLC372M, TLC372Q  
D, P, OR PW PACKAGE  
TLC372M . . . JG PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
Single or Dual-Supply Operation  
Wide Range of Supply Voltages 2 V to 18 V  
Low Supply Current Drain  
150 µA Typ at 5 V  
Fast Response Time . . . 200 ns Typ for  
TTL-Level Input Step  
1OUT  
1IN−  
1IN+  
GND  
V
CC  
1
2
3
4
8
7
6
5
2OUT  
2IN−  
2IN+  
Built-in ESD Protection  
12  
High Input Impedance . . . 10 Typ  
Extremely Low Input Bias Current  
5 pA Typ  
TLC372M . . . FK PACKAGE  
(TOP VIEW)  
D
Ultrastable Low Input Offset Voltage  
D
Input Offset Voltage Change at Worst-Case  
Input Conditions Typically 0.23 µV/Month,  
Including the First 30 Days  
3
2
1
20 19  
18  
NC  
NC  
1IN−  
NC  
4
5
6
7
8
D
D
D
Common-Mode Input Voltage Range  
Includes Ground  
2OUT  
NC  
17  
16  
15  
14  
Output Compatible With TTL, MOS, and  
CMOS  
2IN−  
NC  
1IN+  
NC  
9 10 11 12 13  
Pin-Compatible With LM393  
description  
This device is fabricated using LinCMOS  
technology and consists of two independent  
voltage comparators, each designed to operate  
from a single power supply. Operation from dual  
supplies is also possible if the difference between  
the two supplies is 2 V to 18 V. Each device  
features extremely high input impedance  
NC − No internal connection  
TLC372M  
U PACKAGE  
(TOP VIEW)  
NC  
1OUT  
1IN−  
NC  
1
2
3
4
5
10  
9
12  
(typically greater than 10 ), allowing direct  
V
CC  
interfacing with high-impedance sources. The  
outputs are n-channel open-drain configurations  
and can be connected to achieve positive-logic  
wired-AND relationships.  
8
2OUT  
2IN−  
2IN+  
1IN+  
7
6
GND  
The TLC372 has internal electrostatic discharge  
(ESD) protection circuits and has been classified  
with a 1000-V ESD rating using human body  
model testing. However, care should be exercised  
in handling this device as exposure to ESD may  
result in a degradation of the device parametric  
performance.  
symbol (each comparator)  
IN+  
OUT  
IN −  
The TLC372C is characterized for operation from 0°C to 70°C. The TLC372I is characterized for operation from  
−40°C to 85°C. The TLC372M is characterized for operation over the full military temperature range of 55°C  
to 125°C. The TLC372Q is characterized for operation from 40°C to 125°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
LinCMOS is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners.  
ꢀꢝ  
Copyright 1983−2008, Texas Instruments Incorporated  
ꢙ ꢝ ꢚ ꢙꢆ ꢇꢧ ꢕꢔ ꢘ ꢠꢠ ꢞꢘ ꢖ ꢘ ꢗ ꢝ ꢙ ꢝ ꢖ ꢚ ꢢ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂ ꢃꢄ ꢅ  
 
ꢋ ꢌꢍ ꢁ ꢋꢎ ꢏ ꢏꢐ ꢑꢐ ꢒꢀ ꢎ ꢍꢁ ꢂꢉ ꢈꢓꢍꢑꢍꢀꢉ ꢑꢊ  
SLCS114E − NOVEMBER 1983 − REVISED JULY 2008  
equivalent schematic (each comparator)  
Common to All Channels  
V
DD  
OUT  
GND  
IN +  
IN −  
(1)  
AVAILABLE OPTIONS  
PACKAGED DEVICES  
V
max  
IO  
SMALL  
CHIP  
CARRIER  
(FK)  
CERAMIC  
DIP  
PLASTIC  
DIP  
CERAMIC  
FLAT PACK  
(U)  
T
A
TSSOP  
(PW)  
AT 25°C  
OUTLINE  
(2)  
(D)  
(JG)  
(P)  
0°C to 70°C  
40°C to 85°C  
55°C to 125°C  
40°C to 125°C  
5 mV  
5 mV  
5 mV  
5 mV  
TLC372CD  
TLC372ID  
TLC372MD  
TLC372QD  
TLC372CP  
TLC372IP  
TLC372MP  
TLC372QP  
TLC372CPW  
TLC372MFK  
TLC372MJG  
TLC372MU  
1.For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web  
site at www.ti.com.  
2.The D packages are available taped and reeled. Add R suffix to device type (e.g., TLC372CDR).  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀꢁ ꢂꢃ ꢄꢅ  
ꢋꢌꢍ ꢁ ꢋꢎ ꢏꢏ ꢐꢑ ꢐꢒꢀ ꢎꢍ ꢁ ꢂꢉ ꢈ ꢓꢍ ꢑꢍꢀꢉ ꢑꢊ  
SLCS114E − NOVEMBER 1983 − REVISED JULY 2008  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage, V  
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V  
DD  
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V  
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 18 V  
ID  
I
Output voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V  
O
Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA  
I
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA  
O
Duration of output short circuit to ground (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited  
Package thermal impedance, θ (see Notes 6 and 7): D package . . . . . . . . . . . . . . . . . . . . . . . . . . 97.1°C/W  
JA  
P package . . . . . . . . . . . . . . . . . . . . . . . . . . 84.6°C/W  
PW package . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W  
Package thermal impedance, θ (see Notes 6 and 7): FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6°C/W  
JC  
JG package . . . . . . . . . . . . . . . . . . . . . . . . . 14.5°C/W  
U package . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7°C/W  
Operating free-air temperature range, T : TLC372C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
A
TLC372I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C  
TLC372M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C  
TLC372Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C  
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, P, or PW package . . . . . . . . . . . . 260°C  
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG or U package . . . . . . . . . . . . . . . 300°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 3. All voltage values except differential voltages are with respect to network ground.  
4. Differential voltages are at IN+ with respect to IN −.  
5. Short circuits from outputs to V  
can cause excessive heating and eventual device destruction.  
DD  
6. Maximum power dissipation is a function of T (max), θ , and T . The maximum allowable power dissipation at any allowable  
JA  
J
A
ambient temperature is P = (T (max) − T )/θ . Operating at the absolute maximum T of 150°C can affect reliability.  
D
J
A
JA  
J
7. The package thermal impedance is calculated in accordance with JESD 51-7 (plastic) or MIL-STD-883 Method 1012 (ceramic).  
recommended operating conditions  
TLC372C  
TLC372I  
TLC372M  
TLC372Q  
UNIT  
MIN  
3
MAX  
MIN  
3
MAX  
MIN  
4
MAX  
MIN  
4
MAX  
Supply voltage, V  
DD  
16  
3.5  
8.5  
70  
16  
3.5  
8.5  
85  
16  
3.5  
8.5  
125  
16  
3.5  
8.5  
125  
V
V
V
= 5 V  
0
0
0
0
DD  
Common-mode input voltage, V  
IC  
V
= 10 V  
0
0
0
0
DD  
Operating free-air temperature, T  
0
40  
55  
40  
°C  
A
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
Template Release Date: 7−11−94  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ  
ꢁꢨ  
SLCS114E − NOVEMBER 1983 − REVISED JULY 2008  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀꢁ ꢂꢃ ꢄꢅ  
ꢏꢏ  
SLCS114E − NOVEMBER 1983 − REVISED JULY 2008  
electrical characteristics at specified free-air temperature, V  
noted)  
= 5 V, T = 25°C (unless otherwise  
DD  
A
TLC372Y  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN  
TYP  
MAX  
V
Input offset voltage  
V
IC  
= V  
ICR  
min, See Note 4  
1
1
5
5
mV  
pA  
pA  
IO  
I
I
Input offset current  
Input bias current  
IO  
IB  
0 to  
−1  
V
ICR  
Common-mode input voltage range  
V
V
DD  
I
High-level output current  
Low-level output voltage  
Low-level output current  
V
ID  
V
ID  
V
ID  
V
ID  
= 1 V,  
V
= 5 V  
0.1  
150  
16  
nA  
mV  
mA  
µA  
OH  
OH  
= 4 mA  
V
= 1 V,  
= 1 V,  
= 1 V,  
I
400  
300  
OL  
OL  
I
I
V
= 1.5 V  
6
OL  
OL  
No load  
Supply current (two comparators)  
150  
DD  
All characteristics are measured with zero common-mode input voltage unless otherwise noted. IMPORTANT: See Parameter Measurement  
Information.  
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kresistor  
between the output and V . They can be verified by applying the limit value to the input and checking for the appropriate output state.  
DD  
PARAMETER MEASUREMENT INFORMATION  
The digital output stage of the TLC372 can be damaged if it is held in the linear region of the transfer curve.  
Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force  
the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the  
following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc., are  
offered.  
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown  
in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With  
the input polarity reversed, the output should be low.  
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can  
be slewed as shown in Figure 1(b) for the V  
accuracy.  
test, rather than changing the input voltages, to provide greater  
ICR  
5 V  
1 V  
5.1 kΩ  
5.1 kΩ  
+
+
Applied V  
Limit  
IO  
Applied V  
Limit  
IO  
V
O
V
O
−4 V  
(a) V WITH V = 0  
IO IC  
(b) V WITH V = 4 V  
IO IC  
Figure 1. Method for Verifying That Input Offset Voltage is Within Specified Limits  
5
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ꢀ ꢁ ꢂ ꢃꢄ ꢅ  
  
ꢋ ꢌꢍ ꢁ ꢋꢎ ꢏ ꢏꢐ ꢑꢐ ꢒꢀ ꢎ ꢍꢁ ꢂꢉ ꢈꢓꢍꢑꢍꢀꢉ ꢑꢊ  
SLCS114E − NOVEMBER 1983 − REVISED JULY 2008  
PARAMETER MEASUREMENT INFORMATION  
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the  
differential input voltage while monitoring the output state. When the applied input voltage differential is equal, but  
opposite in polarity, to the input offset voltage, the output changes states.  
Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the  
comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a  
triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer, with C2 and R4 removing any residual  
dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input  
is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop  
reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which  
can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input  
exactly equals the input offset voltage.  
Voltage divider R9 and R10 provides a step up of the input offset voltage by a factor of 100 to make measurement  
easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is  
suggested that their tolerance level be 1% or lower.  
Measuring the extremely low values of input current requires isolation from all other sources of leakage current and  
compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage  
can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from  
the measurement obtained with a device in the socket to obtain the actual input current of the device.  
C3  
0.68 µF  
V
DD  
R5  
1.8 k, 1%  
U1b  
1/4 TLC274C  
C2  
1 µF  
U1c  
1/4 TLC274CN  
R6  
5.1 kΩ  
Buffer  
+
+
DUT  
R7  
1 MΩ  
V
IO  
(X100)  
R4  
47 kΩ  
R1  
240 kΩ  
R8  
1.8 k, 1%  
Integrator  
C4  
0.1 µF  
U1a  
+
1/4 TLC274CN  
C1  
0.1 µF  
Triangle  
Generator  
R9  
10 k, 1%  
R10  
100 Ω, 1%  
R2  
10 kΩ  
R3  
100 kΩ  
Figure 2. Circuit for Input Offset Voltage Measurement  
6
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ꢀꢁ ꢂꢃ ꢄꢅ  
ꢋꢌꢍ ꢁ ꢋꢎ ꢏꢏ ꢐꢑ ꢐꢒꢀ ꢎꢍ ꢁ ꢂꢉ ꢈ ꢓꢍ ꢑꢍꢀꢉ ꢑꢊ  
  
SLCS114E − NOVEMBER 1983 − REVISED JULY 2008  
PARAMETER MEASUREMENT INFORMATION  
Response time is defined as the interval between the application of an input step function and the instant when the  
output reaches 50% of its maximum value. Response time, low-to-high level output, is measured from the leading  
edge of the input pulse, while response time, high-to-low level output, is measured from the trailing edge of the input  
pulse. Response-time measurement at low input signal levels can be greatly affected by the input offset voltage. The  
offset voltage should be balanced by the adjustment at the inverting input as shown in Figure 3, so that the circuit  
is just at the transition point. Then a low signal, for example 105-mV or 5-mV overdrive, causes the output to change  
state.  
V
DD  
1 µF  
5.1 kΩ  
Pulse  
Generator  
DUT  
50 Ω  
C
1 V  
L
(see Note A)  
Input Offset Voltage  
Compensation Adjustment  
10 Ω  
10 Turn  
1 kΩ  
−1 V  
0.1 µF  
TEST CIRCUIT  
Overdrive  
100 mV  
Input  
Overdrive  
Input  
100 mV  
90%  
50%  
10%  
90%  
50%  
Low-to-High-  
Level Output  
High-to-Low-  
Level Output  
10%  
t
t
f
r
t
t
PLH  
PHL  
VOLTAGE WAVEFORMS  
NOTE A: C includes probe and jig capacitance.  
L
Figure 3. Response, Rise, and Fall Times Circuit and Voltage Waveforms  
7
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ꢀ ꢁ ꢂ ꢃꢄ ꢅ  
  
ꢋ ꢌꢍ ꢁ ꢋꢎ ꢏ ꢏꢐ ꢑꢐ ꢒꢀ ꢎ ꢍꢁ ꢂꢉ ꢈꢓꢍꢑꢍꢀꢉ ꢑꢊ  
SLCS114E − NOVEMBER 1983 − REVISED JULY 2008  
PRINCIPLES OF OPERATION  
LinCMOSprocess  
The LinCMOSprocess is a Linear polysilicon-gate complementary-MOS process. Primarily designed for  
single-supply applications, LinCMOSproducts facilitate the design of a wide range of high-performance  
analog functions, from operational amplifiers to complex mixed-mode converters.  
While digital designers are experienced with CMOS, MOS technologies are relatively new for analog designers.  
This short guide is intended to answer the most frequently asked questions related to the quality and reliability  
of LinCMOSproducts. Further questions should be directed to the nearest Texas Instruments field sales office.  
electrostatic discharge  
CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only  
for very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage to  
CMOS devices. It can occur when a device is handled without proper consideration for environmental  
electrostatic charges, e.g. during board assembly. If a circuit in which one amplifier from a dual operational  
amplifier is being used and the unused pins are left open, high voltages tends to develop. If there is no provision  
for ESD protection, these voltages may eventually punch through the gate oxide and cause the device to fail.  
To prevent voltage buildup, each pin is protected by internal circuitry.  
Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more  
transistors break down at voltages higher than the normal operating voltages but lower than the breakdown  
voltage of the input gate. This type of protection scheme is limited by leakage currents which flow through the  
shunting transistors during normal operation after an ESD voltage has occurred. Although these currents are  
small, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as  
tens of picoamps.  
To overcome this limitation, Texas Instruments design engineers developed the patented ESD-protection circuit  
shown in Figure 4. This circuit can withstand several successive 1-kV ESD pulses, while reducing or eliminating  
leakage currents that may be drawn through the input pins. A more detailed discussion of the operation of Texas  
Instruments’s ESD- protection circuit is presented on the next page.  
All input and output pins on LinCMOS and Advanced LinCMOSproducts have associated ESD-protection  
circuitry that undergoes qualification testing to withstand 1000 V discharged from a 100-pF capacitor through  
a 1500-resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor  
(charged device model). These tests simulate both operator and machine handling of devices during normal  
test and assembly operations.  
V
DD  
R1  
Input  
To Protected Circuit  
R2  
Q1  
Q2  
D1  
D2  
D3  
V
SS  
Figure 4. LinCMOSESD-Protection Schematic  
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.  
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀꢁ ꢂꢃ ꢄꢅ  
ꢋꢌꢍ ꢁ ꢋꢎ ꢏꢏ ꢐꢑ ꢐꢒꢀ ꢎꢍ ꢁ ꢂꢉ ꢈ ꢓꢍ ꢑꢍꢀꢉ ꢑꢊ  
  
SLCS114E − NOVEMBER 1983 − REVISED JULY 2008  
PRINCIPLES OF OPERATION  
input protection circuit operation  
Texas Instruments’ patented protection circuitry allows for both positive-and negative-going ESD transients.  
These transients are characterized by extremely fast rise times and usually low energies, and can occur both  
when the device has all pins open and when it is installed in a circuit.  
positive ESD transients  
Initial positive charged energy is shunted through Q1 to V . Q1 turns on when the voltage at the input rises  
SS  
EB  
above the voltage on the V  
pin by a value equal to the V of Q1. The base current increases through R2  
DD  
with input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2  
to exceed its threshold level (V ~ 22 V to 26 V) and turn Q2 on. The shunted input current through Q1 to V  
T
SS  
is now shunted through the n-channel enhancement-type MOSFET Q2 to V . If the voltage on the input pin  
SS  
continues to rise, the breakdown voltage of the zener diode D3 is exceeded, and all remaining energy is  
dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 V to 27 V, which is well below the  
gate oxide voltage of the circuit to be protected.  
negative ESD transients  
The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1  
and D2 as D2 becomes forward biased. The voltage seen by the protected circuit is 0.3 V to 1 V (the forward  
voltage of D1 and D2).  
circuit-design considerations  
LinCMOSproducts are being used in actual circuit environments that have input voltages that exceed the  
recommended common-mode input voltage range and activate the input protection circuit. Even under normal  
operation, these conditions occur during circuit power up or power down, and in many cases, when the device  
is being used for a signal conditioning function. The input voltages can exceed V  
and not damage the device  
ICR  
only if the inputs are current limited. The recommended current limit shown on most product data sheets is  
5 mA. Figure 5 and Figure 6 show typical characteristics for input voltage versus input current.  
Normal operation and correct output state can be expected even when the input voltage exceeds the positive  
supply voltage. Again, the input current should be externally limited even though internal positive current limiting  
is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current  
to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input  
current. This base current is forced into the V  
producing the current limiting effects shown in Figure 5. This internal limiting lasts only as long as the input  
pin and into the device I  
or the V  
supply through R2  
DD  
DD  
DD  
voltage is below the V of Q2.  
T
When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage  
states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be  
severely affected. External current limiting must be used since this current is directly shunted by D1 and D2 and  
no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is  
required (see Figure 7).  
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂ ꢃꢄ ꢅ  
  
SLCS114E − NOVEMBER 1983 − REVISED JULY 2008  
PRINCIPLES OF OPERATION  
circuit-design considerations (continued)  
INPUT CURRENT  
vs  
INPUT CURRENT  
vs  
POSITIVE INPUT VOLTAGE  
NEGATIVE INPUT VOLTAGE  
8
−10  
−9  
−8  
−7  
−6  
−5  
−4  
−3  
−2  
−1  
0
T
A
= 25°C  
T
= 25°C  
A
7
6
5
4
3
2
1
0
V
V
DD  
+ 4  
V
DD  
+ 8  
V
DD  
+ 12  
−0.3  
−0.5  
−0.7  
−0.9  
DD  
Input Voltage (V)  
Input Voltage (V)  
Figure 5  
Figure 6  
V
DD  
Positive Voltage Input Current Limit:  
+V − V − 0.3 V  
I
DD  
5 mA  
R =  
I
R
I
R
L
Negative Voltage Input Current Limit:  
V
I
+
| V | − 0.3 V  
I
R =  
I
TLC372  
5 mA  
V
ref  
See Note A  
NOTE A: If the correct output state is required when the negative input is less than GND, a schottky clamp is required.  
Figure 7. Typical Input Current-Limiting Configuration for a LinCMOSComparator  
10  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
25-Sep-2013  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
5962-87658012A  
ACTIVE  
LCCC  
FK  
20  
1
TBD  
POST-PLATE  
N / A for Pkg Type  
-55 to 125  
5962-  
87658012A  
TLC372MFKB  
5962-8765801PA  
5962-9554901NXD  
5962-9554901NXDR  
TLC372CD  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
CDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
SO  
JG  
D
8
8
8
8
8
8
8
8
8
8
8
8
8
1
TBD  
A42  
N / A for Pkg Type  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
N / A for Pkg Type  
-55 to 125  
-55 to 125  
-55 to 125  
0 to 70  
8765801PA  
TLC372M  
2500  
2500  
75  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Q372M  
Q372M  
372C  
D
Green (RoHS  
& no Sb/Br)  
D
Green (RoHS  
& no Sb/Br)  
TLC372CDG4  
TLC372CDR  
D
75  
Green (RoHS  
& no Sb/Br)  
0 to 70  
372C  
D
2500  
2500  
50  
Green (RoHS  
& no Sb/Br)  
0 to 70  
372C  
TLC372CDRG4  
TLC372CP  
D
Green (RoHS  
& no Sb/Br)  
0 to 70  
372C  
P
Pb-Free  
(RoHS)  
0 to 70  
TLC372CP  
TLC372CP  
P372  
TLC372CPE4  
P
50  
Pb-Free  
(RoHS)  
N / A for Pkg Type  
0 to 70  
TLC372CPSR  
TLC372CPSRG4  
TLC372CPW  
PS  
PS  
PW  
PW  
2000  
2000  
150  
150  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
0 to 70  
SO  
Green (RoHS  
& no Sb/Br)  
0 to 70  
P372  
TSSOP  
TSSOP  
Green (RoHS  
& no Sb/Br)  
0 to 70  
P372  
TLC372CPWG4  
Green (RoHS  
& no Sb/Br)  
0 to 70  
P372  
TLC372CPWLE  
TLC372CPWR  
OBSOLETE  
ACTIVE  
TSSOP  
TSSOP  
PW  
PW  
8
8
TBD  
Call TI  
Call TI  
0 to 70  
0 to 70  
2000  
2000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-1-260C-UNLIM  
P372  
P372  
TLC372CPWRG4  
ACTIVE  
TSSOP  
PW  
8
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-1-260C-UNLIM  
0 to 70  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
25-Sep-2013  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-55 to 125  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
TLC372ID  
TLC372IDG4  
TLC372IDR  
ACTIVE  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
LCCC  
D
8
8
75  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
POST-PLATE  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
N / A for Pkg Type  
372I  
372I  
372I  
372I  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
D
D
75  
2500  
2500  
50  
Green (RoHS  
& no Sb/Br)  
8
Green (RoHS  
& no Sb/Br)  
TLC372IDRG4  
TLC372IP  
D
8
Green (RoHS  
& no Sb/Br)  
P
8
Pb-Free  
(RoHS)  
TLC372IP  
TLC372IP  
372M  
TLC372IPE4  
TLC372MD  
P
8
50  
Pb-Free  
(RoHS)  
N / A for Pkg Type  
D
8
75  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
N / A for Pkg Type  
TLC372MDG4  
TLC372MDR  
TLC372MDRG4  
TLC372MFKB  
D
8
75  
Green (RoHS  
& no Sb/Br)  
372M  
D
8
2500  
2500  
1
Green (RoHS  
& no Sb/Br)  
-55 to 125  
-55 to 125  
372M  
D
8
Green (RoHS  
& no Sb/Br)  
372M  
FK  
20  
TBD  
5962-  
87658012A  
TLC372MFKB  
TLC372MJG  
ACTIVE  
ACTIVE  
CDIP  
CDIP  
JG  
JG  
8
8
1
1
TBD  
TBD  
A42  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
-55 to 125  
-55 to 125  
TLC372MJG  
TLC372MJGB  
8765801PA  
TLC372M  
TLC372MP  
ACTIVE  
PDIP  
P
8
50  
Pb-Free  
(RoHS)  
CU NIPDAU  
N / A for Pkg Type  
-55 to 125  
TLC372MP  
TLC372MUB  
TLC372QD  
ACTIVE  
ACTIVE  
CFP  
U
D
10  
8
1
TBD  
A42  
N / A for Pkg Type  
-55 to 125  
-40 to 125  
TLC372MUB  
372Q  
SOIC  
75  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-1-260C-UNLIM  
TLC372QDG4  
TLC372QDR  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
D
D
8
8
75  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
-40 to 125  
-40 to 125  
372Q  
372Q  
2500  
Green (RoHS  
& no Sb/Br)  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
25-Sep-2013  
Orderable Device  
TLC372QDRG4  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
ACTIVE  
SOIC  
D
8
2500  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-1-260C-UNLIM  
-40 to 125  
372Q  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF TLC372, TLC372M :  
Catalog: TLC372  
Addendum-Page 3  
PACKAGE OPTION ADDENDUM  
www.ti.com  
25-Sep-2013  
Enhanced Product: TLC372-EP, TLC372-EP  
Military: TLC372M  
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
Enhanced Product - Supports Defense, Aerospace and Medical Applications  
Military - QML certified for Military and Defense Applications  
Addendum-Page 4  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
8-Jul-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
5962-9554901NXDR  
TLC372CDR  
SOIC  
SOIC  
SO  
D
D
8
8
8
8
8
8
8
8
2500  
2500  
2000  
2000  
2500  
2500  
2500  
2500  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
12.4  
12.4  
16.4  
12.4  
12.4  
12.4  
12.4  
12.4  
6.4  
6.4  
8.2  
7.0  
6.4  
6.4  
6.4  
6.4  
5.2  
5.2  
6.6  
3.6  
5.2  
5.2  
5.2  
5.2  
2.1  
2.1  
2.5  
1.6  
2.1  
2.1  
2.1  
2.1  
8.0  
8.0  
12.0  
8.0  
8.0  
8.0  
8.0  
8.0  
12.0  
12.0  
16.0  
12.0  
12.0  
12.0  
12.0  
12.0  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
TLC372CPSR  
TLC372CPWR  
TLC372IDR  
PS  
PW  
D
TSSOP  
SOIC  
SOIC  
SOIC  
SOIC  
TLC372MDR  
D
TLC372MDRG4  
TLC372QDR  
D
D
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
8-Jul-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
5962-9554901NXDR  
TLC372CDR  
SOIC  
SOIC  
SO  
D
D
8
8
8
8
8
8
8
8
2500  
2500  
2000  
2000  
2500  
2500  
2500  
2500  
367.0  
340.5  
367.0  
367.0  
340.5  
367.0  
367.0  
367.0  
367.0  
338.1  
367.0  
367.0  
338.1  
367.0  
367.0  
367.0  
35.0  
20.6  
38.0  
35.0  
20.6  
35.0  
35.0  
35.0  
TLC372CPSR  
TLC372CPWR  
TLC372IDR  
PS  
PW  
D
TSSOP  
SOIC  
SOIC  
SOIC  
SOIC  
TLC372MDR  
D
TLC372MDRG4  
TLC372QDR  
D
D
Pack Materials-Page 2  
MECHANICAL DATA  
MCER001A – JANUARY 1995 – REVISED JANUARY 1997  
JG (R-GDIP-T8)  
CERAMIC DUAL-IN-LINE  
0.400 (10,16)  
0.355 (9,00)  
8
5
0.280 (7,11)  
0.245 (6,22)  
1
4
0.065 (1,65)  
0.045 (1,14)  
0.310 (7,87)  
0.290 (7,37)  
0.063 (1,60)  
0.015 (0,38)  
0.020 (0,51) MIN  
0.200 (5,08) MAX  
0.130 (3,30) MIN  
Seating Plane  
0.023 (0,58)  
0.015 (0,38)  
0°–15°  
0.100 (2,54)  
0.014 (0,36)  
0.008 (0,20)  
4040107/C 08/96  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. This package can be hermetically sealed with a ceramic lid using glass frit.  
D. Index point is provided on cap for terminal identification.  
E. Falls within MIL STD 1835 GDIP1-T8  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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配单直通车
TLC372IPE4产品参数
型号:TLC372IPE4
Brand Name:Texas Instruments
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Obsolete
零件包装代码:DIP
包装说明:DIP, DIP8,.3
针数:8
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:5.5
放大器类型:COMPARATOR
最大平均偏置电流 (IIB):0.002 µA
25C 时的最大偏置电流 (IIB):0.002 µA
最大输入失调电压:7000 µV
JESD-30 代码:R-PDIP-T8
JESD-609代码:e4
长度:9.81 mm
功能数量:2
端子数量:8
最高工作温度:85 °C
最低工作温度:-40 °C
输出类型:OPEN-DRAIN
封装主体材料:PLASTIC/EPOXY
封装代码:DIP
封装等效代码:DIP8,.3
封装形状:RECTANGULAR
封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V
认证状态:Not Qualified
标称响应时间:650 ns
座面最大高度:5.08 mm
子类别:Comparator
最大压摆率:0.4 mA
供电电压上限:18 V
标称供电电压 (Vsup):5 V
表面贴装:NO
技术:CMOS
温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:THROUGH-HOLE
端子节距:2.54 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mm
Base Number Matches:1
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