TLC5620CDR原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

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产品型号TLC5620CDR的概述

芯片TLC5620CDR的概述 TLC5620CDR是一款由德州仪器（Texas Instruments）推出的数字电压输出数模转换器（DAC）。这款DAC具有出色的性能和灵活性，广泛应用于各种电子设备中。TLC5620CDR采用低功耗设计，适合便携式设备和电池供电的应用。它能够将数字信号转换为高精度的模拟电压信号，并提供多个输出通道，从而满足多种信号处理需求。芯片TLC5620CDR的详细参数 TLC5620CDR的主要技术参数包括： - 通道数：该DAC提供8个输出通道，可支持多路信号处理。 - 分辨率：具有10位分辨率，使得其在信号转换时能够提供较高的精确度。 - 输出电压范围：输出电压范围一般在0V到Vref之间，具体取决于供电电压和内部参考电压的设置。 - 最低功耗：静态功耗非常低，适合需要长时间工作的便携式设备。 - 通信接口：采用SPI（Serial Periphera...

产品型号TLC5620CDR的Datasheet PDF文件预览

TLC5620C, TLC5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001

N OR D PACKAGE

(TOP VIEW)

Four 8-Bit Voltage Output DACs

5-V Single-Supply Operation

Serial Interface

GND

REFA

REFB

REFC

REFD

DATA

CLK

High-Impedance Reference Inputs

Programmable 1 or 2 Times Output Range

Simultaneous Update Facility

Internal Power-On Reset

LDAC

DACA

DACB

DACC

DACD

LOAD

Low-Power Consumption

Half-Buffered Output

applications

Programmable Voltage Sources

Digitally Controlled Amplifiers/Attenuators

Mobile Communications

Automatic Test Equipment

Process Monitoring and Control

Signal Synthesis

description

The TLC5620C and TLC5620I are quadruple 8-bit voltage output digital-to-analog converters (DACs) with

buffered reference inputs (high impedance). The DACs produce an output voltage that ranges between either

one or two times the reference voltages and GND, and the DACs are monotonic. The device is simple to use,

running from a single supply of 5 V. A power-on reset function is incorporated to ensure repeatable start-up

conditions.

Digital control of the TLC5620C and TLC5620I are over a simple three-wire serial bus that is CMOS compatible

and easily interfaced to all popular microprocessor and microcontroller devices. The 11-bit command word

comprises eight bits of data, two DAC-select bits, and a range bit, the latter allowing selection between the times

1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be

written to the device, then all DAC outputs are updated simultaneously through control of LDAC. The digital

inputs feature Schmitt triggers for high noise immunity.

The 14-terminal small-outline (D) package allows digital control of analog functions in space-critical

applications. The TLC5620C is characterized for operation from 0°C to 70°C. The TLC5620I is characterized

for operation from –40°C to 85°C. The TLC5620C and TLC5620I do not require external trimming.

AVAILABLE OPTIONS

PACKAGE

SMALL OUTLINE

(D)

PLASTIC DIP

(N)

0°C to 70°C

TLC5620CD

TLC5620ID

TLC5620CN

TLC5620IN

–40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5620C, TLC5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001

functional block diagram

REFA

–

DAC

–

DACA

DACB

DACC

DACD

× 2

Latch

REFB

–

REFC

REFD

–

CLK

DATA

LOAD

Power-On

Reset

Serial

Interface

LDAC

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

CLK

Serial interface clock. The input digital data is shifted into the serial interface

DACA

DACB

DACC

DACD

DATA

DAC A analog output

DAC B analog output

DAC C analog output

DAC D analog output

Serial interface digital data input. The digital code for the DAC is clocked into the

serial interface register serially. Each data bit is clocked into the register on the

falling edge of the clock signal.

GND

Ground return and reference terminal

LDAC

Load DAC. When the LDAC signal is high, no DAC output updates occur when

the input digital data is read into the serial interface. The DAC outputs are only

updated when LDAC is taken from high to low.

LOAD

Serial Interface load control. When LDAC is low, the falling edge of the LOAD

signal latches the digital data into the output latch and immediately produces the

analog voltage at the DAC output terminal.

REFA

REFB

REFC

REFD

Reference voltage input to DAC A. This voltage defines the output analog range.

Reference voltage input to DAC B. This voltage defines the output analog range.

Reference voltage input to DAC C. This voltage defines the output analog range.

Reference voltage input to DAC D. This voltage defines the output analog range.

Positive supply voltage

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5620C, TLC5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001

detailed description

The TLC5620 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with

256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected

to the GND terminal and the other end is fed from the output of the reference input buffer. Monotonicity is

maintainedbyuseoftheresistorstrings. Linearitydependsuponthematchingoftheresistorelementsandupon

the performance of the output buffer. Since the inputs are buffered, the DACs always present a high-impedance

load to the reference source.

Each DAC output is buffered by a configurable-gain output amplifier that can be programmed to times 1 or times

2 gain.

On power up, the DACs are reset to CODE 0.

Each output voltage is given by:

CODE

V (DACA|B|C|D)

REF

(1 RNG bit value)

256

where CODE is in the range 0 to 255 and the range (RNG) bit is 0 or 1 within the serial control word.

Table 1. Ideal Output Transfer

•

OUTPUT VOLTAGE

GND

(1/256) × REF (1+RNG)

•

(127/256) × REF (1+RNG)

(128/256) × REF (1+RNG)

•

(255/256) × REF (1+RNG)

data interface

With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have

been clocked in, LOAD is pulsed low to transfer the data from the serial input register to the selected DAC as

shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low. When

LDAC is high during serial programming, the new value is stored within the device and can be transferred to

the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered most significant bit

(MSB) first. Data transfers using two 8-clock cycle periods are shown in Figures 3 and 4.

CLK

su(DATA-CLK)

su(LOAD-CLK)

D2 D1

su(CLK-LOAD)

v(DATA-CLK)

DATA

LOAD

A0 RNG

w(LOAD)

DAC Update

Figure 1. LOAD-Controlled Update (LDAC = Low)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5620C, TLC5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001

CLK

su(DATA-CLK)

v(DATA-CLK)

DATA

LOAD

LDAC

A0 RNG

su(LOAD-LDAC)

w(LDAC)

DAC Update

Figure 2. LDAC-Controlled Update

CLK Low

CLK

RNG

DATA

LOAD

LDAC

Figure 3. Load-Controlled Update Using 8-Bit Serial Word (LDAC = Low)

CLK Low

CLK

RNG

DATA

LOAD

LDAC

Figure 4. LDAC-Controlled Update Using 8-Bit Serial Word

Table 2 lists the A1 and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output

range. When RNG = low, the output range is between the applied reference voltage and GND, and when

RNG = high, the range is between twice the applied reference voltage and GND.

Table 2. Serial Input Decode

DAC UPDATED

DACA

DACB

DACC

DACD

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5620C, TLC5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001

linearity, offset, and gain error using single-end supplies

When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With

a positive offset voltage, the output voltage changes on the first code change. With a negative offset the output

voltage may not change with the first code depending on the magnitude of the offset voltage.

The output amplifier attempts to drive the output to a negative voltage. However, because the most negative

supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage then remains at zero until the input code value produces a sufficient positive output voltage

to overcome the negative offset voltage, resulting in the transfer function shown in Figure 5.

Output

Voltage

0 V

DAC Code

Negative

Offset

Figure 5. Effect of Negative Offset (Single Supply)

This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the

dotted line if the output buffer could drive below ground.

For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after

offset and full scale are adjusted out or accounted for in some way. However, single-supply operation does not

allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity

is measured between full-scale code and the lowest code that produces a positive output voltage. The code is

calculated from the maximum specification for the negative offset voltage.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5620C, TLC5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001

equivalent inputs and outputs

INPUT CIRCUIT

OUTPUT CIRCUIT

Input from

Decoded DAC

DAC

Voltage Output

Input

ref

× 1

84 kΩ

Output

Range

Select

To DAC

Resistor

String

× 2

SINK

60 µA

Typical

84 kΩ

GND

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage (V

– GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to V

Reference input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to V

Operating free-air temperature range, T : TLC5620C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

+ 0.3 V

TLC5620I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage, V

4.75

5.25

High-level input voltage, V

0.8 V

Low-level input voltage, V

0.8

Reference voltage, V [A|B|C|D]

–1.5

ref

Analog full-scale output voltage, R = 10 kΩ

3.5

Load resistance, R

kΩ

Setup time, data input, t

(see Figures 1 and 2)

su(DATA-CLK)

Valid time, data input valid after CLK↓, t

(see Figures 1 and 2)

v(DATA-CLK)

Setup time, CLK eleventh falling edge to LOAD, t

(see Figure 1)

su(CLK-LOAD)

(see Figure 1)

Setup time, LOAD↑ to CLK↓, t

su(LOAD-CLK)

Pulse duration, LOAD, t

Pulse duration, LDAC, t

(see Figure 1)

(see Figure 2)

250

w(LOAD)

w(LDAC)

Setup time, LOAD↑ to LDAC↓, t

(see Figure 2)

su(LOAD-LDAC)

CLK frequency

MHz

°C

TLC5620C

TLC5620I

Operating free-air temperature, T

–40

°C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5620C, TLC5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001

electrical characteristics over recommended operating free-air temperature range, V = 5 V ± 5%,

= 2 V, × 1 gain output range (unless otherwise noted)

ref

PARAMETER

High-level input current

Low-level input current

Output sink current

TEST CONDITIONS

MIN

TYP

MAX

±10

UNIT

µA

V = V

I DD

V = 0 V

µA

O(sink)

O(source)

Each DAC output

Output source current

Input capacitance

Reference input capacitance

Supply current

= 5 V

= 5 V,

= 2 V,

±10

±1

µA

Reference input current

Linearity error (end point corrected)

Differential-linearity error

Zero-scale error

= 2 V

ref

× 2 gain (see Note 1)

× 2 gain (see Note 2)

× 2 gain (see Note 3)

× 2 gain (see Note 4)

× 2 gain (see Note 5)

× 2 gain (see Note 6)

LSB

ref

±0.9

ref

Zero-scale-error temperature coefficient

Full-scale error

ref

µV/°C

ref

±60

Full-scale-error temperature coefficient

Power-supply rejection ratio

ref

±25

µV/°C

mV/V

PSRR

See Notes 7 and 8

0.5

NOTES: 1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects

of zero code and full-scale errors).

2. Differentialnonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes.

Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

4. Zero-scale-error temperature coefficient is given by: ZSETC = [ZSE(T

) – ZSE(T

)]/V × 10 /(T

min ref max

– T

min

max

5. Full-scale error is the deviation from the ideal full-scale output (V – 1 LSB) with an output load of 10 kΩ.

ref

6. Full-scale-error temperature coefficient is given by: FSETC = [FSE(T

7. Zero-scale-error rejection ratio (ZSE RR) is measured by varying the V

this signal imposed on the zero-code output voltage.

) – FSE (T

)]/V × 10 /(T

min ref max

– T

min

max

from 4.5 V to 5.5 V dc and measuring the proportion of

8. Full-scale-error rejection ratio (FSE RR) is measured by varying the V

this signal imposed on the full-scale output voltage.

from 4.5 V to 5.5 V dc and measuring the proportion of

operating characteristics over recommended operating free-air temperature range, V = 5 V ± 5%,

= 2 V, × 1 gain output range (unless otherwise noted)

ref

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V/µs

µs

Output slew rate

= 100 pF,

= 10 kΩ

Output settling time

To ±0.5 LSB,

= 100 pF,

= 10 kΩ, See Note 9

Large-signal bandwidth

Digital crosstalk

Measured at –3 dB point

100

–50

–60

100

kHz

CLK = 1-MHz square wave measured at DACA-DACD

Reference feedthrough

Channel-to-channel isolation

Reference input bandwidth

See Note 10

See Note 11

See Note 12

kHz

NOTES: 9. Settling time is the time between a LOAD falling edge and the DAC output reaching full scale voltage within +/–0.5 LSB starting from

an initial output voltage equal to zero.

10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a V input = 1 V dc + 1 V at 10 kHz.

ref pp

11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex

with V input = 1 V dc + 1 V at 10 kHz.

ref pp

12. Reference bandwidth is the –3 dB bandwidth with an input at V = 1.25 V dc + 2 V and with a full-scale digital-input code.

ref

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5620C, TLC5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001

PARAMETER MEASUREMENT INFORMATION

TLC5620

DACA

DACB

•

10 kΩ

= 100 pF

DACD

Figure 6. Slew, Settling Time, and Linearity Measurements

TYPICAL CHARACTERISTICS

NEGATIVE FALL AND SETTLING TIME

POSITIVE RISE AND SETTLING TIME

LDAC

= 5 V

= 25°C

= 5 V

= 25°C

Code FF to 00 Hex

Code 00 to FF Hex

Range = ×2

= 2 V

ref

= 2 V

10 12

t – Time – µs

Figure 7

Figure 8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5620C, TLC5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001

TYPICAL CHARACTERISTICS

DAC OUTPUT VOLTAGE

OUTPUT LOAD

3.5

4.8

4.6

4.4

4.2

2.5

3.8

3.6

1.5

= 5 V,

= 2.5 V,

ref

3.4

3.2

= 5 V,

= 3.5 V,

Range = 2x

ref

0.5

Range = 1x

10 20 30 40 50 60 70 80 90 100

– Output Load – kΩ

Figure 9

Figure 10

OUTPUT SOURCE CURRENT

SUPPLY CURRENT

OUTPUT VOLTAGE

TEMPERATURE

1.2

1.15

1.1

= 5 V

= 25°C

ref

= 2 V

Range = ×2

Input Code = 255

= 5 V

2 V

ref

Range = ×2

Input Code = 255

1.05

0.95

0.9

0.85

0.8

–50

100

t – Temperature – °C

– Output Voltage – V

Figure 11

Figure 12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5620C, TLC5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001

TYPICAL CHARACTERISTICS

RELATIVE GAIN

FREQUENCY

–2

–4

–10

–6

–8

–20

–30

–40

–10

–12

–14

–16

= 5 V

= 25°C

= 2 Vdc + 0.5 V

ref

Input Code = 255

= 5 V

= 25°C

–50

–60

ref

= 1.25 Vdc + 2 V

–18

–20

Input Code = 255

100

1000

10000

100

1000

f – Frequency – kHz

Figure 13

Figure 14

APPLICATION INFORMATION

TLC5620

DACA

DACB

•

DACD

NOTE A: Resistor R

10 kΩ

Figure 15. Output Buffering Scheme

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5620C, TLC5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001

MECHANICAL DATA

D (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

PINS **

0.050 (1,27)

DIM

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

0.197

(5,00)

0.344

(8,75)

0.394

(10,00)

A MAX

0.189

(4,80)

0.337

(8,55)

0.386

(9,80)

A MIN

0.244 (6,20)

0.228 (5,80)

0.008 (0,20) NOM

0.157 (4,00)

0.150 (3,81)

Gage Plane

0.010 (0,25)

0°–8°

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.004 (0,10)

0.010 (0,25)

0.004 (0,10)

0.069 (1,75) MAX

4040047/B 10/94

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Four center pins are connected to die mount pad.

E. Falls within JEDEC MS-012

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5620C, TLC5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001

MECHANICAL DATA

N (R-PDIP-T**)

PLASTIC DUAL-IN-LINE PACKAGE

16 PIN SHOWN

PINS **

DIM

0.775

(19,69)

0.775

(19,69)

0.920

(23.37)

0.975

(24,77)

A MAX

0.745

(18,92)

0.745

(18,92)

0.850

(21.59)

0.940

(23,88)

A MIN

0.260 (6,60)

0.240 (6,10)

0.070 (1,78) MAX

0.020 (0,51) MIN

0.310 (7,87)

0.290 (7,37)

0.035 (0,89) MAX

0.200 (5,08) MAX

Seating Plane

0.125 (3,18) MIN

0.100 (2,54)

0°–15°

0.021 (0,53)

0.015 (0,38)

0.010 (0,25)

0.010 (0,25) NOM

14/18 PIN ONLY

4040049/C 08/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

18-Feb-2005

PACKAGING INFORMATION

Orderable Device

TLC5620CD

TLC5620CDR

TLC5620CN

TLC5620ID

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

2500

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1YEAR/

Level-1-220C-UNLIM

SOIC

PDIP

SOIC

PDIP

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1YEAR/

Level-1-220C-UNLIM

Pb-Free

(RoHS)

CU NIPDAU Level-NA-NA-NA

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1YEAR/

Level-1-220C-UNLIM

TLC5620IDR

TLC5620IN

2500

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1YEAR/

Level-1-220C-UNLIM

Pb-Free

(RoHS)

CU NIPDAU Level-NA-NA-NA

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

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Addendum-Page 1

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TLC5620CDR产品参数

型号:	TLC5620CDR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	SOIC
包装说明：	SOP, SOP14,.25
针数：	14
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	0.66
最大模拟输出电压：	7 V
最小模拟输出电压：
转换器类型：	D/A CONVERTER
输入位码：	BINARY
输入格式：	SERIAL
JESD-30 代码：	R-PDSO-G14
JESD-609代码：	e4
长度：	8.65 mm
最大线性误差 (EL)：	0.3906%
湿度敏感等级：	1
位数：	8
功能数量：	1
端子数量：	14
最高工作温度：	70 °C
最低工作温度：
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP14,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
电源：	5 V
认证状态：	Not Qualified
采样速率：	0.048 MHz
座面最大高度：	1.75 mm
标称安定时间 (tstl)：	10 µs
子类别：	Other Converters
最大压摆率：	2 mA
标称供电电压：	5 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.91 mm
Base Number Matches：	1

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