欢迎访问ic37.com |
会员登录 免费注册
发布采购
所在地: 型号: 精确
  • 批量询价
  •  
  • 供应商
  • 型号
  • 数量
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
更多
  • TLK2201B1图
  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站6年以上
  • TLK2201B1
  • 数量6500 
  • 厂家TI 
  • 封装QFP 
  • 批号24+ 
  • 全新原装★真实库存★含13点增值税票!
  • QQ:2885134615QQ:2885134615 复制
    QQ:2353549508QQ:2353549508 复制
  • 0755-83201583 QQ:2885134615QQ:2353549508
  • TLK2201B1图
  • HECC GROUP CO.,LIMITED

     该会员已使用本站17年以上
  • TLK2201B1
  • 数量278 
  • 厂家TI 
  • 封装QFP 
  • 批号24+ 
  • 假一罚万,全新原装库存现货,可长期订货
  • QQ:800888908QQ:800888908 复制
  • 755-83950019 QQ:800888908
  • TLK2201B1图
  • 深圳市芯福林电子有限公司

     该会员已使用本站15年以上
  • TLK2201B1
  • 数量65000 
  • 厂家TEXASIN 
  • 封装QFP 
  • 批号23+ 
  • 真实库存全新原装正品!代理此型号
  • QQ:2881495753QQ:2881495753 复制
  • 0755-23605827 QQ:2881495753
  • TLK2201B1图
  • 深圳市创思克科技有限公司

     该会员已使用本站2年以上
  • TLK2201B1
  • 数量8500 
  • 厂家N/A 
  • 封装QFP 
  • 批号20+ 
  • 全新原装挺实单欢迎来撩/可开票
  • QQ:1092793871QQ:1092793871 复制
  • -0755-88910020 QQ:1092793871
  • TLK2201B1图
  • 深圳市一线半导体有限公司

     该会员已使用本站11年以上
  • TLK2201B1
  • 数量14500 
  • 厂家原厂品牌 
  • 封装原厂外观 
  • 批号 
  • 全新原装部分现货其他订货
  • QQ:2881493920QQ:2881493920 复制
    QQ:2881493921QQ:2881493921 复制
  • 0755-88608801多线 QQ:2881493920QQ:2881493921

产品型号TLK2201BI的Datasheet PDF文件预览

ꢀ ꢁꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢇ ꢀꢁ ꢂꢃ ꢃꢄ ꢅꢆ ꢈ  
ꢉꢀ ꢊꢉ ꢋꢌꢉꢀ ꢀ ꢋꢍꢌꢎꢏ ꢉ ꢈꢐ ꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
D
D
D
D
1 to 1.6 Gigabits Per Second (Gbps)  
Serializer/Deserializer (TLK2201B)  
D
Industrial Temperature Range From −40°C  
to 85°C (TLK2201BI)  
1.2 to 1.6 Gigabits Per Second (Gbps)  
Serializer/Deserializer (TLK2201BI)  
D
D
D
D
D
D
D
D
D
IEEE 802.3 Gigabit Ethernet Compliant  
Advanced 0.25 µm CMOS Technology  
No External Filter Capacitors Required  
Comprehensive Suite of Built-In Testability  
IEEE 1149.1 JTAG Support  
Low Power Consumption <200 mW  
at 1.25 Gbps  
LVPECL Compatible Differential I/O on High  
Speed Interface  
2.5-V Supply Voltage for Lowest Power  
Operation  
D
Single Monolithic PLL Design  
D
Support For 10 Bit Interface or Reduced  
Interface 5 Bit DDR (Double Data Rate)  
Clocking  
3.3-V Tolerant on LVTTL Inputs  
Hot Plug Protection  
64-Pin VQFP With Thermally Enhanced  
Package (PowerPAD)  
D
Receiver Differential Input Thresholds  
200 mV Minimum  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
GND  
TD0  
TD1  
TD2  
VDD  
TD3  
TD4  
TD5  
TD6  
VDD  
JTDI  
1
2
3
4
5
6
7
8
9
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
SYNC/PASS  
GND  
RD0  
RD1  
RD2  
VDD  
RD3  
RD4  
RD5  
10  
TD7 11  
TD8 12  
TD9 13  
38 RD6  
37 VDD  
36  
35  
34  
33  
RD7  
RD8  
RD9  
GND  
14  
15  
16  
GND  
MODESEL  
PRBSEN  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
description  
The TLK2201B and TLK2201BI gigabit ethernet transceivers provide for ultrahigh-speed full-duplex  
point-to-point data transmissions. These devices are based on the timing requirements of the 10-bit interface  
specification by the IEEE 802.3 Gigabit Ethernet specification. The TLK2201B supports data rates from 1.0  
Gbps through 1.6 Gbps and the TLK2201BI supports data rates from 1.2 Gbps through 1.6 Gbps.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PowerPAD is a trademark of Texas Instruments.  
ꢀꢠ  
Copyright 2003, Texas Instruments Incorporated  
ꢜ ꢠ ꢝ ꢜꢕ ꢖꢪ ꢘꢗ ꢛ ꢣꢣ ꢡꢛ ꢙ ꢛ ꢚ ꢠ ꢜ ꢠ ꢙ ꢝ ꢥ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁ ꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢈ  
ꢉ ꢀ ꢊ ꢉꢋ ꢌ ꢉꢀ ꢀ ꢋ ꢍ ꢌꢎ ꢏꢉ ꢈ ꢐꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
description (continued)  
The primary application of these devices is to provide building blocks for point-to-point baseband data  
transmission over controlled impedance media of 50 or 75 . The transmission media can be printed-circuit  
board traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent  
upon the attenuation characteristics of the media and the noise coupling to the environment.  
The TLK2201B and TLK2201BI perform the data serialization, deserialization, and clock extraction functions  
for a physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps  
of data bandwidth over a copper or optical media interface.  
The TLK2201B and TLK2201BI support both the defined 10-bit interface (TBI) and a reduced 5-bit interface  
utilizing double data rate (DDR) clocking. In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit  
wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially  
at PECL compatible voltage levels. The SERDES extracts clock information from the input serial stream and  
deserializes the data, outputting a parallel 10-bit data byte.  
In the DDR mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned to both the rising and  
falling edge of the reference clock. The data is clocked most significant bit first, (bits 0 − 4 of the 8b/10b encoded  
data) on the rising edge of the clock and the least significant bits (bits 5 − 9 of the 8b/10b encoded data) are  
clocked on the falling edge of the clock.  
The TLK2201B and TLK2201BI provide a comprehensive series of built-in tests for self-test purposes including  
loopback and pseudorandom binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port  
is also supported.  
The TLK2201B and TLK2201BI are housed in a high performance, thermally enhanced, 64-pin VQFP  
PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note  
that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical  
conductor. It is recommended that the TLK2201B and TLK2201BI PowerPADs be soldered to the thermal land  
on the board.  
The TLK2201B is characterized for operation from 0°C to 70°C. The TLK2201BI is characterized for operation  
from −40°C to 85°C.  
The TLK2201B and TLK2201BI use a 2.5-V supply. The I/O section is 3.3-V compatible. With the 2.5-V supply  
the chipset is very power-efficient, dissipating less than 200 mW typical power when operating at 1.25 Gbps.  
The TLK2201B and TLK2201BI are designed to be hot plug capable. A power-on reset causes RBC0, RBC1,  
the parallel output signal terminals, TXP, and TXN to be held in high-impedance state.  
differences between TLK2201B, TLK2201BI, and TNETE2201  
The TLK2201B and TLK2201BI are the functional equivalent of the TNETE2201. There are several differences  
between the devices as noted below. Refer to Figure 12 in the application information section for an example  
of a typical application circuit.  
D
D
The V  
is 2.5 V for the TLK2201B and TLK2201BI vs 3.3 V for TNETE2201.  
CC  
The PLL filter capacitors on pins 16, 17, 48, and 49 of the TNETE2201 are no longer required. The  
TLK2201B and TLK2201BI uses these pins to provide added test capabilities. The capacitors, if present,  
do not affect the operation of the device.  
D
No pulldown resistors are required on the TXP/TXN outputs.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢇ ꢀꢁ ꢂꢃ ꢃꢄ ꢅꢆ ꢈ  
ꢉꢀ ꢊꢉ ꢋꢌꢉꢀ ꢀ ꢋꢍꢌꢎꢏ ꢉ ꢈꢐ ꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
block diagram  
PRBSEN  
LOOPEN  
PRBS  
Generator  
TXP  
TXN  
2:1  
MUX  
Parallel to  
Serial  
10 Bit  
Registers  
TD(0−9)  
Clock  
Phase Generator  
REFCLK  
MODESEL  
Control  
Logic  
ENABLE  
TESTEN  
Clock  
Interpolator  
and  
Clock Extraction  
2:1  
MUX  
PRBS  
RBC1  
Verification  
RBC0  
SYNC/PASS  
Clock  
Serial to Parallel  
and  
Comma Detect  
2:1  
MUX  
Data  
RD(0−9)  
RXP  
RXN  
SYNCEN  
LOS  
RBCMODE  
JTMS  
JTAG  
Control  
Register  
JTDO  
JTRSTN  
JTDI  
TCK  
detailed description  
data transmission  
These devices support both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing DDR  
clocking. When MODESEL is low, the TBI mode is selected. When MODESEL is high, the DDR mode is  
selected.  
In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data,  
TD0−TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock  
by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted  
sequentially bit 0 through 9 over the differential high-speed I/O channel.  
In the DDR mode, the transmitter accepts 5-bit wide 8b/10b encoded data on pins TD0−TD4. In this mode data  
is aligned to both the rising and falling edges of REFCLK. The data is then formed into a 10-bit wide word and  
sent to the serializer. The rising edge REFCLK clocks in bit 0−4, and the falling edge of REFCLK clocks in bits  
5−9. ( Bit 0 is the first bit transmitted).  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁ ꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢈ  
ꢉ ꢀ ꢊ ꢉꢋ ꢌ ꢉꢀ ꢀ ꢋ ꢍ ꢌꢎ ꢏꢉ ꢈ ꢐꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
detailed description (continued)  
transmission latency  
Data transmission latency is defined as the delay from the initial 10-bit word load to the serial transmission of  
bit 9. The minimum latency in TBI mode is 19 bit times. The maximum latency in TBI mode is 20 bit times. The  
minimum latency in DDR mode is 29 bit times, and maximum latency in DDR mode is 30 bit times.  
10 Bit Code  
b9  
TXP, TXN  
t
d(Tx latency)  
10 Bit Code  
TD(0−9)  
REFCLK  
Figure 1. Transmitter Latency Full Rate Mode  
data reception  
The receiver portion deserializes the differential serial data. The serial data is retimed based on an interpolated  
clock generated from the reference clock. The serial data is then aligned to the 10-bit word boundaries and  
presented to the protocol controller along with receive byte clocks (RBC0, RBC1).  
receiver clock select mode  
There are two modes of operation for the parallel busses. 1)The 10-bit (TBI) mode and 2) 5-bit (DDR) mode.  
When in TBI mode, there are two user-selectable clock modes that are controlled by the RBCMODE terminal.  
1) Full-rate clock on RBC0 and 2) Half-rate clocks on RBC0 and RBC1. When in the DDR mode, only a full-rate  
clock is available on RBC0; refer to Table 1.  
Table 1. Mode Selection  
MODESEL  
RBCMODE  
MODE  
FREQUENCY  
(TLK2201B)  
FREQUENCY  
(TLK2201BI)  
0
0
1
1
0
1
0
1
TBI half-rate  
TBI full-rate  
DDR  
100−125 MHz  
100−160 MHz  
100−125 MHz  
100−125 MHz  
120−125 MHz  
120−160 MHz  
120−125 MHz  
120−125 MHz  
DDR  
In the half-rate mode, two receive byte clocks (RBC0 and RBC1) are 180 degrees out of phase and operate  
at one-half the data rate. The clocks are generated by dividing down the recovered clock. The received data  
is output with respect to the two receive byte clocks (RBC0, RBC1) allowing a protocol device to clock the  
parallel bytes using the RBC0 and RBC1 rising edges. The outputs to the protocol device, byte 0 of the received  
data valid on the rising edge of RBC1. Refer to the timing diagram shown in Figure 2.  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢇ ꢀꢁ ꢂꢃ ꢃꢄ ꢅꢆ ꢈ  
ꢉꢀ ꢊꢉ ꢋꢌꢉꢀ ꢀ ꢋꢍꢌꢎꢏ ꢉ ꢈꢐ ꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
receiver clock select mode (continued)  
t
d(S)  
RBC0  
t
d(S)  
RBC1  
SYNC  
t
d(H)  
t
d(H)  
RD(0−9)  
K28.5  
DXX.X  
DXX.X  
DXX.X  
K28.5  
DXX.X  
Figure 2. Synchronous Timing Characteristics Waveforms (TBI half-rate mode)  
In the normal-rate mode, only RBC0 is used and operates at full data rate (i.e., 1.25 Gbps data rate produces  
a 125 MHz clock). The received data is output with respect to the rising edge of RBC0. RBC1 is low in this mode.  
Refer to the timing diagram shown in Figure 3.  
RBC0  
t
t
d(H)  
d(S)  
SYNC  
RD(0−9)  
K28.5  
DXX.X  
DXX.X  
DXX.X  
K28.5  
DXX.X  
Figure 3. Synchronous Timing Characteristics Waveforms (TBI full-rate mode)  
In the double data rate mode, the receiver presents the data on both the rising and falling edges of RBC0. RBC1  
is low impedance. The data is clocked bit-0 first, and aligned to the rising edge of RBC0. Refer to the timing  
diagram shown in Figure 4.  
t
d(S)  
RBC0  
t
d(S)  
t
d(H)  
t
d(H)  
SYNC  
RD(0−4)  
K28.5  
K28.5 DXX.X DXX.X DXX.X DXX.X DXX.X DXX.X K28.5 K28.5 DXX.X  
Bits 0−4 Bits 5−9  
Figure 4. Synchronous Timing Characteristics Waveforms (DDR mode)  
The receiver clock interpolator can lock to the incoming data without the need for a lock-to-reference preset.  
The received serial data rate (RXP and RXN) is at the same baud rate as the transmitted data stream, 0.02%  
(200 PPM) for proper operation (see page 11).  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁ ꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢈ  
ꢉ ꢀ ꢊ ꢉꢋ ꢌ ꢉꢀ ꢀ ꢋ ꢍ ꢌꢎ ꢏꢉ ꢈ ꢐꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
receiver word alignment  
These devices use the IEEE 802.3 Gigabit Ethernet defined 10-bit K28.5 character (comma character) word  
alignment scheme. The following sections explain how this scheme works and how it realigns itself.  
comma character on expected boundary  
These devices provide 10-bit K28.5 character recognition and word alignment. The 10-bit word alignment is  
enabled by forcing the SYNCEN terminal high. This enables the function that examines and compares serial  
input data to the seven bit synchronization pattern. The K28.5 character is defined by the 8-bit/10-bit coding  
scheme as a pattern consisting of 0011111010 (a negative number beginning with disparity) with the 7 MSBs  
(0011111), referred to as the comma character. The K28.5 character was implemented specifically for aligning  
data words. As long as the K28.5 character falls within the expected 10-bit boundary, the received 10-bit data  
is properly aligned and data realignment is not required. Figure 2 shows the timing characteristics of RBC0,  
RBC1, SYNC and RD0−RD9 while synchronized. (Note: the K28.5 character is valid on the rising edge of  
RBC1).  
comma character not on expected boundary  
If synchronization is enabled and a K28.5 character straddles the expected 10-bit word boundary, then word  
realignment is necessary. Realignment or shifting the 10-bit word boundary truncates the character following  
the misaligned K28.5, but the following K28.5 and all subsequent data is aligned properly as shown in  
Figure 5. The RBC0 and RBC1 pulse widths are stretched or stalled in their current state during realignment.  
With this design the maximum stretch that occurs is 20 bit times. This occurs during a worst case scenario when  
the K28.5 is aligned to the falling edge of RBC1 instead of the rising edge. Figure 5 shows the timing  
characteristics of the data realignment.  
31 Bit  
Times  
30 Bit  
Times (Max)  
Max Receive  
Path Latency  
K28.5  
DXX.X  
K28.5  
DXX.X  
DXX.X  
K28.5  
DXX.X  
DXX.X  
INPUT DATA  
RBC0  
RBC1  
Worst Case  
Misaligned K28.5  
Corrupt Data  
DXX.X  
Misalignment Corrected  
DXX.X  
RD(0−9)  
SYNC  
DXX.X  
DXX.X  
K28.5  
DXX.X  
K28.5  
DXX.X  
K28.5  
DXX.X  
Figure 5. Word Realignment Timing Characteristics Waveforms  
Systems that do not require framed data may disable byte alignment by tying SYNCEN low.  
When a SYNC character is detected, the SYNC signal is brought high and is aligned with the K28.5 character.  
The duration of the SYNC pulse is equal to the duration of the data when in TBI mode. When in DDR mode the  
SYNC pulse is present for the entire RBC0 period.  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢇ ꢀꢁ ꢂꢃ ꢃꢄ ꢅꢆ ꢈ  
ꢉꢀ ꢊꢉ ꢋꢌꢉꢀ ꢀ ꢋꢍꢌꢎꢏ ꢉ ꢈꢐ ꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
data reception latency  
The serial to parallel data latency is the time from when the first bit arrives at the receiver until it is output in the  
aligned parallel word with RD0 received as first bit. The minimum latency in TBI mode is 21 bit times and the  
maximum latency is 31 bit times. The minimum latency in DDR mode is 27 bit times and maximum latency is  
34 bit times.  
data reception latency (continued)  
10 Bit Code  
RXP, RXN  
t
d(Rx latency)  
RD(0−9)  
RBC0  
10 Bit Code  
Figure 6. Receiver Latency − TBI Normal Mode Shown  
loss of signal detection  
These devices have a loss of signal (LOS) detection circuit for conditions where the incoming signal no longer  
has sufficient voltage level to keep the clock recovery circuit in lock. The LOS is intended to be an indication  
of gross signal error conditions, such as a detached cable or no signal being transmitted, and not an indication  
of signal coding health. Under a PRBS serial input pattern, LOS is high for signal amplitudes greater than  
150 mV. The LOS is low for all amplitudes below 50 mV. Between 50 mV and 150 mV, LOS is undetermined.  
testability  
The loopback function provides for at-speed testing of the transmit/receive portions of the circuitry. The enable  
function allows for all circuitry to be disabled so that an Iddq test can be performed. The PRBS function also  
allows for a BIST( built-in self test). The terminal setting, TESTEN high, enables the test mode. The terminal  
TESTEN has an internal pulldown resistor, so it defaults to normal operation. The TESTEN is only used for  
factory testing, and is not intended for the end-user.  
loopback testing  
The transceiver can provide a self-test function by enabling (LOOPEN to high level) the internal loopback path.  
Enabling this function causes serial transmitted data to be routed internally to the receiver. The parallel data  
output can be compared to the parallel input data for functional verification. (The external differential output is  
held in a high-impedance state during the loopback testing.)  
enable function  
When held low, ENABLE disables all quiescent power in both the analog and digital circuitry. This allows an  
ultralow-power idle state when the link is not active.  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁ ꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢈ  
ꢉ ꢀ ꢊ ꢉꢋ ꢌ ꢉꢀ ꢀ ꢋ ꢍ ꢌꢎ ꢏꢉ ꢈ ꢐꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
PRBS function  
7
These devices have a built-in 2 −1 PRBS function. When the PRBSEN control bit is set high, the PRBS test  
is enabled. A PRBS is generated and fed into the 10-bit parallel transmitter input bus. Data from the normal  
parallel input source is ignored during PRBS test mode. The PRBS pattern is then fed through the transmit  
circuitry as if it were normal data and sent out to the transmitter. The output can be sent to a (BERT) bit error  
rate tester or to the receiver of another TLK2201B or TLK2201BI. Since the PRBS is not really random and is  
really a predetermined sequence of ones and zeros, the data can be captured and checked for errors by a BERT.  
These devices also have a built-in BERT function on the receiver side that is enabled by PRBSEN. It can receive  
a PRBS pattern and check for errors, and then reports the errors by forcing the SYNC/PASS terminal low. When  
PRBS is enabled, RBCMODE and MODESEL are ignored. The device operates in TBI mode with a full-rate  
clock on RBC0. The PRBS testing supports two modes (normal and latched), which are controlled by the  
SYNCEN input. When SYNCEN is low, the result of the PRBS bit error rate test is passed to the SYNC/PASS  
terminal. When SYNCEN is high the result of the PRBS verification is latched on the SYNC/PASS output (i.e.,  
a single failure forces SYNC/PASS to remain low).  
Terminal Functions  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
NO.  
SIGNAL  
TXP  
TXN  
62  
61  
PECL Differential output transmit. TXP and TXN are differential serial outputs that interface to a copper or an  
O
optical I/F module. TXP and TXN are put in a high-impedance state when LOOPEN is high and are active  
when LOOPEN is low.  
RXP  
RXN  
54  
52  
PECL Differential input receive. RXP and RXN together are the differential serial input interface from a copper  
I
or an optical I/F module.  
REFCLK  
22  
I
Reference clock. REFCLK is an external input clock that synchronizes the receiver and transmitter  
interface (100 MHz to 160 MHz). The transmitter uses this clock to register the input data (TD0−TD9)  
for serialization.  
In the TBI mode that data is registered on the rising edge of REFCLK.  
In the DDR mode, the data is registered on both the rising and falling edges of REFCLK with the most  
significant bits aligned to the rising edge of REFCLK.  
TD0−TD9  
2−4, 6−9,  
11−13  
I
Transmit data. When in the TBI mode (MODESEL = low) these inputs carry 10-bit parallel data output  
from a protocol device to the transceiver for serialization and transmission. This 10-bit parallel data is  
clocked into the transceiver on the rising edge of REFCLK and transmitted as a serial stream with TD0  
sent as the first bit.  
When in the DDR mode (MODESEL = high) only TD0−TD4 are valid. The 5-bit parallel data is clocked  
into the transceiver on the rising and falling edge of REFCLK and transmitted as a serial stream with TD0  
sent as the first bit.  
RD0−RD9  
45, 44, 43,  
41, 40, 39,  
38, 36, 35,  
34  
O
O
Receive data. When in TBI mode (MODESEL = low) these outputs carry 10-bit parallel data output from  
the transceiver to the protocol layer. The data is referenced to terminals RBC0 and RBC1, depending  
on the receive clock mode selected. RD0 is the first bit received.  
When in the DDR mode (MODESEL = high) only RD0−RD4 are valid. RD5−RD9 are held low. The 5-bit  
parallel data is clocked out of the transceiver on the rising edge of RBC0.  
RBC0  
RBC1  
31  
30  
Receive byte clock. RBC0 and RBC1 are recovered clocks used for synchronizing the 10-bit output data  
on RD0−RD9. The operation of these clocks is dependent upon the receive clock mode selected.  
In the half-rate mode, the 10-bit output data words are valid on the rising edges of RBC0 and RBC1.  
These clocks are adjusted to half-word boundaries in conjunction with synchronous detect. The clocks  
are always expanded during data realignment and never slivered or truncated. RBC0 registers bytes  
1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data.  
In the normal rate mode, only RBC0 is valid and operates at 1/10 the serial data rate. Data is aligned  
to the rising edge.  
In the DDR mode, only RBC0 is valid and operates at 1/10 the serial data rate. Data is aligned to both  
the rising and falling edges.  
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢇ ꢀꢁ ꢂꢃ ꢃꢄ ꢅꢆ ꢈ  
ꢉꢀ ꢊꢉ ꢋꢌꢉꢀ ꢀ ꢋꢍꢌꢎꢏ ꢉ ꢈꢐ ꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
Terminal Functions (Continued)  
TERMINAL  
NAME NO.  
SIGNAL (Continued)  
I/O  
DESCRIPTION  
RBCMODE  
32  
I
Receive clock mode select. When RBCMODE and MODESEL are low, half-rate clocks are output on  
RBC0 and RBC1. When MODESEL is low and RBCMODE is high, a full baud-rate clock is output on  
RBC0 and RBC1 is held low. When MODESEL is high, RBCMODE is ignored and a full baud-rate clock is  
output on RBC0 and RBC1 is held low.  
P/D  
SYNCEN  
24  
I
Synchronous function enable. When SYNCEN is high, the internal synchronization function is activated.  
When this function is activated, the transceiver detects the K28.5 comma character (0011111 negative  
beginning disparity) in the serial data stream and realigns data on byte boundaries if required. When  
SYNCEN is low, serial input data is unframed in RD0 − RD9.  
P/U  
SYNC/PASS  
LOS  
47  
26  
O
O
Synchronous detect. The SYNC output is asserted high upon detection of the comma pattern in the serial  
data path. SYNC pulses are output only when SYNCEN is activated (asserted high). In PRBS test mode  
(PRBSEN=high), SYNC/PASS outputs the status of the PRBS test results (high=pass).  
Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN.  
If magnitude of RXP−RXN > 150 mV, LOS = 1, valid input signal  
If magnitude of RXP−RXN < 150 mV and > 50 mV, LOS is undefined  
If magnitude of RXP−RXN < 50 mV, LOS = 0, loss of signal  
MODESEL  
15  
19  
I
Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR interface. When  
low the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode is selected. The default  
mode is the TBI.  
P/D  
TEST  
LOOPEN  
I
Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The transmitted  
serial data is directly routed to the inputs of the receiver. This provides a self-test capability in conjunction  
with the protocol device. The TXP and TXN outputs are held in a high-impedance state during the  
loop-back test. LOOPEN is held low during standard operational state with external serial outputs and  
inputs active.  
P/D  
TCK  
JTDI  
49  
48  
I
Test clock. IEEE1149.1 (JTAG)  
I
Test data input. IEEE1149.1 (JTAG)  
P/U  
JTDO  
27  
56  
O
Test data output. IEEE1149.1 (JTAG)  
Reset signal. IEEE1149.1 (JTAG)  
JTRSTN  
I
P/U  
JTMS  
55  
28  
I
Test mode select. IEEE1149.1 (JTAG)  
P/U  
ENABLE  
I
When this terminal is low, the device is disabled for Iddq testing. RD0 − RD9, RBCn, TXP, and TXN are  
high impedance. The pullup and pulldown resistors on any input are disabled. When ENABLE is high, the  
device operates normally.  
P/U  
PRBSEN  
TESTEN  
16  
17  
I
PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS verification  
circuit in the receive side is also enabled. A PRBS signal can be fed to the receive inputs and checked for  
errors, that are reported by the SYNC/PASS terminal indicating low.  
P/D  
I
Manufacturing test terminal  
P/D  
POWER  
VDD  
5, 10, 20,  
23, 29, 37,  
42, 50, 63  
Supply Digital logic power. Provides power for all digital circuitry and digital I/O buffers.  
VDDA  
53, 57, 59, Supply Analog power. VDDA provides power for the high-speed analog circuits, receiver, and transmitter  
60  
VDDPLL  
18  
Supply PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering.  
P/D = Internal pulldown  
P/U = Internal pullup  
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁ ꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢈ  
ꢉ ꢀ ꢊ ꢉꢋ ꢌ ꢉꢀ ꢀ ꢋ ꢍ ꢌꢎ ꢏꢉ ꢈ ꢐꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
Terminal Functions (Continued)  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
GROUND  
GNDA  
NO.  
51,58  
Ground Analog ground. GNDA provides a ground for the high-speed analog circuits, RX and TX.  
Ground Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.  
GND  
1, 14, 21,  
25, 33, 46  
GNDPLL  
64  
Ground PLL ground. Provides a ground for the PLL circuitry.  
absolute maximum ratings over operating free-air temperature (unless otherwise noted)  
Supply voltage, V  
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 3 V  
DD  
Input voltage range at TTL terminals, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V  
Input voltage range at any other terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V  
Storage temperature, T  
I
+0.3 V  
DD  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
stg  
Electrostatic discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDM: 1 kV, HBM:2 kV  
Characterized free-air operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
Characterized free-air operating temperature range: TLK2201B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
TLK2201BI . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.  
DISSIPATION RATING TABLE  
T
A
25°C  
OPERATING FACTOR  
T = 70°C  
A
POWER RATING  
PACKAGE  
POWER RATING  
ABOVE T = 25°C  
A
§
RCP64  
5.25 W  
46.58 mW/°C  
23.70 mW/°C  
13.19 mW/°C  
2.89 W  
RCP64  
3.17 W  
1.74 W  
#
RCP64  
2.01 W  
1.11 W  
§
#
This is the inverse of the traditional junction-to-ambient thermal resistance (R  
2 oz. Trace and copper pad with solder.  
2 oz. Trace and copper pad without solder.  
Standard JEDEC high-K board  
).  
θJA  
NOTE: For more information, refer to TI application note PowerPAD Thermally Enhanced  
Package, TI literature number SLMA002.  
thermal characteristics  
PARAMETER  
TEST CONDITION  
MIN  
TYP  
MAX  
UNIT  
Board-mounted, no air flow, high conductivity TI  
recommended test board, chip soldered or greased to  
thermal land  
21.47  
Board-mounted, no air flow, high conductivity TI  
recommended test board with thermal land but no  
solder or grease thermal connection to thermal land  
R
R
Junction-to-free-air thermal resistance  
°C/W  
θJA  
θJC  
42.20  
75.83  
0.38  
Board-mounted, no air flow, JEDEC test board  
Board-mounted, no air flow, high conductivity TI  
recommended test board, chip soldered or greased to  
thermal land  
Board-mounted, no air flow, high conductivity TI  
recommended test board with thermal land but no  
solder or grease thermal connection to thermal land  
Junction-to-case-thermal resistance  
°C/W  
0.38  
7.8  
Board-mounted, no air flow, JEDEC test board  
10  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢇ ꢀꢁ ꢂꢃ ꢃꢄ ꢅꢆ ꢈ  
ꢉꢀ ꢊꢉ ꢋꢌꢉꢀ ꢀ ꢋꢍꢌꢎꢏ ꢉ ꢈꢐ ꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
recommended operating conditions  
MIN NOM  
MAX  
UNIT  
Supply voltage, V  
V
2.3  
2.5  
80  
2.7  
V
DD, DD(A)  
Frequency = 1.25 Gbps,  
Frequency = 1.6 Gbps,  
Frequency = 1.25 Gbps  
Frequency = 1.6 Gbps  
Enable = 0,  
PRBS pattern  
Total supply current I  
I
mA  
DD, DD(A)  
Worst case pattern  
PRBS pattern  
111  
200  
Total power dissipation P  
mW  
D
Worst case pattern  
310  
50  
Total shutdown current I  
Startup lock time, PLL  
I
Vdda , Vdd = 2.7 V  
µA  
µs  
DD, DD(A)  
V
V
= 2.5 V, ENto PLL acquire  
500  
70  
DD, DD(A)  
TLK2201B  
TLK2201BI  
0
Operating free-air temperature, T  
°C  
A
−40  
85  
Worst case pattern is a pattern that creates a maximum transition density on the serial transceiver.  
TLK2201B reference clock (REFCLK) timing requirements over recommended operating  
conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
Minimum data rate  
MIN  
TYP−0.01%  
TYP−0.01%  
−100  
TYP  
MAX  
UNIT  
MHz  
MHz  
ppm  
Frequency  
Frequency  
Accuracy  
Duty cycle  
Jitter  
100 TYP−0.01%  
160 TYP−0.01%  
100  
Maximum data rate  
40%  
50%  
60%  
40  
Random plus deterministic  
ps  
TLK2201BI reference clock (REFCLK) timing requirements over recommended operating  
conditions (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
Minimum data rate  
MIN  
TYP−0.01%  
TYP−0.01%  
−100  
TYP  
MAX  
UNIT  
MHz  
MHz  
ppm  
Frequency  
Frequency  
Accuracy  
Duty cycle  
Jitter  
120 TYP−0.01%  
160 TYP−0.01%  
100  
Maximum data rate  
40%  
50%  
60%  
40  
Random plus deterministic  
ps  
TTL electrical characteristics over recommended operating conditions (unless otherwise noted)  
PARAMETER  
High-level output voltage  
Low-level output voltage  
High-level input voltage  
Low-level input voltage  
Input high current  
TEST CONDITIONS  
MIN  
−0.2  
GND  
1.7  
TYP  
2.3  
MAX  
UNIT  
V
V
V
V
V
I
I
= −400 µA  
V
DD  
OH  
OL  
IH  
OH  
= 1 mA  
0.25  
0.5  
3.6  
0.8  
40  
V
OL  
V
V
IL  
I
I
V
V
= 2.3 V,  
= 2.3 V,  
V
V
= 2.0 V  
= 0.4 V  
µA  
µA  
pf  
IH  
DD  
IN  
Input low current  
−40  
IL  
DD  
IN  
C
4
IN  
11  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁ ꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢈ  
ꢉ ꢀ ꢊ ꢉꢋ ꢌ ꢉꢀ ꢀ ꢋ ꢍ ꢌꢎ ꢏꢉ ꢈ ꢐꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
transmitter/receiver characteristics  
PARAMETER  
TEST CONDITIONS  
Rt = 50 Ω  
MIN  
600  
TYP  
850  
MAX  
1100  
1200  
1400  
1400  
UNIT  
Vod = |TxD−TxN|  
mV  
Rt = 75 Ω  
Rt = 50 Ω  
Rt = 75 Ω  
800  
1050  
1250  
1250  
1000  
1000  
V
(cm)  
Transmit common mode voltage range  
mV  
mV  
mV  
Receiver Input voltage requirement,  
Vid = |RxP − RxN|  
200  
1600  
2250  
Receiver common mode voltage range,  
(RxP + RxN)/2  
1000  
−350  
1250  
I
Receiver input leakage current  
Receiver input capacitance  
350  
2
µA  
lkg(R)  
C
pF  
I
Differential output jitter, Random  
+ deterministic, PRBS pattern,  
t
Serial data total jitter (peak-to-peak)  
0.24  
UI  
(TJ)  
R
= 125 MHz  
ω
Differential output jitter, PRBS  
t
Serial data deterministic jitter (peak-to-peak)  
Differential signal rise, fall time (20% to 80%)  
0.12  
250  
UI  
ps  
UI  
(DJ)  
pattern,  
R
= 125 MHz  
C = 5 pF,  
L
ω
R
L
= 50 ,  
t , t  
r f  
100  
See Figures 7 and 8  
Serial data jitter tolerance minimum required eye  
opening, (per IEEE-802.3 specification)  
Differential input jitter, Random  
0.25  
+ deterministic, R = 125 MHz  
ω
Receiver data acquisition lock time from powerup  
Data relock time from loss of synchronization  
500  
1024  
20  
µs  
Bit times  
TBI modes  
See Figure 1  
See Figure 6  
19  
29  
21  
27  
t
t
Tx latency  
DDR mode  
UI  
UI  
d(Tx latency)  
30  
TBI modes  
31  
Rx latency  
d(Rx latency)  
DDR mode  
34  
V  
80%  
50%  
TX+  
20%  
V  
t
f
t
r
V  
C
5 pF  
L
80%  
50 Ω  
50 Ω  
50%  
TX−  
V  
20%  
t
f
t
r
1V  
80%  
20%  
0 V  
VOD  
C
5 pF  
L
−1V  
Figure 7. Differential and Common-Mode  
Output Voltage Definitions  
Figure 8. Transmitter Test Setup  
1.4 V  
CLOCK  
t
t
f
r
2 V  
80%  
50%  
20%  
DATA  
0.8 V  
t
f
t
r
Figure 9. TTL Data I/O Valid Levels for AC Measurement  
12  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢇ ꢀꢁ ꢂꢃ ꢃꢄ ꢅꢆ ꢈ  
ꢉꢀ ꢊꢉ ꢋꢌꢉꢀ ꢀ ꢋꢍꢌꢎꢏ ꢉ ꢈꢐ ꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
LVTTL output switching characteristics over recommended operating conditions (unless  
otherwise noted)  
PARAMETER  
Clock rise time  
TEST CONDITIONS  
MIN  
0.3  
0.3  
0.3  
0.3  
TYP  
MAX  
1.5  
UNIT  
t
t
t
t
r(RBC)  
ns  
Clock fall time  
Data rise time  
Data fall time  
1.5  
f(RBC)  
80% to 20% output voltage, C = 5 pF (see Figure 9)  
1.5  
r
f
ns  
ns  
ns  
1.5  
Data setup time (RD0..RD9),  
Data valid prior to RBC0 rising  
t
t
TBI normal mode (see Figure 3)  
TBI normal mode (see Figure 3)  
2.5  
2
su(D1)  
h(D1)  
Data hold time (RD0..RD9),  
Data valid after RBC0 rising  
t
t
t
t
Data setup time (RD0..RD4)  
Data hold time (RD0..RD4)  
Data setup time (RD0..RD9)  
Data hold time (RD0..RD9)  
DDR mode, R = 125 MHz (see Figure 4)  
2
0.8  
2.5  
1.5  
ns  
ns  
ns  
ns  
su(D2)  
ω
DDR mode, R = 125 MHz (see Figure 4)  
h(D2)  
ω
TBI half-rate mode, R = 125 MHz (see Figure 2)  
su(D3)  
h(D3)  
ω
TBI half-rate mode, R = 125 MHz (see Figure 2)  
ω
transmitter timing requirements over recommended operating conditions (unless otherwise  
noted)  
PARAMETER  
Data setup time (TD0..TD9)  
Data hold time (TD0..TD9)  
Data setup time (TD0..TD9)  
Data hold time (TD0..TD9)  
TD[0,9] Data rise and fall time  
TEST CONDITIONS  
MIN  
1.6  
0.8  
0.7  
0.5  
TYP  
MAX  
UNIT  
t
t
t
t
su(D4)  
TBI modes  
ns  
h(D4)  
su(D5)  
h(D5)  
DDR modes  
See Figure 9  
ns  
ns  
t , t  
r f  
2
AVAILABLE OPTIONS  
PACKAGE  
T
A
PLASTIC QUAD FLAT PACK  
(RCP)  
0°C to 70°C  
TLK2201BRCP  
TLK2201BIRCP  
40°C to 85°C  
13  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁ ꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢈ  
ꢉ ꢀ ꢊ ꢉꢋ ꢌ ꢉꢀ ꢀ ꢋ ꢍ ꢌꢎ ꢏꢉ ꢈ ꢐꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
APPLICATION INFORMATION  
8B/10B transmission code  
The PCS maps GMII signals into ten-bit code groups and vice versa, using an 8b/10b block coding scheme.  
The PCS uses the transmission code to improve the transmission characteristics of information to be transferred  
across the link. The encoding defined by the transmission code ensures that sufficient transitions are present  
in the PHY bit stream to make clock recovery possible in the receiver. Such encoding also greatly increases  
the likelihood of detecting any single or multiple bit errors that may occur during transmission and reception of  
information. The 8b/10b transmission code specified for use has a high transition density, is run length limited,  
and is dc-balanced. The transition density of the 8b/10b symbols ranges from 3 to 8 transitions per symbol. The  
definition of the 8b/10b transmission code is specified in IEEE 802.3 Gigabit Ethernet and ANSI X3.230-1994  
(FC−PH), clause 11.  
8b/10b transmission code uses letter notation describing the bits of an unencoded information octet. The bit  
notation of A,B,C,D,E,F,G,H for an unencoded information octet is used in the description of the 8b/10b  
transmission code-groups, where A is the LSB. Each valid code group has been given a name using the  
following convention: /Dx.y/ for the 256 valid data code-groups and /Kx.y/ for the special control code-groups,  
where y is the decimal value of bits EDCBA and x is the decimal value of bits HGF (noted as K<HGF.EDCBA>).  
Thus, an octet value of FE representing a code-group value of K30.7 would be represented in bit notation as  
111 11110.  
14  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢇ ꢀꢁ ꢂꢃ ꢃꢄ ꢅꢆ ꢈ  
ꢉꢀ ꢊꢉ ꢋꢌꢉꢀ ꢀ ꢋꢍꢌꢎꢏ ꢉ ꢈꢐ ꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
APPLICATION INFORMATION  
VDD  
5 kΩ  
TXP  
Z
O
RXP  
7.5 kΩ  
Z
Z
O
GND  
VDD  
+
_
O
5 kΩ  
Z
O
TXN  
RXN  
7.5 kΩ  
GND  
Receiver  
Transmitter  
Media  
Figure 10. High-Speed I/O Directly-Coupled Mode  
VDD  
5 kΩ  
TXP  
Z
O
RXP  
7.5 kΩ  
Z
Z
O
GND  
VDD  
+
_
O
5 kΩ  
Z
O
TXN  
RXN  
7.5 kΩ  
GND  
Receiver  
Transmitter  
Media  
Figure 11. High-Speed I/O AC-Coupled Mode  
15  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁ ꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢈ  
ꢉ ꢀ ꢊ ꢉꢋ ꢌ ꢉꢀ ꢀ ꢋ ꢍ ꢌꢎ ꢏꢉ ꢈ ꢐꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
APPLICATION INFORMATION  
5 at 100 MHz  
2.5 V  
2.5 V  
18  
0.01 µF  
VDD VDDA  
VDDPLL  
64  
GND  
GNDPLL  
GNDA  
TLK2201B  
TLK2201BI  
17  
22  
TESTEN  
10  
Controlled Impedance  
Transmission Line  
62  
61  
TD0−TD9  
REFCLK  
PRBSEN  
TXP  
TXN  
16  
19  
LOOPEN  
SYNCEN  
24  
47  
Controlled Impedance  
Transmission Line  
Host  
Protocol  
Device  
SYNC/PASS  
RD0−RD9  
10  
2
RBC0−RBC1  
ENABLE  
28  
Controlled Impedance  
Transmission Line  
54  
RXP  
26  
32  
LOS  
50 Ω  
50 Ω  
R
t
t
RBCMODE  
MODESEL  
TCK  
15  
49  
55  
48  
56  
R
Controlled Impedance  
Transmission Line  
52  
RXN  
JTMS  
JTAG  
Controller  
JTDI  
JTRSTN  
JTDO  
27  
Figure 12. Typical Application Circuit (AC mode)  
designing with PowerPAD  
The TLK2201B and TLK2201BI are housed in a high performance, thermally enhanced, 64-pin VQFP (RCP64)  
PowerPADpackage. Use of the PowerPAD package does not require any special considerations except to note  
that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical  
conductor. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly  
techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD of connection  
etches or vias under the package. It is strongly recommended that the PowerPAD be soldered to the thermal  
land. The recommended convention, however, is to not run any etches or signal vias under the device, but to  
have only a grounded thermal land as explained below. Although the actual size of the exposed die pad may  
vary, the minimum size required for the keepout area for the 64-pin PFP PowerPAD package is 8 mm × 8 mm.  
16  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢇ ꢀꢁ ꢂꢃ ꢃꢄ ꢅꢆ ꢈ  
ꢉꢀ ꢊꢉ ꢋꢌꢉꢀ ꢀ ꢋꢍꢌꢎꢏ ꢉ ꢈꢐ ꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
APPLICATION INFORMATION  
designing with PowerPAD (continued)  
It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the  
PowerPAD package. The thermal land varies in size depending on the PowerPAD package being used, the PCB  
construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may not  
contain numerous thermal vias depending on PCB construction.  
Other requirements for thermal lands and thermal vias are detailed in the TI application note PowerPAD  
Thermally Enhanced Package Application Report, TI literature number SLMA002, available via the TI Web  
pages beginning at URL: http://www.ti.com.  
Figure 13. Example of a Thermal Land  
For the TLK2201B, this thermal land must be grounded to the low-impedance ground plane of the device. This  
improves not only thermal performance but also the electrical grounding of the device. It is also recommended  
that the device ground pin landing pads be connected directly to the grounded thermal land. The land size must  
be as large as possible without shorting device signal pins. The thermal land may be soldered to the exposed  
PowerPAD using standard reflow soldering techniques.  
While the thermal land may be electrically floated and configured to remove heat to an external heat sink, it is  
recommended that the thermal land be connected to the low-impedance ground plane for the device. More  
information may be obtained from the TI application note PHY Layout, TI literature number SLLA020.  
17  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢇ ꢀ ꢁ ꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢈ  
ꢉ ꢀ ꢊ ꢉꢋ ꢌ ꢉꢀ ꢀ ꢋ ꢍ ꢌꢎ ꢏꢉ ꢈ ꢐꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
MECHANICAL DATA  
RCP (S-PQFP-G64)  
PowerPADPLASTIC QUAD FLATPACK  
0,27  
M
0,08  
0,50  
0,17  
48  
33  
49  
32  
Thermal Pad  
(See Note D)  
64  
17  
0,13 NOM  
1
16  
7,50 TYP  
Gage Plane  
10,20  
SQ  
9,80  
0,25  
12,20  
0,15  
0,05  
0° − 7°  
SQ  
11,80  
0,85  
0,75  
0,75  
0,45  
Seating Plane  
0,08  
1,00 MAX  
4147711/A 10/98  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion.  
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.  
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.  
E. Falls within JEDEC MS-026  
PowerPAD is a trademark of Texas Instruments.  
18  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃ ꢃ ꢄꢅ ꢆ ꢇ ꢀꢁ ꢂꢃ ꢃꢄ ꢅꢆ ꢈ  
ꢉꢀ ꢊꢉ ꢋꢌꢉꢀ ꢀ ꢋꢍꢌꢎꢏ ꢉ ꢈꢐ ꢉ ꢋꢎ  
SLLS585 − NOVEMBER 2003  
THERMAL PAD MECHANICAL DATA  
PowerPADt PLASTIC QUAD FLATPACK  
RCP (S−PQFP−G64)  
PPTD037  
19  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
4-Feb-2005  
PACKAGING INFORMATION  
Orderable Device  
TLK2201BIRCP  
Status (1)  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
HVQFP  
RCP  
64  
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
TLK2201BIRCPG4  
HVQFP  
RCP  
64  
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
TLK2201BIRCPR  
TLK2201BRCP  
ACTIVE  
ACTIVE  
HVQFP  
HVQFP  
RCP  
RCP  
64  
64  
1000  
None  
CU NIPDAU Level-3-235C-168 HR  
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
TLK2201BRCPR  
ACTIVE  
HVQFP  
RCP  
64  
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional  
product content details.  
None: Not yet available Lead (Pb-Free).  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,  
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process  
in which TI products or services are used. Information published by TI regarding third-party products or services  
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.  
Use of such information may require a license from a third party under the patents or other intellectual property  
of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without  
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction  
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for  
such altered documentation.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that  
product or service voids all express and any implied warranties for the associated TI product or service and  
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.  
Following are URLs where you can obtain information on other Texas Instruments products and application  
solutions:  
Products  
Applications  
Audio  
Amplifiers  
amplifier.ti.com  
www.ti.com/audio  
Data Converters  
dataconverter.ti.com  
Automotive  
www.ti.com/automotive  
DSP  
dsp.ti.com  
Broadband  
Digital Control  
Military  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
Logic  
interface.ti.com  
logic.ti.com  
Power Mgmt  
Microcontrollers  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
Telephony  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address:  
Texas Instruments  
Post Office Box 655303 Dallas, Texas 75265  
Copyright 2005, Texas Instruments Incorporated  
配单直通车
TLK2201BIRCP产品参数
型号:TLK2201BIRCP
Brand Name:Texas Instruments
是否无铅:不含铅
是否Rohs认证:符合
生命周期:Active
IHS 制造商:TEXAS INSTRUMENTS INC
零件包装代码:QFP
包装说明:HVQFP-64
针数:64
Reach Compliance Code:compliant
ECCN代码:5A991.B.1
HTS代码:8542.39.00.01
Factory Lead Time:1 week
风险等级:1.09
Is Samacsys:N
数据速率:1600000 Mbps
JESD-30 代码:S-PQFP-G64
JESD-609代码:e4
长度:10 mm
湿度敏感等级:3
功能数量:1
端子数量:64
收发器数量:1
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:HVFQFP
封装等效代码:TQFP64,.47SQ
封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, VERY THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260
电源:2.5 V
认证状态:Not Qualified
座面最大高度:1 mm
子类别:Network Interfaces
最大压摆率:0.111 mA
标称供电电压:2.5 V
表面贴装:YES
技术:CMOS
电信集成电路类型:ETHERNET TRANSCEIVER
温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING
端子节距:0.5 mm
端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10 mm
Base Number Matches:1
  •  
  • 供货商
  • 型号 *
  • 数量*
  • 厂商
  • 封装
  • 批号
  • 交易说明
  • 询价
批量询价选中的记录已选中0条,每次最多15条。
 复制成功!