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  • 北京元坤伟业科技有限公司

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  • 深圳市正纳电子有限公司

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  • 深圳市芯脉实业有限公司

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  • 深圳德田科技有限公司

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  • 深圳市芯脉实业有限公司

     该会员已使用本站11年以上
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  • 数量2500 
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  • 封装VSSOP (DGK) 
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  • 深圳市力拓辉电子有限公司

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     该会员已使用本站6年以上
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  • 深圳市芯福林电子有限公司

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  • 深圳市正纳电子有限公司

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  • 千层芯半导体(深圳)有限公司

     该会员已使用本站9年以上
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  • TI一级代理专营品牌绝对进口原装假一赔十
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     该会员已使用本站12年以上
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     该会员已使用本站7年以上
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  • 数量8500 
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  • 深圳市毅创腾电子科技有限公司

     该会员已使用本站16年以上
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  • 深圳市拓亿芯电子有限公司

     该会员已使用本站12年以上
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产品型号TLV2372IDGKR的概述

TLV2372IDGKR 芯片的概述与应用 一、概述 TLV2372IDGKR 是由德州仪器(Texas Instruments)公司生产的一款高精度运算放大器。这款运算放大器具备低功耗、高输入阻抗和宽工作电压范围等特性,非常适合用于需要高线性度和高增益的各种模拟电路。TLV2372IDGKR 通常用于信号处理、数据采集、传感器接口、以及各种工业和消费类应用中。该芯片以其出色的性能和可靠性,成为许多电子工程师的首选。 二、详细参数 1. 电气特性 TLV2372IDGKR 的主要电气参数包括: - 增益带宽积(GBP): 1 MHz - 增益(A_V): 100000 (100 dB) - 输入失调电压(V_os): ±0.5 mV - 输入偏置电流(I_b): 0.2 nA - 输出电压范围: 0 V 到 V_DD – 1.5 V - 功耗: 35 µA/放大器 - 工作温度范围...

产品型号TLV2372IDGKR的Datasheet PDF文件预览

ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢄ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ ꢇ ꢀꢁꢂ ꢃꢄ ꢅꢊ  
ꢐ ꢙꢛꢗ ꢌꢀ ꢎꢐ ꢘꢌꢁ ꢌꢍ ꢙꢁ ꢎꢋ ꢎꢛ ꢗꢜ ꢝ ꢎꢀ ꢕ ꢜꢕꢚ ꢀꢞ ꢐ ꢝꢘ  
ꢆ ꢑµꢌꢒ ꢓꢔ ꢄ ꢑꢍ ꢕꢖ ꢗꢌꢎ ꢁ ꢑꢀꢐ ꢑꢗꢌꢎ ꢁ ꢎꢘ ꢙꢚꢀꢒ ꢐ ꢚ ꢀꢙ ꢚꢀ  
SLOS270D − MARCH 2001 − REVISED JANUARY 2005  
D
D
D
D
D
D
Rail-To-Rail Input/Output  
Wide Bandwidth . . . 3 MHz  
High Slew Rate . . . 2.4 V/µs  
Supply Voltage Range . . . 2.7 V to 16 V  
Supply Current . . . 550 µA/Channel  
Low Power Shutdown Mode  
Operational Amplifier  
+
I
. . . 25 µA/Channel  
DD(SHDN)  
D
D
D
Input Noise Voltage . . . 39 nV/Hz  
Input Bias Current . . . 1 pA  
Specified Temperature Range  
−40°C to 125°C . . . Industrial Grade  
D
Ultrasmall Packaging  
5 or 6 Pin SOT-23 (TLV2370/1)  
8 or 10 Pin MSOP (TLV2372/3)  
description  
The TLV237x single supply operational amplifiers provide rail-to-rail input and output capability. The TLV237x  
takes the minimum operating supply voltage down to 2.7 V over the extended industrial temperature range while  
adding the rail-to-rail output swing feature. The TLV237x also provides 3-MHz bandwidth from only 550 µA. The  
maximum recommended supply voltage is 16 V, which allows the devices to be operated from ( 8 V supplies  
down to 1.35 V) a variety of rechargeable cells.  
The CMOS inputs enable use in high-impedance sensor interfaces, with the lower voltage operation making  
an ideal alternative for the TLC227x in battery-powered applications. The rail-to-rail input stage further  
increases its versatility. The TLV237x is the seventh member of a rapidly growing number of RRIO products  
available from TI, and it is the first to allow operation up to 16-V rails with good ac performance.  
All members are available in PDIP and SOIC with the singles in the small SOT-23 package, duals in the MSOP,  
and quads in the TSSOP package.  
The 2.7-V operation makes the TLV237x compatible with Li-Ion powered systems and the operating supply  
voltage range of many micro-power microcontrollers available today including TI’s MSP430.  
SELECTION OF SIGNAL AMPLIFIER PRODUCTS  
RAIL-  
TO-  
RAIL  
V
(µV)  
Iq/Ch  
(µA)  
GBW  
(MHz)  
SR  
(V/µs)  
IO  
DEVICE  
TLV237x  
V
(V)  
I
IB  
(pA)  
SHUTDOWN  
SINGLES/DUALS/QUADS  
DD  
2.7−16  
4−16  
500  
300  
500  
1100  
150  
250  
300  
550  
1100  
550  
675  
550  
600  
725  
1
1
1
1
3
2.4  
3.6  
2.4  
3.6  
1.6  
1.5  
1.4  
Yes  
I/O  
O
S/D/Q  
D/Q  
TLC227x  
TLV27x  
2.2  
3
2.7−16  
3−16  
O
S/D/Q  
S/D/Q  
S/D/Q  
S/D/Q  
D/Q  
TLC27x  
TLV246x  
TLV247x  
TLV244x  
1.7  
6.4  
2.8  
1.8  
I/O  
I/O  
O
2.7−6  
2.7−6  
2.7−10  
1300  
Yes  
Yes  
2
1
Typical values measured at 5 V, 25°C  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢀꢪ  
Copyright 2001−2005, Texas Instruments Incorporated  
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ꢆ ꢌꢒ ꢓ ꢔ ꢄ ꢑꢍꢕꢖ ꢗꢌ ꢎ ꢁꢑꢀꢐ ꢑꢗꢌꢎ ꢁ ꢎꢘ ꢙꢚꢀ ꢒꢐ ꢚꢀ ꢙꢚ ꢀ  
µ
SLOS270D − MARCH 2001 − REVISED JANUARY 2005  
(1)  
FAMILY PACKAGE TABLE  
PACKAGE TYPES  
NUMBER OF  
DEVICE  
UNIVERSAL  
EVM BOARD  
SHUTDOWN  
CHANNELS  
PDIP  
SOIC  
8
SOT-23 TSSOP MSOP  
TLV2370  
TLV2371  
TLV2372  
TLV2373  
TLV2374  
TLV2375  
1
1
2
2
4
4
8
8
6
14  
16  
8
Yes  
8
5
Refer to the EVM  
Selection Guide  
(Lit# SLOU060)  
8
8
14  
14  
16  
14  
14  
16  
10  
Yes  
Yes  
(1)  
TLV2370 and TLV2371 AVAILABLE OPTIONS  
PACKAGED DEVICES  
V
IO  
MAX AT  
25°C  
SOT-23  
T
A
SMALL OUTLINE  
PLASTIC DIP  
(D)  
(P)  
(DBV)  
SYMBOL  
TLV2370ID  
TLV2371ID  
TLV2370IDBV  
TLV2371IDBV  
VBFI  
VBGI  
TLV2370IP  
TLV2371IP  
40°C to 125°C  
4.5 mV  
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2370IDR).  
This package is only available taped and reeled. For standard quantities (3,000 pieces per reel), add an R suffix (e.g., TLV2370IDBVR). For  
smaller quantities (250 pieces per mini-reel), add a T suffix to the part number (e.g., TLV2370IDBVT).  
(1)  
TLV2372 AND TLV2373 AVAILABLE OPTIONS  
PACKAGED DEVICES  
V
IO  
MAX AT  
25°C  
SMALL  
PLASTIC  
DIP  
PLASTIC  
DIP  
MSOP  
SYMBOL  
T
A
OUTLINE  
§
§
§
(DGK)  
(DGS)  
SYMBOL  
(D)  
(N)  
(P)  
40°C  
to  
125°C  
TLV2372ID  
TLV2373ID  
TLV2372IDGK  
APG  
API  
TLV2372IP  
4.5 mV  
TLV2373IDGS  
TLV2373IN  
§
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2372IDR).  
(1)  
TLV2374 and TLV2375 AVAILABLE OPTIONS  
PACKAGED DEVICES  
V
IO  
MAX AT  
25°C  
T
A
SMALL OUTLINE  
PLASTIC DIP  
(N)  
TSSOP  
(PW)  
(D)  
TLV2374ID  
TLV2375ID  
TLV2374IN  
TLV2375IN  
TLV2374IPW  
TLV2375IPW  
40°C to 125°C  
4.5 mV  
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number  
(e.g., TLV2374IDR).  
1. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website  
at www.ti.com.  
2
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SLOS270D − MARCH 2001 − REVISED JANUARY 2005  
(1)  
TLV237x PACKAGE PINOUTS  
TLV2370  
D OR P PACKAGE  
(TOP VIEW)  
TLV2370  
DBV PACKAGE  
(TOP VIEW)  
TLV2371  
DBV PACKAGE  
(TOP VIEW)  
1
2
3
V
5
V
DD  
OUT  
GND  
OUT  
GND  
1
2
6
5
NC  
IN−  
SHDN  
DD  
1
2
3
4
8
7
6
5
V
DD  
SHDN  
IN−  
IN+  
OUT  
NC  
GND  
4
IN−  
IN+  
IN+  
3
4
TLV2373  
DGS PACKAGE  
(TOP VIEW)  
TLV2371  
D OR P PACKAGE  
(TOP VIEW)  
TLV2372  
D, DGK, OR P PACKAGE  
(TOP VIEW)  
1
1OUT  
1IN−  
1IN+  
GND  
1SHDN  
V
DD  
2OUT  
2IN−  
2IN+  
10  
NC  
IN−  
IN+  
NC  
1OUT  
1IN−  
1IN+  
GND  
V
DD  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
2
3
4
5
9
8
7
6
V
2OUT  
2IN−  
2IN+  
DD  
OUT  
NC  
GND  
2SHDN  
TLV2375  
D, N, OR PW PACKAGE  
TLV2374  
D, N, OR PW PACKAGE  
TLV2373  
D OR N PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
(TOP VIEW)  
1OUT  
1IN−  
1IN+  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
4OUT  
4IN−  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OUT  
1IN−  
1IN+  
GND  
NC  
V
1OUT  
1IN−  
1IN+  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4OUT  
4IN−  
4IN+  
GND  
3IN+  
3IN−  
3OUT  
DD  
2OUT  
2IN−  
2IN+  
NC  
4IN+  
V
+
GND  
DD  
V
DD  
2IN+  
2IN−  
3IN+  
2IN+  
2IN−  
3IN−  
1SHDN  
NC  
2SHDN  
NC  
2OUT  
3OUT  
3/4SHDN  
8
8
2OUT  
1/2SHDN  
NC − No internal connection  
TYPICAL PIN 1 INDICATORS  
Pin 1  
Pin 1  
Pin 1  
Pin 1  
Molded “U” Shape  
Printed or  
Molded Dot  
Stripe  
Bevel Edges  
NOTE:  
(1) If there is not a Pin 1 indicator, turn device to enable reading the symbol from the left to right. Pin 1 is at the lower left corner of the  
device.  
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µ
SLOS270D − MARCH 2001 − REVISED JANUARY 2005  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage, V  
Differential input voltage, V  
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V  
DD  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
V
ID  
DD  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2 V to V  
Input current range, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA  
Output current range, I  
+ 0.2 V  
I
DD  
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA  
O
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table  
Operating free-air temperature range, T : I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C  
A
Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C  
J
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
stg  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE:  
All voltage values, except differential voltages, are with respect to GND.  
DISSIPATION RATING TABLE  
θ
θ
T 25°C  
A
POWER RATING  
JC  
JA  
PACKAGE  
(°C/W)  
(°C/W)  
D (8)  
38.3  
176  
710 mW  
D (14)  
D (16)  
26.9  
25.7  
55  
122.3  
114.7  
324.1  
294.3  
259.96  
1022 mW  
1090 mW  
385 mW  
425 mW  
481 mW  
DBV (5)  
DBV (6)  
DGK (8)  
55  
54.23  
DGS (10)  
N (14, 16)  
P (8)  
54.1  
32  
257.71  
78  
485 mW  
1600 mW  
1200 mW  
720 mW  
774 mW  
41  
104  
PW (14)  
PW (16)  
29.3  
28.7  
173.6  
161.4  
recommended operating conditions  
MIN  
2.7  
1.35  
0
MAX  
16  
UNIT  
Single supply  
Supply voltage, V  
DD  
V
Split supply  
8
Common-mode input voltage range, V  
ICR  
V
DD  
V
°C  
V
Operating free-air temperature, T  
I-suffix  
−40  
125  
2
A
Turnon voltage level, V  
Turnoff voltage level, V  
, relative to GND pin voltage  
(ON)  
, relative to GND pin voltage  
0.8  
V
(OFF)  
4
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µ
SLOS270D − MARCH 2001 − REVISED JANUARY 2005  
electrical characteristics at specified free-air temperature, V  
otherwise noted)  
= 2.7 V, 5 V, and 15 V (unless  
DD  
dc performance  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
4.5  
6
T
UNIT  
A
25°C  
2
V
Input offset voltage  
Offset voltage drift  
mV  
V
V
V
V
= V /2,  
DD  
V
R
= V /2,  
DD  
IO  
O
IC  
S
Full range  
= 50 Ω  
α
VIO  
25°C  
25°C  
2
µV/°C  
50  
49  
56  
54  
55  
54  
67  
64  
64  
63  
67  
66  
98  
76  
100  
86  
81  
79  
68  
V
R
= 0 to V  
= 50 Ω  
,
IC  
DD  
Full range  
25°C  
S
= 2.7 V  
DD  
DD  
DD  
70  
72  
V
R
= 0 to V −1.35V,  
DD  
= 50 Ω  
IC  
Full range  
25°C  
S
V
R
= 0 to V  
= 50 ,  
,
IC  
DD  
Full range  
25°C  
S
CMRR Common-mode rejection ratio  
= 5 V  
dB  
80  
V
R
= 0 to V −1.35V,  
DD  
= 50 ,  
IC  
Full range  
25°C  
S
82  
V
R
= 0 to V  
= 50 ,  
,
IC  
DD  
Full range  
25°C  
S
= 15 V  
84  
V
R
= 0 to V −1.35V,  
DD  
= 50 ,  
IC  
Full range  
25°C  
S
106  
110  
83  
V
DD  
V
DD  
V
DD  
= 2.7 V  
= 5 V  
Full range  
25°C  
Large-signal differential voltage  
amplification  
V
= V /2,  
DD  
R = 10 kΩ  
O(PP)  
A
VD  
dB  
Full range  
25°C  
L
= 15 V  
Full range  
input characteristics  
PARAMETER  
TEST CONDITIONS  
T
MIN  
TYP  
MAX  
60  
UNIT  
A
25°C  
70°C  
125°C  
25°C  
70°C  
125°C  
25°C  
25°C  
1
100  
1000  
60  
I
I
Input offset current  
Input bias current  
pA  
IO  
V
= 15 V,  
V = V /2,  
IC DD  
DD  
= V /2  
V
O
1
DD  
100  
1000  
pA  
IB  
r
Differential input resistance  
1000  
8
GΩ  
i(d)  
C
Common-mode input capacitance  
f = 21 kHz  
pF  
IC  
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µ
SLOS270D − MARCH 2001 − REVISED JANUARY 2005  
electrical characteristics at specified free-air temperature, V  
otherwise noted) (continued)  
= 2.7 V, 5 V, and 15 V (unless  
DD  
output characteristics  
PARAMETER  
TEST CONDITIONS  
MIN  
2.55  
2.48  
4.9  
TYP  
MAX  
T
UNIT  
A
25°C  
Full range  
25°C  
2.58  
V
V
V
V
V
V
V
V
V
V
V
V
= 2.7 V  
= 5 V  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
4.93  
V
V
V
V
= V /2,  
DD  
I
I
I
I
= −1 mA  
= −5 mA  
= 1 mA  
IC  
IC  
IC  
IC  
OH  
OH  
OL  
OL  
Full range  
25°C  
4.85  
14.92 14.96  
14.9  
= 15 V  
= 2.7 V  
= 5 V  
Full range  
25°C  
V
OH  
High-level output voltage  
V
1.9  
1.6  
2
4.68  
14.8  
0.1  
Full range  
25°C  
4.6  
= V /2,  
DD  
Full range  
25°C  
4.5  
14.7  
14.6  
= 15 V  
= 2.7 V  
= 5 V  
Full range  
25°C  
0.15  
0.22  
0.1  
Full range  
25°C  
0.05  
0.05  
0.52  
0.28  
0.19  
= V /2,  
DD  
Full range  
25°C  
0.15  
0.08  
0.1  
= 15 V  
= 2.7 V  
= 5 V  
Full range  
25°C  
V
OL  
Low-level output voltage  
V
0.7  
Full range  
25°C  
1.1  
0.4  
= V /2,  
DD  
= 5 mA  
Full range  
25°C  
0.5  
0.3  
= 15 V  
Full range  
25°C  
0.35  
Positive rail  
Negative rail  
Positive rail  
Negative rail  
Positive rail  
Negative rail  
4
5
V
DD  
V
DD  
V
DD  
= 2.7 V, V = 0.5 V from rail  
O
25°C  
25°C  
7
I
O
Output current  
= 5 V,  
V
= 0.5 V from rail  
= 0.5 V from rail  
mA  
O
25°C  
8
25°C  
16  
15  
= 15 V,  
V
O
25°C  
power supply  
PARAMETER  
TEST CONDITIONS  
T
MIN  
TYP  
470  
550  
750  
MAX  
560  
UNIT  
A
V
V
= 2.7 V  
= 5 V  
25°C  
25°C  
DD  
660  
DD  
I
Supply current (per channel)  
V
V
= V /2,  
DD  
µA  
DD  
O
25°C  
900  
V
= 15 V  
DD  
IC  
Full range  
25°C  
1200  
70  
65  
80  
Supply voltage rejection ratio  
(V /V  
= 2.7 V to 15 V,  
V
= V /2,  
DD  
DD  
PSRR  
dB  
)
No load  
Full range  
DD IO  
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SLOS270D − MARCH 2001 − REVISED JANUARY 2005  
electrical characteristics at specified free-air temperature, V  
otherwise noted) (continued)  
= 2.7 V, 5 V, and 15 V (unless  
DD  
dynamic performance  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
2.4  
3
MAX  
UNIT  
T
A
25°C  
25°C  
V
V
= 2.7 V  
DD  
R
C
= 2 kΩ,  
= 10 pF  
L
L
UGBW Unity gain bandwidth  
MHz  
= 5 V to 15 V  
DD  
25°C  
1.4  
1
2
V
V
V
= 2.7 V  
V/µs  
V/µs  
V/µs  
DD  
DD  
DD  
Full range  
25°C  
V
C
R
= V /2,  
DD  
O(PP)  
L
L
1.6  
1.2  
1.9  
1.4  
2.4  
2.1  
= 50 pF,  
SR  
Slew rate at unity gain  
= 5 V  
Full range  
25°C  
= 10 kΩ  
= 15 V  
Full range  
25°C  
φ
m
Phase margin  
Gain margin  
65°  
R
R
= 2 k,  
= 2 k,  
C
C
= 100 pF  
= 10 pF  
L
L
L
25°C  
18  
dB  
L
V
V
C
= 2.7 V,  
DD  
= 1 V,  
A
R
= −1,  
= 2 kΩ  
0.1%  
0.1%  
2.9  
2
(STEP)PP  
= 10 pF,  
V
L
L
t
s
Settling time  
25°C  
µs  
V
V
C
= 5 V, 15 V,  
DD  
(STEP)PP  
= 47 pF,  
= 1 V,  
A
= −1,  
= 2 kΩ  
V
R
L
L
noise/distortion performance  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
0.02%  
0.05%  
0.18%  
0.02%  
0.09%  
0.5%  
39  
MAX  
UNIT  
T
A
A
V
= 1  
V
V
R
= 2.7 V,  
DD  
O(PP)  
L
A
= 10  
= 100  
= 1  
= V /2 V,  
DD  
25°C  
25°C  
V
= 2 k, f = 10 kHz  
A
V
THD + N Total harmonic distortion plus noise  
A
V
V
V
R
= 5 V, 15 V,  
= V /2 V,  
DD  
O(PP)  
A
V
= 10  
= 100  
DD  
= 2 k, f = 10 kHz  
L
A
V
f = 1 kHz  
f = 10 kHz  
f = 1 kHz  
nV/Hz  
fA/Hz  
V
I
Equivalent input noise voltage  
Equivalent input noise current  
25°C  
25°C  
n
35  
0.6  
n
shutdown characteristics  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
30  
UNIT  
T
A
25°C  
Full range  
25°C  
25  
V
= 2.7 V, 5 V,  
DD  
SHDN = 0 V  
µA  
35  
Supply current in shutdown mode (TLV2370,  
TLV2373, TLV2375) (per channel)  
I
DD(SHDN)  
40  
45  
V
= 15 V,  
DD  
SHDN = 0 V  
µA  
Full range  
25°C  
50  
t
Amplifier turnon time (see Note 2)  
Amplifier turnoff time (see Note 2)  
0.8  
1
µs  
µs  
(on)  
R
= 2 kΩ  
L
t
25°C  
(off)  
NOTE:  
Disable time and enable time are defined as the interval between application of the logic signal to the SHDN terminal and the point at  
which the supply current has reached one half of its final value.  
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µ  
SLOS270D − MARCH 2001 − REVISED JANUARY 2005  
TYPICAL CHARACTERISTICS  
Table of Graphs  
FIGURE  
1, 2, 3  
4
V
Input offset voltage  
vs Common-mode input voltage  
IO  
CMRR  
Common-mode rejection ratio  
Input bias and offset current  
Low-level output voltage  
High-level output voltage  
Peak-to-peak output voltage  
Supply current  
vs Frequency  
vs Free-air temperature  
vs Low-level output current  
vs High-level output current  
vs Frequency  
5
V
V
V
6, 8, 10  
7, 9, 11  
12  
OL  
OH  
O(PP)  
I
vs Supply voltage  
vs Frequency  
13  
DD  
PSRR  
Power supply rejection ratio  
Differential voltage gain & phase  
Gain-bandwidth product  
14  
A
VD  
vs Frequency  
15  
vs Free-air temperature  
vs Supply voltage  
vs Free-air temperature  
vs Capacitive load  
vs Frequency  
16  
17  
SR  
Slew rate  
18  
φ
m
Phase margin  
19  
V
n
Equivalent input noise voltage  
Voltage-follower large-signal pulse response  
Voltage-follower small-signal pulse response  
Inverting large-signal response  
Inverting small-signal response  
Crosstalk  
20  
21, 22  
23  
24, 25  
26  
vs Frequency  
27  
Shutdown forward & reverse isolation  
Shutdown supply current  
vs Frequency  
28  
I
I
I
vs Supply voltage  
vs Shutdown pin voltage  
vs Time  
29  
DD(SHDN)  
DD(SHDN)  
DD(SHDN)  
Shutdown pin leakage current  
Shutdown supply current/output voltage  
30  
31, 32  
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SLOS270D − MARCH 2001 − REVISED JANUARY 2005  
TYPICAL CHARACTERISTICS  
INPUT OFFSET VOLTAGE  
vs  
COMMON-MODE INPUT VOLTAGE  
INPUT OFFSET VOLTAGE  
INPUT OFFSET VOLTAGE  
vs  
COMMON-MODE INPUT VOLTAGE  
vs  
COMMON-MODE INPUT VOLTAGE  
1000  
1000  
1000  
V
T
A
=15 V  
= 25 °C  
DD  
V
T
= 5 V  
= 25 °C  
DD  
A
V
T
A
= 2.7 V  
= 25°C  
DD  
800  
600  
400  
200  
800  
800  
600  
400  
200  
600  
400  
200  
0
0
0
−200  
−200  
−200  
0
0.4  
0.8  
1.2  
1.6  
2
2.4 2.7  
0
2
4
6
8
10  
12  
14 15  
0
1
2
3
4
5
V
− Common-Mode Input Voltage − V  
V
− Common-Mode Input Voltage − V  
ICR  
V
− Common-Mode Input Voltage −V  
ICR  
ICR  
Figure 1  
Figure 2  
Figure 3  
COMMON-MODE REJECTION RATIO  
INPUT BIAS/OFFSET CURRENT  
vs  
LOW-LEVEL OUTPUT VOLTAGE  
vs  
vs  
FREE-AIR TEMPERATURE  
LOW-LEVEL OUTPUT CURRENT  
FREQUENCY  
2.80  
2.40  
2
300  
250  
200  
150  
100  
50  
120  
V
= 2.7 V  
DD  
= 125 °C  
V
V
= 2.7 V, 5 V and 15 V  
DD  
= V /2  
IC  
DD  
100  
80  
T
A
V
= 5 V, 15 V  
DD  
1.60  
1.20  
0.80  
0.40  
0
60  
V
= 2.7 V  
DD  
T
A
= 70 °C  
40  
20  
0
T
A
= 25 °C  
T
A
= 0 °C  
0
T
A
= −40 °C  
−50  
−4025 −10 5 20 35 50 65 80 95 110 125  
0
2
4
6
8
10 12 14 16 18 20 22 24  
10  
100  
1 k  
10 k  
100 k  
1 M  
I
− Low-Level Output Current − mA  
T
A
− Free-Air Temperature − °C  
OL  
f − Frequency − Hz  
Figure 5  
Figure 4  
Figure 6  
HIGH-LEVEL OUTPUT VOLTAGE  
vs  
HIGH-LEVEL OUTPUT CURRENT  
LOW-LEVEL OUTPUT VOLTAGE  
vs  
LOW-LEVEL OUTPUT CURRENT  
HIGH-LEVEL OUTPUT VOLTAGE  
vs  
HIGH-LEVEL OUTPUT CURRENT  
5
5
4.50  
4
2.80  
2.40  
2
V
= 5 V  
V
= 5 V  
DD  
CC  
V
= 2.7 V  
DD  
4.50  
4
T
A
= −40°C  
T
A
= 125 °C  
T
A
= 0°C  
T
A
=−40°C  
T
A
= 70 °C  
3.50  
3
3.50  
3
T
= 125°C  
= 70°C  
A
1.60  
1.20  
0.80  
0.40  
0
2.50  
2
2.50  
2
T
A
= 25°C  
T
A
T
A
= 25 °C  
T
= 25°C  
= 0°C  
A
1.50  
1
T
A
= 70°C  
1.50  
1
T
= 0 °C  
A
T
A
T
A
= −40 °C  
T
A
= 125°C  
0.50  
0
0.50  
0
0
5
10 15 20 25 30 35 40 45  
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70  
0
1
2
3
4
5
6
7
8
9
10 11 12  
I
− Low-Level Output Current − mA  
I
− High-Level Output Current − mA  
I
− High-Level Output Current − mA  
OL  
OH  
OH  
Figure 8  
Figure 7  
Figure 9  
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µ  
SLOS270D − MARCH 2001 − REVISED JANUARY 2005  
TYPICAL CHARACTERISTICS  
PEAK-TO-PEAK OUTPUT VOLTAGE  
HIGH-LEVEL OUTPUT VOLTAGE  
vs  
LOW-LEVEL OUTPUT VOLTAGE  
vs  
vs  
FREQUENCY  
HIGH-LEVEL OUTPUT CURRENT  
LOW-LEVEL OUTPUT CURRENT  
15  
16  
15  
V
= 15 V  
14  
12  
10  
8
15  
14  
13  
12  
11  
10  
9
8
7
6
5
DD  
V
= 15 V  
14  
12  
10  
8
DD  
V
= 15 V  
DD  
T
A
=125°C  
T
= −40°C  
A
T
=70°C  
=25°C  
A
A
R
C
= −10  
V
L
L
= 2 kΩ  
= 10 pF  
= 25°C  
T
A
T
A
= 0°C  
T
A
T
A
=0°C  
THD = 5%  
T
A
= 25°C  
6
6
T
A
=−40°C  
V
= 5 V  
DD  
T
A
= 70°C  
4
4
4
3
2
V
= 2.7 V  
DD  
T
A
= 125°C  
2
2
1
0
0
0
10  
100  
1 k  
10 k 100 k 1 M  
10 M  
20 40 60 80 100 120 140 160  
0
20 40 60 80 100 120 140 160  
0
I
− Low-Level Output Current − mA  
f − Frequency − Hz  
I
− High-Level Output Current − mA  
OL  
OH  
Figure 11  
Figure 10  
Figure 12  
POWER SUPPLY REJECTION RATIO  
SUPPLY CURRENT  
vs  
vs  
FREQUENCY  
SUPPLY VOLTAGE  
1
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
120  
100  
A
V
= 1  
T
A
= 25°C  
V
IC  
= V / 2  
DD  
T
A
= 125°C  
T
= 70°C  
V
= 5 V, 15 V  
A
DD  
80  
60  
V
= 2.7 V  
DD  
T
A
= 25°C  
40  
T
A
= 0°C  
T
A
= −40°C  
20  
0
0
0
10  
100  
1 k  
10 k  
100 k  
1 M  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
f − Frequency − Hz  
V
− Supply Voltage − V  
CC  
Figure 14  
Figure 13  
DIFFERENTIAL VOLTAGE GAIN AND PHASE  
GAIN BANDWIDTH PRODUCT  
vs  
vs  
FREQUENCY  
FREE-AIR TEMPERATURE  
180  
135  
90  
120  
100  
80  
4
3.5  
V
= 15 V  
Phase  
DD  
3
45  
60  
2.5  
V
= 5 V  
DD  
0
40  
2
1.5  
1
Gain  
V
= 2.7 V  
DD  
−45  
−90  
−135  
−180  
20  
V
=5 Vdc  
0
DD  
L
L
R =2 kΩ  
C =10 pF  
−20  
0.5  
0
T
=25°C  
A
−40  
10  
−40 −2510  
5
20 35 50 65 80 95 110 125  
100  
1 k  
10 k 100 k 1 M  
10 M  
T
A
− Free-Air Temperature − °C  
f − Frequency − Hz  
Figure 16  
Figure 15  
10  
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SLOS270D − MARCH 2001 − REVISED JANUARY 2005  
TYPICAL CHARACTERISTICS  
SLEW RATE  
vs  
FREE-AIR TEMPERATURE  
SLEW RATE  
vs  
SUPPLY VOLTAGE  
PHASE MARGIN  
vs  
CAPACITIVE LOAD  
3.5  
3
2.5  
2
100  
V
= 5 V  
SR−  
DD  
R = 2 kΩ  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
3
L
T
= 25°C  
= Open Loop  
A
SR−  
A
V
2.5  
Rnull = 100  
2
SR+  
1.5  
1
SR+  
1.5  
Rnull = 0  
V
A
R
= 5 V  
= 1  
= 10 kΩ  
= 50 pF  
A
= 1  
DD  
V
L
L
V
L
L
1
R
C
T
= 10 kΩ  
= 50 pF  
= 25°C  
Rnull = 50  
0.5  
0
0.5  
0
C
A
V = 3 V  
I
−40 −25 −10  
5
20 35 50 65 80 95 110 125  
2.5  
4.5  
6.5  
8.5  
10.5 12.5 14.5  
10  
100  
1000  
T
A
− Free-Air Temperature − °C  
V
− Supply Voltage −V  
CC  
C
− Capacitive Load − pF  
L
Figure 18  
Figure 17  
Figure 19  
EQUIVALENT INPUT NOISE VOLTAGE  
vs  
VOLTAGE-FOLLOWER LARGE-SIGNAL  
FREQUENCY  
PULSE RESPONSE  
100  
4
V
= 2.7, 5, 15 V  
DD  
= 25°C  
90  
80  
3
2
T
A
V
A
= 5 V  
= 1  
DD  
V
1
0
70  
60  
V
I
R
C
= 2 kΩ  
= 10 pF  
L
L
V = 3 V  
I
PP  
50  
T
= 25°C  
A
4
3
2
1
0
40  
30  
20  
V
O
10  
0
10  
100  
1 k  
10 k  
100 k  
0
2
4
6
8
10 12 14 16 18  
f − Frequency − Hz  
t − Time − µs  
Figure 21  
Figure 20  
VOLTAGE-FOLLOWER LARGE-SIGNAL  
VOLTAGE-FOLLOWER SMALL-SIGNAL  
PULSE RESPONSE  
PULSE RESPONSE  
12  
0.12  
9
0.08  
0.04  
0
V
= 15 V  
DD  
= 1  
6
3
0
V
A
R
= 5 V  
= 1  
= 2 kΩ  
= 10 pF  
DD  
V
L
L
A
V
R
C
= 2 kΩ  
= 10 pF  
L
L
I
V
V
I
I
C
V = 9 V  
T
A
PP  
= 25°C  
V = 100 mV  
T
A
I
PP  
12  
9
= 25°C  
0.12  
0.08  
0.04  
0
6
3
V
O
V
O
0
0
2
4
6
8
10 12 14 16 18  
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8  
t − Time − µs  
t − Time − µs  
Figure 23  
Figure 22  
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ꢆ ꢌꢒ ꢓ ꢔ ꢄ ꢑꢍꢕꢖ ꢗꢌ ꢎ ꢁꢑꢀꢐ ꢑꢗꢌꢎ ꢁ ꢎꢘ ꢙꢚꢀ ꢒꢐ ꢚꢀ ꢙꢚ ꢀ  
µ  
SLOS270D − MARCH 2001 − REVISED JANUARY 2005  
TYPICAL CHARACTERISTICS  
INVERTING LARGE-SIGNAL RESPONSE  
12  
INVERTING LARGE-SIGNAL RESPONSE  
4
V
I
3
2
1
9
V
A
= 15 V  
V
A
R
= 5 V  
= 1  
= 2 kΩ  
= 10 pF  
DD  
= −1  
DD  
V
L
L
I
6
V
R
C
= 2 kΩ  
= 10 pF  
L
L
3
0
V
C
0
I
V = 9 V  
V = 3 V  
I
pp  
PP  
T
A
= 25°C  
T
A
= 25°C  
9
6
3
V
O
2
1
0
3
0
V
O
0
2
4
6
8
10 12 14 16  
0
2
4
6
8
10 12 14 16  
t − Time − µs  
t − Time − µs  
Figure 25  
Figure 24  
CROSSTALK  
vs  
FREQUENCY  
INVERTING SMALL-SIGNAL RESPONSE  
0
V
= 2.7, 5, & 15 V  
DD  
V = V /2  
−20  
−40  
0.10  
I
DD  
A
V
= 1  
R
T
A
= 2 kΩ  
= 25°C  
V
A
R
= 5 V  
= −1  
= 2 kΩ  
= 10 pF  
L
DD  
V
L
L
0.05  
0
V
I
−60  
C
V = 100 mV  
I
pp  
0.1  
0.05  
0
−80  
T
A
= 25°C  
Crosstalk in Shutdown  
V
O
−100  
−120  
−140  
Crosstalk  
10 k  
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5  
10  
100  
1 k  
100 k  
t − Time − µs  
f − Frequency −Hz  
Figure 27  
Figure 26  
SHUTDOWN FORWARD AND  
REVERSE ISOLATION  
vs  
SHUTDOWN PIN LEAKAGE CURRENT  
vs  
SHUTDOWN SUPPLY CURRENT  
vs  
SHUTDOWN PIN VOLTAGE  
SUPPLY VOLTAGE  
FREQUENCY  
250  
50  
45  
40  
35  
30  
25  
20  
15  
10  
5
160  
140  
120  
100  
80  
SHDN = 0 V  
V
= 2.7 V, 5 V & 15 V  
T
A
= 125°C  
DD  
V = V  
V = V /2  
I
DD  
T
A
= 125°C  
/2  
DD  
= 2 kΩ  
I
A
= 1  
V
200  
150  
100  
50  
R
L
C = 10 pF  
L
V
A
= 1  
T
A
= 25°C  
T
A
= 70°C  
T
A
= 25°C  
60  
T
A
= 0°C  
40  
T
A
= −40°C  
20  
0
0
0
0
1
2
3
4
5 6 7 8 9 10 11 12 13 14 15  
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15  
10  
100  
1 k  
10 k 100 k 1 M  
1 M  
Shutdown Pin Voltage − V  
V
− Supply Voltage − V  
DD  
f − Frequency − Hz  
Figure 29  
Figure 28  
Figure 30  
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ꢋꢌ  
ꢁꢏ  
ꢐ ꢙꢛꢗ ꢌꢀ ꢎꢐ ꢘꢌꢁ ꢌꢍ ꢙꢁ ꢎꢋ ꢎꢛ ꢗꢜ ꢝ ꢎꢀ ꢕ ꢜꢕꢚ ꢀꢞ ꢐ ꢝꢘ  
ꢆ ꢑµꢌꢒ ꢓꢔ ꢄ ꢑꢍ ꢕꢖ ꢗꢌꢎ ꢁ ꢑꢀꢐ ꢑꢗꢌꢎ ꢁ ꢎꢘ ꢙꢚꢀꢒ ꢐ ꢚ ꢀꢙ ꢚꢀ  
SLOS270D − MARCH 2001 − REVISED JANUARY 2005  
TYPICAL CHARACTERISTICS  
SHUTDOWN SUPPLY CURRENT/OUTPUT VOLTAGE  
SHUTDOWN SUPPLY CURRENT/OUTPUT VOLTAGE  
vs  
vs  
TIME  
TIME  
6
10  
V
A
R
= 15 V  
DD  
= 1  
5
8
6
V
V
= 5 V  
= 1  
= 2 kΩ  
= 10 pF  
DD  
4
3
= 2 kΩ  
= 10 pF  
L
L
A
V
C
R
C
L
L
I
V = V /2  
I
A
DD  
= 25° C  
2
1
0
SHDN  
T
4
2
SHDN  
V = V /2  
T
A
DD  
= 25° C  
0
7.5  
6
2.5  
2
V
O
V
O
4.5  
1.5  
1
3
1.5  
0
0.5  
0
−0.5  
−1.5  
−1.0  
1
0.75  
I
1
DD(SHDN = 0)  
0.75  
0.50  
0.25  
0
0.50  
0.25  
0
I
DD(SHDN = 0)  
−0.25  
−0.25  
−2  
−1  
0
1
2
3
4
5
6
7
8
9
10  
−40 −20  
0
20  
40  
60  
80  
100 120 140 160  
t − Time − µs  
t − Time − µs  
Figure 32  
Figure 31  
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µ  
SLOS270D − MARCH 2001 − REVISED JANUARY 2005  
APPLICATION INFORMATION  
rail-to-rail input operation  
The TLV237x input stage consists of two differential transistor pairs, NMOS and PMOS, that operate together  
to achieve rail-to-rail input operation. The transition point between these two pairs can be seen in Figure 1,  
Figure 2, and Figure 3 for a 2.7-V, 5-V, and 15-V supply. As the common-mode input voltage approaches the  
positive supply rail, the input pair switches from the PMOS differential pair to the NMOS differential pair. This  
transition occurs approximately 1.35 V from the positive rail and results in a change in offset voltage due to  
different device characteristics between the NMOS and PMOS pairs. If the input signal to the device is large  
enough to swing between both rails, this transition results in a reduction in common-mode rejection ratio  
(CMRR). If the input signal does not swing between both rails, it is best to bias the signal in the region where  
only one input pair is active. This is the region in Figure 1 through Figure 3 where the offset voltage varies slightly  
across the input range and optimal CMRR can be achieved. This has the greatest impact when operating from  
a 2.7-V supply voltage.  
driving a capacitive load  
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device’s  
phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than  
10 pF, it is recommended that a resistor be placed in series (R  
) with the output of the amplifier, as shown  
NULL  
in Figure 33. A minimum value of 20 should work well for most applications.  
R
F
R
G
R
NULL  
+
Input  
Output  
LOAD  
C
V
DD  
/2  
Figure 33. Driving a Capacitive Load  
offset voltage  
The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times  
OO  
IO  
IB  
the corresponding gains. The following schematic and formula can be used to calculate the output offset  
voltage:  
R
F
I
IB−  
R
G
+
+
V
I
V
O
R
S
I
IB+  
R
R
F
F
V
+ V  
1 ) ǒ Ǔ " I  
R
1 ) ǒ Ǔ " I  
R
ǒ Ǔ ǒ Ǔ  
OO  
IO  
IB)  
S
IB–  
F
R
R
G
G
Figure 34. Output Offset Voltage Model  
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ꢋꢌ  
ꢍꢎ  
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ꢆ ꢑµꢌꢒ ꢓꢔ ꢄ ꢑꢍ ꢕꢖ ꢗꢌꢎ ꢁ ꢑꢀꢐ ꢑꢗꢌꢎ ꢁ ꢎꢘ ꢙꢚꢀꢒ ꢐ ꢚ ꢀꢙ ꢚꢀ  
SLOS270D − MARCH 2001 − REVISED JANUARY 2005  
APPLICATION INFORMATION  
general configurations  
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often  
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier  
(see Figure 35).  
R
R
F
G
V
DD  
/2  
V
1
O
+
V
I
R1  
C1  
f
+
–3dB  
2pR1C1  
V
R
O
F
1
ǒ
Ǔ
+
ǒ
1 )  
Ǔ
V
R
1 ) 2pfR1C1  
I
G
Figure 35. Single-Pole Low-Pass Filter  
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this  
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.  
Failure to do this can result in phase shift of the amplifier.  
C1  
R1 = R2 = R  
C1 = C2 = C  
Q = Peaking Factor  
(Butterworth Q = 0.707)  
+
_
V
I
1
R1  
R2  
f
+
–3dB  
2pRC  
C2  
R
F
1
R
=
G
R
F
2 −  
)
R
(
Q
G
V
DD  
/2  
Figure 36. 2-Pole Low-Pass Sallen-Key Filter  
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µ  
SLOS270D − MARCH 2001 − REVISED JANUARY 2005  
APPLICATION INFORMATION  
circuit layout considerations  
To achieve the levels of high performance of the TLV237x, follow proper printed-circuit board design techniques.  
A general set of guidelines is given in the following.  
D
Ground planes—It is highly recommended that a ground plane be used on the board to provide all  
components with a low inductive ground connection. However, in the areas of the amplifier inputs and  
output, the ground plane can be removed to minimize the stray capacitance.  
D
Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic  
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers  
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal  
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply  
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less  
effective. The designer should strive for distances of less than 0.1 inches between the device power  
terminals and the ceramic capacitors.  
D
D
Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins  
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board  
is the best implementation.  
Short trace runs/compact part placements—Optimum high performance is achieved when stray series  
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,  
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of  
the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance at the  
input of the amplifier.  
D
Surface-mount passive components—Using surface-mount passive components is recommended for high  
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of  
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small  
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray  
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be  
kept as short as possible.  
shutdown function  
Three members of the TLV237x family (TLV2370/3/5) have a shutdown terminal for conserving battery life in  
portable applications. When the shutdown terminal is tied low, the supply current is reduced to 25 µA/channel,  
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the  
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care  
should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place  
the operational amplifier into shutdown.  
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ꢐ ꢙꢛꢗ ꢌꢀ ꢎꢐ ꢘꢌꢁ ꢌꢍ ꢙꢁ ꢎꢋ ꢎꢛ ꢗꢜ ꢝ ꢎꢀ ꢕ ꢜꢕꢚ ꢀꢞ ꢐ ꢝꢘ  
ꢆ ꢑµꢌꢒ ꢓꢔ ꢄ ꢑꢍ ꢕꢖ ꢗꢌꢎ ꢁ ꢑꢀꢐ ꢑꢗꢌꢎ ꢁ ꢎꢘ ꢙꢚꢀꢒ ꢐ ꢚ ꢀꢙ ꢚꢀ  
SLOS270D − MARCH 2001 − REVISED JANUARY 2005  
APPLICATION INFORMATION  
general power dissipation considerations  
For a given θ , the maximum power dissipation is shown in Figure 37 and is calculated by the following formula:  
JA  
T
–T  
MAX  
A
P
+
ǒ Ǔ  
D
q
JA  
Where:  
P
= Maximum power dissipation of TLV237x IC (watts)  
= Absolute maximum junction temperature (150°C)  
= Free-ambient air temperature (°C)  
D
T
MAX  
T
A
θ
= θ + θ  
JA  
JC CA  
θ
θ
= Thermal coefficient from junction to case  
JC  
= Thermal coefficient from case to ambient air (°C/W)  
CA  
MAXIMUM POWER DISSIPATION  
vs  
FREE-AIR TEMPERATURE  
2
T
= 150°C  
PDIP Package  
J
Low-K Test PCB  
1.75  
θ
= 104°C/W  
JA  
1.5  
1.25  
1
MSOP Package  
Low-K Test PCB  
SOIC Package  
Low-K Test PCB  
θ
= 260°C/W  
JA  
θ
= 176°C/W  
JA  
0.75  
0.5  
SOT-23 Package  
Low-K Test PCB  
0.25  
0
θ
= 324°C/W  
JA  
−5540 −25 −10  
5
20 35 50 65 80 95 110 125  
T
A
− Free-Air Temperature − °C  
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.  
Figure 37. Maximum Power Dissipation vs Free-Air Temperature  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Dec-2006  
PACKAGING INFORMATION  
Orderable Device  
TLV2370ID  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SOIC  
D
8
6
6
6
6
8
8
8
8
8
8
5
5
5
5
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLV2370IDBVR  
TLV2370IDBVRG4  
TLV2370IDBVT  
TLV2370IDBVTG4  
TLV2370IDG4  
TLV2370IDR  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOIC  
DBV  
DBV  
DBV  
DBV  
D
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLV2370IDRG4  
TLV2370IP  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
PDIP  
P
50  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
TLV2370IPE4  
TLV2371ID  
PDIP  
P
50  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
SOIC  
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLV2371IDBVR  
TLV2371IDBVRG4  
TLV2371IDBVT  
TLV2371IDBVTG4  
TLV2371IDG4  
TLV2371IDR  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOIC  
DBV  
DBV  
DBV  
DBV  
D
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLV2371IDRG4  
TLV2371IP  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
PDIP  
P
50  
Pb-Free  
(RoHS)  
Call TI  
N / A for Pkg Type  
TLV2371IPE4  
TLV2372ID  
PDIP  
P
50  
Pb-Free  
(RoHS)  
Call TI  
N / A for Pkg Type  
SOIC  
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLV2372IDG4  
TLV2372IDGK  
TLV2372IDGKG4  
TLV2372IDGKR  
SOIC  
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
MSOP  
MSOP  
MSOP  
DGK  
DGK  
DGK  
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Dec-2006  
Orderable Device  
TLV2372IDGKRG4  
TLV2372IDR  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
PREVIEW  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
MSOP  
DGK  
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
SOIC  
PDIP  
D
D
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLV2372IDRG4  
TLV2372IP  
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
P
8
50  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
TLV2372IPE4  
TLV2373ID  
PDIP  
P
8
50  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
SOIC  
SOIC  
MSOP  
MSOP  
MSOP  
MSOP  
SOIC  
SOIC  
PDIP  
D
14  
14  
10  
10  
10  
10  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
16  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLV2373IDG4  
TLV2373IDGS  
TLV2373IDGSG4  
TLV2373IDGSR  
TLV2373IDGSRG4  
TLV2373IDR  
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
DGS  
DGS  
DGS  
DGS  
D
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLV2373IDRG4  
TLV2373IN  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
TLV2373INE4  
TLV2374ID  
PDIP  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLV2374IDG4  
TLV2374IDR  
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLV2374IDRG4  
TLV2374IN  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
TLV2374INE4  
TLV2374IPW  
TLV2374IPWG4  
TLV2374IPWR  
TLV2374IPWRG4  
TLV2375D  
PDIP  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
SOIC  
PW  
PW  
PW  
PW  
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TBD  
Call TI  
Call TI  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Dec-2006  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
SOIC  
SOIC  
Drawing  
TLV2375DR  
TLV2375ID  
PREVIEW  
ACTIVE  
D
D
16  
16  
TBD  
Call TI  
Call TI  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLV2375IDG4  
TLV2375IDR  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
D
D
16  
16  
16  
16  
16  
16  
16  
16  
16  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLV2375IDRG4  
TLV2375IN  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
PDIP  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
TLV2375INE4  
TLV2375IPW  
PDIP  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
PW  
PW  
PW  
PW  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLV2375IPWG4  
TLV2375IPWR  
TLV2375IPWRG4  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 3  
MECHANICAL DATA  
MPDI001A – JANUARY 1995 – REVISED JUNE 1999  
P (R-PDIP-T8)  
PLASTIC DUAL-IN-LINE  
0.400 (10,60)  
0.355 (9,02)  
8
5
0.260 (6,60)  
0.240 (6,10)  
1
4
0.070 (1,78) MAX  
0.325 (8,26)  
0.300 (7,62)  
0.020 (0,51) MIN  
0.015 (0,38)  
Gage Plane  
0.200 (5,08) MAX  
Seating Plane  
0.010 (0,25) NOM  
0.125 (3,18) MIN  
0.100 (2,54)  
0.021 (0,53)  
0.430 (10,92)  
MAX  
0.010 (0,25)  
M
0.015 (0,38)  
4040082/D 05/98  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-001  
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process  
in which TI products or services are used. Information published by TI regarding third-party products or services  
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.  
Use of such information may require a license from a third party under the patents or other intellectual property  
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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without  
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that  
product or service voids all express and any implied warranties for the associated TI product or service and  
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.  
Following are URLs where you can obtain information on other Texas Instruments products and application  
solutions:  
Products  
Applications  
Audio  
Amplifiers  
amplifier.ti.com  
www.ti.com/audio  
Data Converters  
dataconverter.ti.com  
Automotive  
www.ti.com/automotive  
DSP  
dsp.ti.com  
Broadband  
Digital Control  
Military  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
Logic  
interface.ti.com  
logic.ti.com  
Power Mgmt  
Microcontrollers  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
Low Power Wireless www.ti.com/lpw  
Telephony  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address:  
Texas Instruments  
Post Office Box 655303 Dallas, Texas 75265  
Copyright 2006, Texas Instruments Incorporated  
配单直通车
TLV2372IDGKR产品参数
型号:TLV2372IDGKR
Brand Name:Texas Instruments
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
零件包装代码:MSOP
包装说明:VSSOP-8
针数:8
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.33.00.01
风险等级:0.75
放大器类型:OPERATIONAL AMPLIFIER
架构:VOLTAGE-FEEDBACK
最大平均偏置电流 (IIB):0.00006 µA
25C 时的最大偏置电流 (IIB):0.00006 µA
最小共模抑制比:55 dB
标称共模抑制比:72 dB
频率补偿:YES
最大输入失调电流 (IIO):0.00006 µA
最大输入失调电压:4500 µV
JESD-30 代码:R-PDSO-G8
JESD-609代码:e4
长度:3 mm
低-偏置:YES
低-失调:NO
微功率:NO
湿度敏感等级:1
功能数量:2
端子数量:8
最高工作温度:125 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP
封装等效代码:TSSOP8,.19
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TR
峰值回流温度(摄氏度):260
功率:NO
电源:+-1.35/+-8/2.7/16 V
可编程功率:NO
认证状态:Not Qualified
座面最大高度:1.1 mm
最小摆率:1 V/us
标称压摆率:2.4 V/us
子类别:Operational Amplifier
最大压摆率:1.32 mA
供电电压上限:16.5 V
标称供电电压 (Vsup):5 V
表面贴装:YES
技术:CMOS
温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING
端子节距:0.65 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
标称均一增益带宽:3000 kHz
最小电压增益:79432
宽带:YES
宽度:3 mm
Base Number Matches:1
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