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产品型号TLV274CPWG4的Datasheet PDF文件预览

ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢃꢆ ꢀꢁꢂ ꢃꢄ ꢇ  
ꢏ ꢉꢑ ꢒꢓ ꢔ ꢐꢊ ꢕꢖ ꢗꢉꢋ ꢁ ꢐꢀꢍ ꢐꢗꢉꢋ ꢁ ꢍ ꢘꢀ ꢙꢘ ꢀ  
ꢍ ꢙꢚꢗ ꢉꢀ ꢋꢍ ꢛꢉꢁ ꢉꢊ ꢙ ꢁꢋ ꢈꢋ ꢚꢗ ꢜ  
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004  
Operational Amplifier  
D
D
D
D
D
D
D
D
Rail-To-Rail Output  
Wide Bandwidth . . . 3 MHz  
High Slew Rate . . . 2 .4 V/µs  
Supply Voltage Range . . . 2.7 V to 16 V  
Supply Current . . . 550 µA/Channel  
Input Noise Voltage . . . 39 nV/Hz  
Input Bias Current . . . 1 pA  
+
Specified Temperature Range  
0°C to 70°C . . . Commercial Grade  
−40°C to 125°C . . . Industrial Grade  
D
D
Ultrasmall Packaging  
− 5 Pin SOT-23 (TLV271)  
− 8 Pin MSOP (TLV272)  
Ideal Upgrade for TLC27x Family  
description  
The TLV27x takes the minimum operating supply voltage down to 2.7 V over the extended industrial  
temperature range while adding the rail-to-rail output swing feature. This makes it an ideal alternative to the  
TLC27x family for applications where rail-to-rail output swings are essential. The TLV27x also provides 3-MHz  
bandwidth from only 550 µA.  
Like the TLC27x, the TLV27x is fully specified for 5-V and 5-V supplies. The maximum recommended supply  
voltage is 16 V, which allows the devices to be operated from a variety of rechargeable cells ( 8 V supplies down  
to 1.35 V).  
The CMOS inputs enable use in high-impedance sensor interfaces, with the lower voltage operation making  
an attractive alternative for the TLC27x in battery-powered applications.  
All members are available in PDIP and SOIC with the singles in the small SOT-23 package, duals in the MSOP,  
and quads in the TSSOP package.  
The 2.7-V operation makes it compatible with Li-Ion powered systems and the operating supply voltage range  
of many micropower microcontrollers available today including TI’s MSP430.  
SELECTION OF SIGNAL AMPLIFIER PRODUCTS†  
RAIL-  
TO-  
RAIL  
V
(µV)  
Iq/Ch  
(µA)  
GBW  
(MHz)  
SR  
(V/µs)  
IO  
DEVICE  
TLV27x  
V
(V)  
I
IB  
(pA)  
SHUTDOWN  
SINGLES/DUALS/QUADS  
DD  
2.7−16  
3−16  
500  
1100  
500  
300  
150  
250  
300  
550  
675  
550  
1100  
550  
600  
725  
1
1
1
1
3
2.4  
3.6  
2.4  
3.6  
1.6  
1.5  
1.4  
O
I/O  
O
S/D/Q  
S/D/Q  
S/D/Q  
D/Q  
TLC27x  
1.7  
3
TLV237x  
TLC227x  
TLV246x  
TLV247x  
TLV244x  
2.7−16  
4−16  
Yes  
2.2  
6.4  
2.8  
1.8  
2.7−6  
2.7−6  
2.7−10  
1300  
Yes  
Yes  
I/O  
I/O  
O
S/D/Q  
S/D/Q  
D/Q  
2
1
Typical values measured at 5 V, 25°C  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢀꢩ  
Copyright 2001−2004, Texas Instruments Incorporated  
ꢥ ꢩ ꢦ ꢥꢞ ꢟꢲ ꢡꢠ ꢤ ꢬꢬ ꢪꢤ ꢢ ꢤ ꢣ ꢩ ꢥ ꢩ ꢢ ꢦ ꢮ  
1
WWW.TI.COM  
ꢍꢙ ꢚ ꢗꢉꢀ ꢋ ꢍꢛ ꢉ ꢁ ꢉꢊ ꢙꢁ ꢋ ꢈꢋ ꢚ ꢗꢜ  
ꢏ ꢉꢑ ꢒ ꢓ ꢔ ꢐꢊꢕꢖ ꢗꢉ ꢋ ꢁꢐꢀꢍ ꢐꢗꢉꢋ ꢁ ꢍ ꢘꢀ ꢙꢘꢀ  
µ  
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004  
FAMILY PACKAGE TABLE  
PACKAGE TYPES  
NUMBER OF  
DEVICE  
UNIVERSAL  
EVM BOARD  
SHUTDOWN  
CHANNELS  
PDIP  
SOIC  
SOT-23 TSSOP MSOP  
TLV271  
TLV272  
TLV274  
1
2
4
8
8
8
8
5
14  
8
Refer to the EVM  
Selection Guide  
(Lit# SLOU060)  
14  
14  
TLV271 AVAILABLE OPTIONS  
PACKAGED DEVICES  
V
IO  
MAX AT  
25°C  
SOT-23  
T
A
SMALL OUTLINE  
PLASTIC DIP  
(D)  
(P)  
(DBV)  
SYMBOL  
VBHC  
0°C to 70°C  
TLV271CD  
TLV271ID  
TLV271CDBV  
TLV271IDBV  
5 mV  
40°C to 125°C  
VBHI  
TLV271IP  
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV271IDR).  
This package is only available taped and reeled. For standard quantities (3,000 pieces per reel), add an R suffix (e.g., TLV270IDBVR). For smaller  
quantities (250 pieces per mini-reel), add a T suffix to the part number (e.g., TLV270IDBVT).  
TLV272 AVAILABLE OPTIONS  
PACKAGED DEVICES  
V
IO  
MAX AT  
25°C  
MSOP  
T
A
SMALL OUTLINE  
PLASTIC DIP  
(P)  
§
§
(D)  
(DGK)  
SYMBOL  
AVF  
0°C to 70°C  
TLV272CD  
TLV272ID  
TLV272CDGK  
TLV272IDGK  
5 mV  
40°C to 125°C  
AVG  
TLV272IP  
§
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV272IDR).  
TLV274 AVAILABLE OPTIONS  
PACKAGED DEVICES  
T
A
V
IO  
MAX AT 25°C  
SMALL OUTLINE  
PLASTIC DIP  
(N)  
TSSOP  
(PW)  
(D)  
0°C to 70°C  
TLV274CD  
TLV274ID  
TLV274CPW  
TLV274IPW  
5 mV  
40°C to 125°C  
TLV274IN  
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV274IDR).  
2
WWW.TI.COM  
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢃꢆ ꢀꢁꢂ ꢃꢄ ꢇ  
ꢏ ꢉꢑ ꢒꢓ ꢔ ꢐꢊ ꢕꢖ ꢗꢉꢋ ꢁ ꢐꢀꢍ ꢐꢗꢉꢋ ꢁ ꢍ ꢘꢀ ꢙꢘ ꢀ  
ꢍ ꢙꢚꢗ ꢉꢀ ꢋꢍ ꢛꢉꢁ ꢉꢊ ꢙ ꢁꢋ ꢈꢋ ꢚꢗ ꢜ  
ꢈꢉ  
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004  
(1)  
TLV27x PACKAGE PINOUTS  
TLV271  
TLV271  
D OR P PACKAGE  
(TOP VIEW)  
DBV PACKAGE  
(TOP VIEW)  
1
2
3
5
4
V
DD  
OUT  
GND  
NC  
IN−  
NC  
1
2
3
4
8
7
6
5
V
DD  
IN+  
OUT  
NC  
GND  
IN−  
IN+  
TLV274  
TLV272  
D, N, OR PW PACKAGE  
D, DGK, OR P PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1OUT  
1IN−  
1IN+  
GND  
V
DD  
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OUT  
1IN−  
1IN+  
4OUT  
4IN−  
4IN+  
GND  
3IN+  
3IN−  
3OUT  
2OUT  
2IN−  
2IN+  
V
DD  
2IN+  
2IN−  
8
2OUT  
NC − No internal connection  
(1) SOT−23 may or may not be indicated  
TYPICAL PIN 1 INDICATORS  
Pin 1  
Pin 1  
Pin 1  
Pin 1  
Printed or  
Molded Dot  
Stripe  
Bevel Edges  
Molded ”U” Shape  
3
WWW.TI.COM  
ꢍꢙ ꢚ ꢗꢉꢀ ꢋ ꢍꢛ ꢉ ꢁ ꢉꢊ ꢙꢁ ꢋ ꢈꢋ ꢚ ꢗꢜ  
ꢏ ꢉꢑ ꢒ ꢓ ꢔ ꢐꢊꢕꢖ ꢗꢉ ꢋ ꢁꢐꢀꢍ ꢐꢗꢉꢋ ꢁ ꢍ ꢘꢀ ꢙꢘꢀ  
µ  
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage, V  
Differential input voltage, V  
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V  
DD  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
V
ID  
DD  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2 V to V  
Input current range, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA  
Output current range, I  
+ 0.2 V  
I
DD  
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA  
O
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table  
Operating free-air temperature range, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
A
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C  
Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C  
J
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
stg  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: All voltage values, except differential voltages, are with respect to GND.  
DISSIPATION RATING TABLE  
θ
θ
T
25°C  
T = 25°C  
A
POWER RATING  
JC  
JA  
A
PACKAGE  
(°C/W)  
(°C/W)  
POWER RATING  
D (8)  
38.3  
176  
710 mW  
396 mW  
D (14)  
D (16)  
26.9  
25.7  
55  
122.3  
114.7  
324.1  
294.3  
259.96  
1022 mW  
1090 mW  
385 mW  
425 mW  
481 mW  
531 mW  
567 mW  
201 mW  
221 mW  
250 mW  
DBV (5)  
DBV (6)  
DGK (8)  
55  
54.23  
DGS (10)  
N (14, 16)  
P (8)  
54.1  
32  
257.71  
78  
485 mW  
1600 mW  
1200 mW  
720 mW  
774 mW  
252 mW  
833 mW  
625 mW  
374 mW  
403 mW  
41  
104  
PW (14)  
PW (16)  
29.3  
28.7  
173.6  
161.4  
recommended operating conditions  
MIN  
MAX  
16  
UNIT  
Single supply  
Split supply  
2.7  
1.35  
0
Supply voltage, V  
DD  
V
V
8
Common-mode input voltage range, V  
ICR  
V
DD  
−1.35  
70  
C-suffix  
I-suffix  
0
Operating free-air temperature, T  
°C  
A
−40  
125  
4
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ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢄ ꢃꢆ ꢀꢁꢂ ꢃꢄ ꢇ  
ꢈꢉ  
ꢁꢌ  
µꢉ  
ꢍ ꢙꢚꢗ ꢉꢀ ꢋꢍ ꢛꢉꢁ ꢉꢊ ꢙ ꢁꢋ ꢈꢋ ꢚꢗ ꢜ  
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004  
electrical characteristics at specified free-air temperature, V  
otherwise noted)  
= 2.7 V, 5 V, and 5 V (unless  
DD  
dc performance  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
T
A
UNIT  
25°C  
0.5  
5
7
V
Input offset voltage  
Offset voltage drift  
mV  
V
R
= V /2,  
= 10 kΩ,  
V
R
= V /2,  
= 50 Ω  
IO  
IC  
L
DD  
O DD  
S
Full range  
α
VIO  
25°C  
25°C  
2
µV/°C  
58  
55  
70  
V
R
= 0 to V −1.35V,  
DD  
= 50 Ω  
IC  
V
DD  
V
DD  
V
DD  
V
DD  
V
DD  
V
DD  
= 2.7 V  
= 5 V  
Full range  
25°C  
S
65  
80  
85  
V
R
= 0 to V −1.35V,  
DD  
= 50 ,  
IC  
CMRR Common-mode rejection ratio  
dB  
Full range  
25°C  
62  
S
69  
V
R
= −5 to V −1.35V,  
DD  
= 50 ,  
IC  
=
5 V  
Full range  
25°C  
66  
S
97  
106  
110  
115  
= 2.7 V  
= 5 V  
Full range  
25°C  
76  
100  
86  
Large-signal differential voltage  
amplification  
V
= V /2,  
DD  
O(PP)  
A
VD  
dB  
R = 10 kΩ  
Full range  
25°C  
L
100  
90  
=
5 V  
Full range  
Full range is 0°C to 70°C for C suffix and full range is 40°C to 125°C for I suffix. If not specified, full range is 40°C to 125°C.  
input characteristics  
PARAMETER  
TEST CONDITIONS  
T
MIN  
TYP  
MAX  
60  
UNIT  
A
25°C  
70°C  
125°C  
25°C  
70°C  
125°C  
25°C  
25°C  
1
100  
1000  
60  
I
I
Input offset current  
Input bias current  
pA  
IO  
V
V
= 5 V,  
V = V /2,  
IC DD  
DD  
= V /2, R = 50 Ω  
1
O
DD  
S
100  
1000  
pA  
IB  
r
Differential input resistance  
1000  
8
GΩ  
i(d)  
C
Common-mode input capacitance  
f = 21 kHz  
pF  
IC  
5
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µ  
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004  
electrical characteristics at specified free-air temperature, V  
otherwise noted)  
= 2.7 V, 5 V, and 5 V (unless  
DD  
output characteristics  
PARAMETER  
TEST CONDITIONS  
MIN  
2.55  
2.48  
4.9  
TYP  
MAX  
T
A
UNIT  
25°C  
Full range  
25°C  
2.58  
V
V
V
V
V
V
V
V
V
V
V
V
= 2.7 V  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
DD  
4.93  
4.96  
2.1  
V
V
V
V
= V /2,  
DD  
I
I
I
I
= −1 mA  
= −5 mA  
= 1 mA  
= 5 V  
IC  
IC  
IC  
IC  
OH  
OH  
OL  
OL  
Full range  
25°C  
4.85  
4.92  
4.9  
=
5 V  
Full range  
25°C  
V
OH  
High-level output voltage  
V
1.9  
= 2.7 V  
= 5 V  
Full range  
25°C  
1.5  
4.6  
4.68  
4.84  
0.1  
= V /2,  
DD  
Full range  
25°C  
4.5  
4.7  
=
5 V  
Full range  
25°C  
4.65  
0.15  
0.22  
0.1  
= 2.7 V  
= 5 V  
Full range  
25°C  
0.05  
= V /2,  
DD  
Full range  
25°C  
0.15  
−4.95 −4.92  
−4.9  
=
5 V  
Full range  
25°C  
V
OL  
Low-level output voltage  
V
0.5  
0.7  
1.1  
= 2.7 V  
= 5 V  
Full range  
25°C  
0.28  
0.4  
= V /2,  
DD  
= 5 mA  
Full range  
25°C  
0.5  
−4.84  
−4.7  
−4.65  
=
5 V  
Full range  
25°C  
Positive rail  
Negative rail  
Positive rail  
Negative rail  
Positive rail  
Negative rail  
4
5
V
O
V
O
V
O
= 0.5 V from rail, V  
= 0.5 V from rail, V  
= 0.5 V from rail, V  
= 2.7 V  
= 5 V  
DD  
DD  
DD  
25°C  
25°C  
7
I
O
Output current  
mA  
25°C  
8
25°C  
13  
12  
= 10 V  
25°C  
Full range is 0°C to 70°C for C suffix and full range is 40°C to 125°C for I suffix. If not specified, full range is 40°C to 125°C.  
Depending on package dissipation rating  
6
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SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004  
electrical characteristics at specified free-air temperature, V  
otherwise noted) (continued)  
= 2.7 V, 5 V, and 5 V (unless  
DD  
power supply  
PARAMETER  
TEST CONDITIONS  
T
A
MIN  
TYP  
470  
MAX  
560  
UNIT  
V
V
= 2.7 V  
= 5 V  
25°C  
25°C  
DD  
550  
625  
660  
DD  
I
Supply current (per channel)  
V
V
= V /2  
DD  
µA  
DD  
O
25°C  
800  
V
= 10 V  
DD  
IC  
Full range  
25°C  
1000  
70  
65  
80  
Supply voltage rejection ratio  
= 2.7 V to 16 V,  
V
= V /2,  
DD  
DD  
PSRR  
dB  
(V  
DD  
/V  
IO  
)
No load  
Full range  
Full range is 0°C to 70°C for C suffix and full range is 40°C to 125°C for I suffix. If not specified, full range is 40°C to 125°C.  
dynamic performance  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
2.4  
3
MAX  
UNIT  
T
A
25°C  
25°C  
V
V
= 2.7 V  
DD  
R
= 2 kΩ,  
C = 10 pF  
L
UGBW Unity gain bandwidth  
MHz  
L
= 5 V to 10 V  
DD  
25°C  
1.35  
1
2.1  
V
V
V
= 2.7 V  
= 5 V  
V/µs  
V/µs  
V/µs  
DD  
DD  
DD  
Full range  
25°C  
1.45  
1.2  
1.8  
1.3  
2.4  
2.6  
V
C
= V /2,  
DD  
O(PP)  
L
SR  
Slew rate at unity gain  
= 50 pF,  
R = 10 k,  
Full range  
25°C  
L
=
5 V  
Full range  
25°C  
φ
m
Phase margin  
Gain margin  
65  
18  
°
R
R
= 2 kΩ  
= 2 kΩ  
C
C
= 10 pF  
= 10 pF  
L
L
L
L
25°C  
dB  
V
V
C
= 2.7 V,  
DD  
= 1 V,  
A
= −1,  
= 2 kΩ  
0.1%  
0.1%  
2.9  
2
(STEP)PP  
= 10 pF,  
V
R
L
L
t
s
Settling time  
25°C  
µs  
V
V
C
= 5 V, 5 V,  
DD  
(STEP)PP  
= 47 pF,  
= 1 V,  
A
= −1,  
= 2 kΩ  
V
L
R
L
Full range is 0°C to 70°C for C suffix and full range is 40°C to 125°C for I suffix. If not specified, full range is 40°C to 125°C.  
noise/distortion performance  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
0.02%  
0.05%  
0.18%  
0.02%  
0.09%  
0.50%  
39  
MAX  
UNIT  
T
A
A
V
= 1  
V
V
R
= 2.7 V,  
DD  
O(PP)  
L
A
= 10  
= 100  
= 1  
= V /2 V,  
DD  
25°C  
25°C  
V
= 2 k, f = 10 kHz  
A
V
THD + N Total harmonic distortion plus noise  
A
V
V
V
R
= 5 V, 5 V,  
= V /2 V,  
DD  
O(PP)  
A
V
= 10  
= 100  
DD  
= 2 k, f = 10K  
L
A
V
f = 1 kHz  
f = 10 kHz  
f = 1 kHz  
nV/Hz  
fA/Hz  
V
I
Equivalent input noise voltage  
Equivalent input noise current  
25°C  
25°C  
n
35  
0.6  
n
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SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004  
TYPICAL CHARACTERISTICS  
Table of Graphs  
FIGURE  
1
CMRR  
Common-mode rejection ratio  
Input bias and offset current  
Low-level output voltage  
High-level output voltage  
Peak-to-peak output voltage  
Supply current  
vs Frequency  
vs Free-air temperature  
vs Low-level output current  
vs High-level output current  
vs Frequency  
2
V
V
V
3, 5, 7  
4, 6, 8  
9
OL  
OH  
O(PP)  
I
vs Supply voltage  
vs Frequency  
10  
DD  
PSRR  
Power supply rejection ratio  
Differential voltage gain & phase  
Gain-bandwidth product  
11  
A
VD  
vs Frequency  
12  
vs Free-air temperature  
vs Supply voltage  
vs Free-air temperature  
vs Capacitive load  
vs Frequency  
13  
14  
SR  
Slew rate  
15  
φ
m
Phase margin  
16  
V
n
Equivalent input noise voltage  
Voltage-follower large-signal pulse response  
Voltage-follower small-signal pulse response  
Inverting large-signal response  
Inverting small-signal response  
Crosstalk  
17  
18, 19  
20  
21, 22  
23  
vs Frequency  
24  
8
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ꢈꢉ  
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004  
TYPICAL CHARACTERISTICS  
COMMON-MODE REJECTION RATIO  
LOW-LEVEL OUTPUT VOLTAGE  
vs  
INPUT BIAS AND OFFSET CURRENT  
vs  
vs  
LOW-LEVEL OUTPUT CURRENT  
FREE-AIR TEMPERATURE  
FREQUENCY  
2.80  
2.40  
2.00  
1.60  
1.20  
0.80  
0.40  
0.00  
300  
120  
V
= 2.7 V  
DD  
V
V
= 2.7 V, 5 V and 10 V  
DD  
= V /2  
250  
200  
150  
100  
50  
T
A
= 125 °C  
100  
80  
IC  
DD  
V
= 5 V, 10 V  
DD  
60  
V
= 2.7 V  
DD  
T
A
= 70 °C  
40  
20  
0
T
A
= 25 °C  
T
A
= 0 °C  
0
T
A
= 40 °C  
−50  
0
2
4
6
8
10 12 14 16 18 20 22 24  
10  
100  
1 k  
10 k  
100 k  
1 M  
−402510 5 20 35 50 65 80 95 110 125  
I
− Low-Level Output Current − mA  
OL  
f − Frequency − Hz  
T
A
− Free-Air Temperature − °C  
Figure 2  
Figure 1  
Figure 3  
HIGH-LEVEL OUTPUT VOLTAGE  
vs  
HIGH-LEVEL OUTPUT CURRENT  
LOW-LEVEL OUTPUT VOLTAGE  
vs  
LOW-LEVEL OUTPUT CURRENT  
HIGH-LEVEL OUTPUT VOLTAGE  
vs  
HIGH-LEVEL OUTPUT CURRENT  
5.00  
5.00  
4.50  
4.00  
3.50  
3.00  
2.50  
2.00  
1.50  
1.00  
0.50  
0.00  
2.80  
2.40  
2.00  
1.60  
1.20  
0.80  
0.40  
0.00  
V
= 5 V  
V
= 5 V  
DD  
CC  
V
= 2.7 V  
DD  
4.50  
4.00  
3.50  
3.00  
T
= −40°C  
A
T
= 125 °C  
A
T
A
= 0°C  
T
=−40°C  
A
T
A
= 70 °C  
T
= 125°C  
= 70°C  
A
2.50  
2.00  
T
= 25°C  
T
A
A
T
= 25 °C  
A
T
= 25°C  
= 0°C  
A
1.50  
1.00  
0.50  
0.00  
T
A
= 70°C  
T
= 0 °C  
A
T
A
T
A
= −40 °C  
T
A
= 125°C  
0
5
10 15 20 25 30 35 40 45  
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70  
0
1
2
3
4
5
6
7
8
9
10 11 12  
I
− Low-Level Output Current − mA  
I
− High-Level Output Current − mA  
I
− High-Level Output Current − mA  
OL  
OH  
OH  
Figure 5  
Figure 4  
Figure 6  
PEAK-TO-PEAK OUTPUT VOLTAGE  
vs  
HIGH-LEVEL OUTPUT VOLTAGE  
vs  
HIGH-LEVEL OUTPUT CURRENT  
LOW-LEVEL OUTPUT VOLTAGE  
vs  
LOW-LEVEL OUTPUT CURRENT  
FREQUENCY  
11  
10  
8
10  
8
V
= 10 V  
DD  
V
= 10 V  
V
= 10 V  
10  
9
DD  
DD  
T
A
=125°C  
A
V
= −10  
T
=70°C  
=25°C  
R
C
T
= 2 kΩ  
= 10 pF  
= 25°C  
8
A
L
L
A
T
A
= −40°C  
7
T
A
6
6
6
THD = 5%  
T
=0°C  
A
5
T
= 0°C  
A
4
4
V
= 5 V  
DD  
T
=−40°C  
4
A
T
= 25°C  
A
3
2
2
T
= 70°C  
2
1
0
A
V
= 2.7 V  
DD  
T
A
= 125°C  
0
0
10  
100  
1 k  
10 k 100 k 1 M  
10 M  
20  
40  
60  
80  
100  
120  
0
0
20  
40  
60  
80  
100  
120  
f − Frequency − Hz  
I
− Low-Level Output Current − mA  
I
− High-Level Output Current − mA  
OL  
OH  
Figure 8  
Figure 7  
Figure 9  
9
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µ  
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004  
TYPICAL CHARACTERISTICS  
POWER SUPPLY REJECTION RATIO  
SUPPLY CURRENT  
vs  
vs  
FREQUENCY  
SUPPLY VOLTAGE  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0.0  
120  
100  
A
V
= 1  
T
A
= 25°C  
V
IC  
= V / 2  
DD  
T
A
= 125°C  
T
= 70°C  
V
= 5 V, 10 V  
A
DD  
80  
60  
V
= 2.7 V  
DD  
T
A
= 25°C  
40  
T
A
= 0°C  
T
A
= −40°C  
20  
0
10  
100  
1 k  
10 k  
100 k  
1 M  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
f − Frequency − Hz  
V
− Supply Voltage − V  
DD  
Figure 11  
Figure 10  
DIFFERENTIAL VOLTAGE GAIN AND PHASE  
GAIN BANDWIDTH PRODUCT  
vs  
vs  
FREQUENCY  
FREE-AIR TEMPERATURE  
180  
135  
90  
120  
100  
80  
4.0  
3.5  
V
= 10 V  
Phase  
DD  
3.0  
2.5  
45  
60  
V
= 5 V  
DD  
0
40  
2.0  
1.5  
1.0  
Gain  
V
= 2.7 V  
DD  
−45  
−90  
−135  
−180  
20  
V
=5 V  
0
DD  
L
L
R =2 kΩ  
C =10 pF  
−20  
0.5  
0.0  
T
=25°C  
A
−40  
10  
−40 −2510  
5
20 35 50 65 80 95 110 125  
100  
1 k  
10 k 100 k 1 M  
10 M  
T
A
− Free-Air Temperature − °C  
f − Frequency − Hz  
Figure 13  
Figure 12  
SLEW RATE  
vs  
FREE-AIR TEMPERATURE  
SLEW RATE  
vs  
SUPPLY VOLTAGE  
PHASE MARGIN  
vs  
CAPACITIVE LOAD  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
V
= 5 V  
DD  
R = 2 kΩ  
SR−  
3.0  
2.5  
2.0  
L
T
= 25°C  
= Open Loop  
A
SR−  
SR+  
A
V
R
= 100  
null  
SR+  
1.5  
1.0  
R
= 0  
null  
V
A
R
= 5 V  
= 1  
= 10 kΩ  
= 50 pF  
A
= 1  
DD  
V
L
L
V
L
L
R
C
T
= 10 kΩ  
= 50 pF  
= 25°C  
R
= 50  
null  
0.5  
0.0  
C
A
V = 3 V  
I
−40 −25 −10  
5
20 35 50 65 80 95 110 125  
2.5  
4.5  
6.5  
8.5  
10.5 12.5 14.5  
10  
100  
1000  
T
A
− Free-Air Temperature − °C  
V
− Supply Voltage −V  
CC  
C
− Capacitive Load − pF  
L
Figure 15  
Figure 14  
Figure 16  
10  
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SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004  
TYPICAL CHARACTERISTICS  
EQUIVALENT INPUT NOISE VOLTAGE  
VOLTAGE-FOLLOWER LARGE-SIGNAL  
vs  
PULSE RESPONSE  
FREQUENCY  
100  
90  
4
V
= 2.7, 5, 10 V  
DD  
= 25°C  
3
2
T
A
80  
V
A
= 5 V  
= 1  
DD  
V
1
0
V
70  
60  
I
R
C
= 2 kΩ  
= 10 pF  
L
L
V = 3 V  
I
PP  
50  
T
= 25°C  
A
40  
30  
3
2
20  
1
0
V
O
10  
0
0
2
4
6
8
10 12 14 16 18  
10  
100  
1 k  
10 k  
100 k  
f − Frequency − Hz  
t − Time − µs  
Figure 18  
Figure 17  
VOLTAGE-FOLLOWER SMALL-SIGNAL  
PULSE RESPONSE  
VOLTAGE-FOLLOWER LARGE-SIGNAL  
PULSE RESPONSE  
8
0.12  
6
0.08  
0.04  
0.00  
V
= 10 V  
DD  
= 1  
V
A
= 5 V  
= 1  
DD  
V
4
2
0
A
V
R
C
= 2 kΩ  
= 10 pF  
L
L
I
V
R
= 2 kΩ  
I
L
V
V
I
C
= 10 pF  
L
V = 6 V  
T
A
PP  
= 25°C  
V = 100 mV  
I
PP  
T
A
= 25°C  
0.12  
0.08  
0.04  
0.00  
6
4
2
0
V
O
O
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8  
0
2
4
6
8
10 12 14 16 18  
t − Time − µs  
t − Time − µs  
Figure 20  
Figure 19  
INVERTING LARGE-SIGNAL RESPONSE  
4
INVERTING LARGE-SIGNAL RESPONSE  
8
V
I
3
2
1
6
V
A
= 10 V  
= V = −1  
I
V
A
R
= 5 V  
= 1  
= 2 kΩ  
= 10 pF  
DD  
V
DD  
V
L
L
I
4
2
0
R
C
T
= 2 kΩ  
= 10 pF  
= 25°C  
L
L
A
V
I
C
0
V = 3 V  
PP  
T
A
= 25°C  
6
4
2
3
V
O
2
1
0
0
V
O
0
2
4
6
8
10 12 14 16  
0
2
4
6
8
10 12 14 16  
t − Time − µs  
t − Time − µs  
Figure 22  
Figure 21  
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µ  
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004  
TYPICAL CHARACTERISTICS  
CROSSTALK  
vs  
FREQUENCY  
INVERTING SMALL-SIGNAL RESPONSE  
0
V
= 2.7, 5, & 15 V  
DD  
V = 1 V /2  
−20  
I
DD  
0.10  
0.05  
0.00  
A
V
= 1  
R
T
A
= 2 kΩ  
= 25°C  
L
−40  
−60  
V
= 5 V  
DD  
A
= V = −1  
V
I
V
I
R
C
= 2 kΩ  
= 10 pF  
L
L
V = 100 mV  
I
pp  
−80  
0.10  
0.05  
0.00  
T
= 25°C  
A
V
O
−100  
−120  
−140  
Crosstalk  
10  
100  
1 k  
10 k  
100 k  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5  
f − Frequency − Hz  
t − Time − µs  
Figure 24  
Figure 23  
APPLICATION INFORMATION  
driving a capacitive load  
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device’s  
phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than  
10 pF, it is recommended that a resistor be placed in series (R  
) with the output of the amplifier, as shown  
NULL  
in Figure 25. A minimum value of 20 should work well for most applications.  
R
F
R
G
R
NULL  
+
Input  
Output  
LOAD  
C
V
DD  
/2  
Figure 25. Driving a Capacitive Load  
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ꢈꢉ  
µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004  
APPLICATION INFORMATION  
offset voltage  
The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times  
OO  
IO  
IB  
the corresponding gains. The following schematic and formula can be used to calculate the output offset  
voltage:  
R
F
I
IB−  
R
G
+
R
R
+
F
F
V
I
V
+ V  
1 ) ǒ Ǔ " I  
R
1 ) ǒ Ǔ " I  
R
V
O
ǒ Ǔ ǒ Ǔ  
OO  
IO  
IB)  
S
IB–  
F
R
R
G
G
R
S
I
IB+  
Figure 26. Output Offset Voltage Model  
general configurations  
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often  
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier  
(see Figure 27).  
R
R
F
G
V
R
R
O
F
1
ǒ
Ǔ
+
+
ǒ
1 )  
Ǔ
V
1 ) sR1C1  
I
G
V
DD  
/2  
1
V
O
f
+
–3dB  
V
I
2pR1C1  
R1  
C1  
Figure 27. Single-Pole Low-Pass Filter  
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this  
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.  
Failure to do this can result in phase shift of the amplifier.  
C1  
R1 = R2 = R  
C1 = C2 = C  
Q = Peaking Factor  
(Butterworth Q = 0.707)  
+
_
V
I
1
R1  
R2  
f
+
–3dB  
2pRC  
C2  
R
F
1
R
=
G
R
F
2 −  
)
R
(
Q
G
V
DD  
/2  
Figure 28. 2-Pole Low-Pass Sallen-Key Filter  
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µ  
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004  
APPLICATION INFORMATION  
circuit layout considerations  
To achieve the levels of high performance of the TLV27x, follow proper printed-circuit board design techniques.  
A general set of guidelines is given in the following.  
D
Ground planes—It is highly recommended that a ground plane be used on the board to provide all  
components with a low inductive ground connection. However, in the areas of the amplifier inputs and  
output, the ground plane can be removed to minimize the stray capacitance.  
D
Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic  
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers  
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal  
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply  
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less  
effective. The designer should strive for distances of less than 0.1 inches between the device power  
terminals and the ceramic capacitors.  
D
D
Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins  
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board  
is the best implementation.  
Short trace runs/compact part placements—Optimum high performance is achieved when stray series  
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,  
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of  
the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance at the  
input of the amplifier.  
D
Surface-mount passive components—Using surface-mount passive components is recommended for high  
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of  
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small  
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray  
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be  
kept as short as possible.  
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µ  
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004  
APPLICATION INFORMATION  
general power dissipation considerations  
For a given θ , the maximum power dissipation is shown in Figure 29 and is calculated by the following formula:  
JA  
T
–T  
MAX  
A
P
+
ǒ Ǔ  
D
q
JA  
Where:  
P
= Maximum power dissipation of TLV27x IC (watts)  
= Absolute maximum junction temperature (150°C)  
= Free-ambient air temperature (°C)  
D
T
MAX  
T
A
θ
= θ + θ  
JA  
JC CA  
θ
θ
= Thermal coefficient from junction to case  
JC  
= Thermal coefficient from case to ambient air (°C/W)  
CA  
MAXIMUM POWER DISSIPATION  
vs  
FREE-AIR TEMPERATURE  
2
T
= 150°C  
PDIP Package  
J
Low-K Test PCB  
1.75  
θ
= 104°C/W  
JA  
1.5  
1.25  
1
MSOP Package  
Low-K Test PCB  
SOIC Package  
Low-K Test PCB  
θ
= 260°C/W  
JA  
θ
= 176°C/W  
JA  
0.75  
0.5  
SOT-23 Package  
Low-K Test PCB  
0.25  
0
θ
= 324°C/W  
JA  
−5540 −25 −10  
5
20 35 50 65 80 95 110 125  
T
A
− Free-Air Temperature − °C  
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.  
Figure 29. Maximum Power Dissipation vs Free-Air Temperature  
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µ
SLOS351D − MARCH 2001 − REVISED FEBRUARY 2004  
APPLICATION INFORMATION  
macromodel information  
Macromodel information provided was derived using Microsim PartsRelease 9.1, the model generation  
software used with Microsim PSpice. The Boyle macromodel (see Note 4) and subcircuit in Figure 30 are  
generated using TLV27x typical electrical and operating characteristics at T = 25°C. Using this information,  
A
output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):  
D
D
D
D
D
D
Maximum positive output voltage swing  
Maximum negative output voltage swing  
Slew rate  
D
D
D
D
D
D
Unity-gain frequency  
Common-mode rejection ratio  
Phase margin  
Quiescent power dissipation  
Input bias current  
DC output resistance  
AC output resistance  
Short-circuit output current limit  
Open-loop voltage amplification  
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal  
of Solid-State Circuits, SC-9, 353 (1974).  
3
99  
V
DD  
+
egnd  
rd1  
11  
rd2  
12  
rss  
ro2  
css  
fb  
rp  
c1  
7
+
c2  
vlim  
8
1
2
+
r2  
9
6
IN+  
IN−  
vc  
D
S
D
S
+
vb  
ga  
G
G
ro1  
gcm  
ioff  
53  
OUT  
dp  
5
dlp  
dln  
91  
90  
92  
10  
+
+
iss  
dc  
vlp  
hlim  
vln  
+
GND  
+ 54  
4
de  
ve  
*DEVICE=amp_tlv27x_highVdd,OP AMP,NJF,INT  
ga  
6
0
11 12 16.272E−6  
10 99 6.8698E−9  
dc 1.3371E−6  
vlim 1K  
* amp_tlv_27x_highVdd operational amplifier ”macromodel”  
gcm  
iss  
0
6
* subcircuit updated using Model Editor release 9.1 on 05/15/00  
* at 14:40 Model Editor is an OrCAD product.  
*
10  
90  
11  
12  
6
4
hlim  
j1  
J2  
r2  
rd1  
rd2  
ro1  
ro2  
rp  
rss  
vb  
vc  
ve  
vlim  
vlp  
vln  
.model  
.model dy  
.model jx1  
.model jx2  
.ends  
0
2
10 jx1  
* connections:  
non-inverting input  
| inverting input  
1
10 jx2  
*
*
*
*
*
9
100.00E3  
61.456E3  
61.456E3  
10  
| | positive power supply  
| | | negative power supply  
| | | | output  
3
11  
12  
5
3
8
| | | | |  
7
99  
4
10  
.subckt amp_tlv27x_highVdd 1 2 3 4 5  
*
3
150.51E3  
149.58E6  
dc 0  
10  
9
99  
0
c1  
11  
6
12 457.48E−15  
c2  
7
5.0000E−12  
3
53  
4
dc .78905  
dc .78905  
dc 0  
dc 14.200  
dc 14.200  
css  
dc  
10  
5
99 1.1431E−12  
53 dy  
54  
7
8
de  
54  
90  
92  
4
99  
7
5
dy  
91  
0
0
dlp  
dln  
dp  
egnd  
fb  
91 dx  
90 dx  
92  
dx  
D(Is=800.00E−18)  
3
0
dx  
D(Is=800.00E−18 Rs=1m Cjo=10p)  
poly(2) (3,0) (4,0) 0 .5 .5  
NJF(Is=500.00E−15 Beta=198.03E−6 Vto=−1)  
NJF(Is=500.00E−15 Beta=198.03E−6 Vto=−1)  
99 poly(5) vb vc ve vlp vln 0  
176.02E6 −1E3 1E3 180E6  
−180E6  
Figure 30. Boyle Macromodel and Subcircuit  
PSpice and Parts are trademarks of MicroSim Corporation.  
16  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
16-Aug-2012  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
TLV271CD  
TLV271CDBVR  
TLV271CDBVRG4  
TLV271CDBVT  
TLV271CDBVTG4  
TLV271CDG4  
TLV271CDR  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOIC  
D
8
5
5
5
5
8
8
8
8
5
5
5
5
8
75  
3000  
3000  
250  
250  
75  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
DBV  
DBV  
DBV  
DBV  
D
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
SOIC  
D
2500  
2500  
75  
Green (RoHS  
& no Sb/Br)  
TLV271CDRG4  
TLV271ID  
SOIC  
D
Green (RoHS  
& no Sb/Br)  
SOIC  
D
Green (RoHS  
& no Sb/Br)  
TLV271IDBVR  
TLV271IDBVRG4  
TLV271IDBVT  
TLV271IDBVTG4  
TLV271IDG4  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOIC  
DBV  
DBV  
DBV  
DBV  
D
3000  
3000  
250  
250  
75  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
TLV271IP  
TLV271IPE4  
TLV272CD  
ACTIVE  
ACTIVE  
ACTIVE  
PDIP  
PDIP  
SOIC  
P
P
D
8
8
8
50  
50  
75  
Pb-Free (RoHS)  
Pb-Free (RoHS)  
CU NIPDAU N / A for Pkg Type  
CU NIPDAU N / A for Pkg Type  
CU NIPDAU Level-1-260C-UNLIM  
Green (RoHS  
& no Sb/Br)  
TLV272CDG4  
ACTIVE  
SOIC  
D
8
75  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
16-Aug-2012  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
TLV272CDGK  
TLV272CDGKG4  
TLV272CDGKR  
TLV272CDGKRG4  
TLV272CDR  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
SOIC  
DGK  
DGK  
DGK  
DGK  
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
80  
80  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
2500  
2500  
2500  
2500  
75  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
TLV272CDRG4  
TLV272ID  
SOIC  
D
Green (RoHS  
& no Sb/Br)  
SOIC  
D
Green (RoHS  
& no Sb/Br)  
TLV272IDG4  
SOIC  
D
75  
Green (RoHS  
& no Sb/Br)  
TLV272IDGK  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
SOIC  
DGK  
DGK  
DGK  
DGK  
D
80  
Green (RoHS  
& no Sb/Br)  
TLV272IDGKG4  
TLV272IDGKR  
TLV272IDGKRG4  
TLV272IDR  
80  
Green (RoHS  
& no Sb/Br)  
2500  
2500  
2500  
2500  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
TLV272IDRG4  
SOIC  
D
Green (RoHS  
& no Sb/Br)  
TLV272IP  
TLV272IPE4  
TLV274CD  
ACTIVE  
ACTIVE  
ACTIVE  
PDIP  
PDIP  
SOIC  
P
P
D
8
8
50  
50  
50  
Pb-Free (RoHS)  
Pb-Free (RoHS)  
CU NIPDAU N / A for Pkg Type  
CU NIPDAU N / A for Pkg Type  
CU NIPDAU Level-1-260C-UNLIM  
14  
Green (RoHS  
& no Sb/Br)  
TLV274CDG4  
TLV274CDR  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
D
D
14  
14  
50  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
2500  
Green (RoHS  
& no Sb/Br)  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
16-Aug-2012  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
TLV274CDRG4  
TLV274CPW  
TLV274CPWG4  
TLV274CPWR  
TLV274CPWRG4  
TLV274ID  
SOIC  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
SOIC  
D
PW  
PW  
PW  
PW  
D
14  
14  
14  
14  
14  
14  
14  
14  
14  
2500  
90  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
90  
Green (RoHS  
& no Sb/Br)  
2000  
2000  
50  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
TLV274IDG4  
TLV274IDR  
SOIC  
D
50  
Green (RoHS  
& no Sb/Br)  
SOIC  
D
2500  
2500  
Green (RoHS  
& no Sb/Br)  
TLV274IDRG4  
SOIC  
D
Green (RoHS  
& no Sb/Br)  
TLV274IN  
TLV274INE4  
TLV274IPW  
ACTIVE  
ACTIVE  
ACTIVE  
PDIP  
PDIP  
N
N
14  
14  
14  
25  
25  
90  
Pb-Free (RoHS)  
Pb-Free (RoHS)  
CU NIPDAU N / A for Pkg Type  
CU NIPDAU N / A for Pkg Type  
CU NIPDAU Level-1-260C-UNLIM  
TSSOP  
PW  
Green (RoHS  
& no Sb/Br)  
TLV274IPWG4  
TLV274IPWR  
ACTIVE  
ACTIVE  
ACTIVE  
TSSOP  
TSSOP  
TSSOP  
PW  
PW  
PW  
14  
14  
14  
90  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
2000  
2000  
Green (RoHS  
& no Sb/Br)  
TLV274IPWRG4  
Green (RoHS  
& no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
Addendum-Page 3  
PACKAGE OPTION ADDENDUM  
www.ti.com  
16-Aug-2012  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF TLV271, TLV272, TLV274 :  
Automotive: TLV271-Q1, TLV272-Q1, TLV274-Q1  
NOTE: Qualified Version Definitions:  
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects  
Addendum-Page 4  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
16-Aug-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TLV271CDBVR  
TLV271CDBVT  
TLV271CDR  
SOT-23  
SOT-23  
SOIC  
DBV  
DBV  
D
5
5
3000  
250  
178.0  
178.0  
330.0  
178.0  
178.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
9.0  
9.0  
3.23  
3.23  
6.4  
3.17  
3.17  
5.2  
1.37  
1.37  
2.1  
4.0  
4.0  
8.0  
4.0  
4.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
Q3  
Q3  
Q1  
Q3  
Q3  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
8
2500  
3000  
250  
12.4  
9.0  
12.0  
8.0  
TLV271IDBVR  
TLV271IDBVT  
TLV272CDGKR  
TLV272CDGKR  
TLV272CDR  
SOT-23  
SOT-23  
VSSOP  
VSSOP  
SOIC  
DBV  
DBV  
DGK  
DGK  
D
5
3.23  
3.23  
5.3  
3.17  
3.17  
3.4  
1.37  
1.37  
1.4  
5
9.0  
8.0  
8
2500  
2500  
2500  
2500  
2500  
2500  
2500  
2000  
2500  
2000  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
16.4  
12.4  
16.4  
12.4  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
16.0  
12.0  
16.0  
12.0  
8
5.3  
3.4  
1.4  
8
6.4  
5.2  
2.1  
TLV272IDGKR  
TLV272IDGKR  
TLV272IDR  
VSSOP  
VSSOP  
SOIC  
DGK  
DGK  
D
8
5.3  
3.4  
1.4  
8
5.3  
3.4  
1.4  
8
6.4  
5.2  
2.1  
TLV274CDR  
SOIC  
D
14  
14  
14  
14  
6.5  
9.0  
2.1  
TLV274CPWR  
TLV274IDR  
TSSOP  
SOIC  
PW  
D
6.9  
5.6  
1.6  
6.5  
9.0  
2.1  
TLV274IPWR  
TSSOP  
PW  
6.9  
5.6  
1.6  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
16-Aug-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TLV271CDBVR  
TLV271CDBVT  
TLV271CDR  
SOT-23  
SOT-23  
SOIC  
DBV  
DBV  
D
5
5
3000  
250  
180.0  
180.0  
340.5  
180.0  
180.0  
358.0  
364.0  
340.5  
364.0  
358.0  
340.5  
333.2  
367.0  
333.2  
367.0  
180.0  
180.0  
338.1  
180.0  
180.0  
335.0  
364.0  
338.1  
364.0  
335.0  
338.1  
345.9  
367.0  
345.9  
367.0  
18.0  
18.0  
20.6  
18.0  
18.0  
35.0  
27.0  
20.6  
27.0  
35.0  
20.6  
28.6  
35.0  
28.6  
35.0  
8
2500  
3000  
250  
TLV271IDBVR  
TLV271IDBVT  
TLV272CDGKR  
TLV272CDGKR  
TLV272CDR  
SOT-23  
SOT-23  
VSSOP  
VSSOP  
SOIC  
DBV  
DBV  
DGK  
DGK  
D
5
5
8
2500  
2500  
2500  
2500  
2500  
2500  
2500  
2000  
2500  
2000  
8
8
TLV272IDGKR  
TLV272IDGKR  
TLV272IDR  
VSSOP  
VSSOP  
SOIC  
DGK  
DGK  
D
8
8
8
TLV274CDR  
SOIC  
D
14  
14  
14  
14  
TLV274CPWR  
TLV274IDR  
TSSOP  
SOIC  
PW  
D
TLV274IPWR  
TSSOP  
PW  
Pack Materials-Page 2  
IMPORTANT NOTICE  
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