TLV4110IDGNR全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

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产品型号TLV4110IDGNR的概述

TLV4110IDGNR芯片概述 TLV4110IDGNR是一款高性能、低功耗的运算放大器，采用TI（德州仪器）公司生产。该芯片具有宽电源电压范围和较高的增益带宽积，适合用于各种精密测量和信号处理应用。其低失调电压和低噪声特性使其非常适合用于音频、医疗和工业设备等需要高精度的场合。 TLV4110IDGNR详细参数 TLV4110IDGNR芯片的主要参数包括： - 电源电压范围：3V至30V - 工作温度范围：-40℃至85℃ - 增益带宽积：2.5 MHz - 失调电压：最大达100 μV - 输入共模电压范围：-0.1V至(V+) - 1.5V - 输入偏置电流：最大达10 nA - 输出短路电流：可达100 mA - 电流消耗：每个放大器大约为1.5 mA - 封装类型：VSSOP-8（8引脚小型封装）厂家、包装、封装 TLV4110IDGNR芯片的生产厂家为德州仪器（Tex...

产品型号TLV4110IDGNR的Datasheet PDF文件预览

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SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006

Operational Amplifier

High Output Drive . . . >300 mA

Rail-To-Rail Output

−

Unity-Gain Bandwidth . . . 2.7 MHz

Slew Rate . . . 1.5 V/µs

Supply Current . . . 700 µA/Per Channel

Supply Voltage Range . . . 2.5 V to 6 V

Specified Temperature Range:

TLV4112

D, DGN, OR P PACKAGE

(TOP VIEW)

− T = 0°C to 70°C . . . Commercial Grade

1OUT

1IN−

1IN+

GND

− T = −40°C to 125°C . . . Industrial Grade

2OUT

2IN−

2IN+

Universal OpAmp EVM

description

The TLV411x single supply operational amplifiers provide output currents in excess of 300 mA at 5 V. This

enables standard pin-out amplifiers to be used as high current buffers or in coil driver applications. The TLV4110

and TLV4113 come with a shutdown feature.

The TLV411x is available in the ultra small MSOP PowerPAD package, which offers the exceptional thermal

impedance required for amplifiers delivering high current levels.

All TLV411x devices are offered in PDIP, SOIC (single and dual) and MSOP PowerPAD (dual).

FAMILY PACKAGE TABLE

PACKAGE TYPES

NUMBER OF

CHANNELS

UNIVERSAL

EVM BOARD

DEVICE

TLV4110

SHUTDOWN

MSOP

PDIP

SOIC

Yes

—

Refer to the EVM

Selection Guide

(Lit# SLOU060)

TLV4111

TLV4112

TLV4113

—

Yes

HIGH-LEVEL OUTPUT VOLTAGE

LOW-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT CURRENT

3.0

2.9

1.0

0.9

0.8

= 3 V

= 70°C

2.8

2.7

2.6

2.5

= 25°C

= 0°C

0.7

0.6

= 125°C

= −40°C

0.5

0.4

0.3

= 0°C

= 125°C

2.4

2.3

= 25°C

= 70°C

2.2

0.2

0.1

0.0

2.1

2.0

100

150

200

250

300

100

150

200

250

300

− High-Level Output Current − mA

− Low-Level Output Current − mA

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006

TLV4110 AND TLV4111 AVAILABLE OPTIONS

PACKAGED DEVICES

MSOP

SMALL OUTLINE

PLASTIC DIP

(P)

SMALL OUTLINE

†‡

(D)

SYMBOL

†

(DGN)

TLV4110CD

TLV4111CD

TLV4110ID

TLV4111ID

TLV4110CDGN

TLV4111CDGN

TLV4110IDGN

TLV4111IDGN

xxTIAHL

xxTIAHN

xxTIAHM

xxTIAHO

TLV4110CP

TLV4111CP

TLV4110IP

TLV4111IP

0°C to 70°C

−40°C to 125°C

†

‡

This package is available taped and reeled. To order this packaging option, add an R suffix to the part

number (e.g., TLV4110CDR).

In the SOIC package, the maximum RMS output power is thermally limited to 350 mW; 700 mW peaks

can be driven, as long as the RMS value is less than 350 mW.

TLV4112 AND TLV4113 AVAILABLE OPTIONS

PACKAGED DEVICES

MSOP

PLASTIC DIP

(P)

SMALL OUTLINE

†‡

(D)

SYMBOL

†

(DGN)

(DGQ)

TLV4112CD

TLV4113CD

TLV4112ID

TLV4113ID

TLV4112DGN

xxTIAHP

—

TLV4112CP

TLV4113CN

TLV4112IP

TLV4113IN

0°C to 70°C

—

TLV4112IDGN

—

TLV4113CDGQ

—

xxTIAHR

—

xxTIAHQ

—

−40°C to 125°C

TLV4113IDGQ

xxTIAHS

†

‡

This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV4112CDR).

In the SOIC package, the maximum RMS output power is thermally limited to 350 mW; 700 mW peaks can be driven, as long as the RMS value

is less than 350 mW.

TLV411x PACKAGE PIN OUTS

TLV4110

D, DGN OR P PACKAGE

(TOP VIEW)

TLV4111

D, DGN OR P PACKAGE

(TOP VIEW)

TLV4112

D, DGN, OR P PACKAGE

(TOP VIEW)

IN−

SHDN

IN−

1OUT

1IN−

1IN+

GND

2OUT

2IN−

2IN+

IN+

OUT

IN+

OUT

GND

TLV4113

D OR N PACKAGE

TLV4113

DGQ PACKAGE

(TOP VIEW)

1OUT

1IN−

1IN+

GND

1SHDN

1OUT

1IN−

1IN+

GND

2OUT

2IN−

2IN+

2OUT

2IN−

2IN+

2SHDN

1SHDN

2SHDN

NC − No internal connection

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢄꢄꢄ ꢆ ꢀ ꢁꢂꢃ ꢄꢄ ꢇꢆ ꢀꢁꢂ ꢃꢄꢄꢈ

ꢉꢊꢋ ꢌꢁꢍ ꢎ ꢉ ꢏꢌ ꢐꢏ ꢎ ꢑꢀ ꢒꢑꢀ ꢓꢔꢌ ꢂꢕ ꢎ ꢒꢕꢔꢊꢀꢌ ꢎ ꢖ ꢊꢁ

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SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

Differential input voltage, V

Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mA

Continuous /RMS output current, I (each output of amplifier): T ≤ 105°C . . . . . . . . . . . . . . . . . . . . 350 mA

T ≤ 150°C . . . . . . . . . . . . . . . . . . . . 110 mA

Peak output current, I (each output of amplifier: T ≤ 105°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA

T ≤ 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 mA

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating free-air temperature range, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C

Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential voltages, are with respect to GND.

2. To prevent permanent damage the die temperature must not exceed the maximum junction temperature.

DISSIPATION RATING TABLE

≤ 25°C

T = 125°C

POWER RATING

PACKAGE

(°C/W)

POWER RATING

D (8)

38.3

176

710 mW

142 mW

D (14)

26.9

122.3

1022 mW

204.4 mW

‡

DGN (8)

4.7

52.7

52.3

104

2.37 W

2.39 W

474.4 mW

478 mW

‡

DGQ (10)

P (8)

1200 mW

1600 mW

240.4 mW

320.5 mW

N (14)

‡

See The Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report (literature number

SLMA002), for more information on the PowerPAD package. The thermal data was measured on a PCB layout based

on the information in the section entitled Texas Instruments Recommended Board for PowerPAD on page 33 of the before

mentioned document.

recommended operating conditions

MIN

2.5

MAX

UNIT

Supply voltage, V

Common-mode input voltage range, V

ICR

−1.5

C-suffix

I-suffix

Operating free-air temperature, T

°C

−40

2.1

3.8

125

= 3 V

= 5 V

= 3 V

= 5 V

V(on)

V(off)

Shutdown turn-on/off voltage level

0.9

1.65

Relative to GND

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006

electrical characteristics at recommend operating conditions, V

noted)

= 3 V and 5 V (unless otherwise

dc performance

†

PARAMETER

Input offset voltage

Offset voltage draft

TEST CONDITIONS

MIN

TYP

MAX UNITS

25°C

175

3500

µV

= V /2,

= 100 Ω,

= V /2 ,

= 50 Ω

O DD

Full range

4000

αVIO

25°C

µV/°C

= 3 V,

= 50 Ω

= 0 to 2 V,

= 0 to 4 V,

25°C

CMRR Common-mode rejection ratio

= 5 V,

= 50 Ω

25°C

Full range

25°C

R =100 Ω

= 3 V,

=0 to 1V

O(PP)

100

R =10 kΩ

Full range

25°C

Large-signal differential voltage

amplification

R =100 Ω

Full range

25°C

= 5 V,

=0 to 3V

O(PP)

110

R =10 kΩ

Full range

†

Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.

input characteristics

†

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

25°C

0.3

TLV411xC

Input offset current

= V /2

Full range

TLV411xI

250

25°C

0.3

= V /2,

= 50 Ω

TLV411xC

TLV411xI

100

500

GΩ

Input bias current

Full range

Differential input resistance

25°C

1000

i(d)

Common-mode input capacitance

f = 100 Hz

†

Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢄꢄꢄ ꢆ ꢀ ꢁꢂꢃ ꢄꢄ ꢇꢆ ꢀꢁꢂ ꢃꢄꢄꢈ

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SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006

electrical characteristics at specified free-air temperature, V

noted) (continued)

= 3 V and 5 V (unless otherwise

output characteristics

†

PARAMETER

TEST CONDITIONS

MIN

2.7

2.6

4.7

4.6

4.45

TYP

MAX UNITS

25°C

Full range

25°C

2.97

= −10 mA

= 3 V,

= V /2

2.73

4.96

4.76

4.6

=−100 mA

= −10 mA

= −100 mA

Full range

25°C

High-level output voltage

Full range

25°C

= 5 V,

= V /2

Full range

25°C

= −200 mA

−40°C to

85°C

4.35

25°C

Full range

25°C

0.03

0.33

0.38

0.1

0.4

= 10 mA

= 3 V and 5 V,

= V /2

= 100 mA

Low-level output voltage

Full range

25°C

0.55

0.6

= 5 V,

= V /2

= 200 mA

−40°C to

85°C

0.7

= 3 V

= 5 V

220

320

800

‡

Output current

Measured at 0.5 V from rail

25°C

Sourcing

Sinking

‡

Short-circuit output current

25°C

†

‡

Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.

When driving output currents in excess of 200 mA, the MSOP PowerPAD package is required for thermal dissipation.

power supply

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

25°C

Full range

25°C

700

1000

Supply current (per channel)

= V /2

µA

1500

=2.7 to 3.3 V, No load,

= V /2 V

Full range

25°C

PSRR Power supply rejection ratio (∆V

/ ∆V

)

=4.5 to 5.5 V, No load,

= V /2 V

Full range

†

Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006

electrical characteristics at specified free-air temperature, V

noted) (continued)

= 3 V and 5 V (unless otherwise

dynamic performance

†

PARAMETER

TEST CONDITIONS

R =100 Ω

MIN

TYP

2.7

MAX UNITS

GBWP Gain bandwidth product

C =10 pF

25°C

MHz

0.8

0.55

1.57

= 3 V

= 5 V

= 2 V,

= 100 Ω,

o( )

Full range

25°C

Slew rate at unity gain

V/µs

1.57

= 10 pF

Full range

0.7

φM

Phase margin

Gain margin

= 100 Ω,

= 10 pF

25°C

= 1 V,

(STEP)pp

0.1%

0.7

1.3

= −1,

= 10 pF,

= 100 Ω

Settling time

µs

0.01%

†

Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.

noise/distortion performance

PARAMETER

TEST CONDITIONS

MIN

TYP

0.025

0.035

0.15

MAX UNITS

= 1

= V /2 V,

) DD

= 10

= 100

= 100 Ω,

THD+N Total harmonic distortion plus noise

f = 100 Hz

25°C

f = 100 Hz

f = 10 kHz

f = 1 kHz

nV/√Hz

fA/√Hz

Equivalent input noise voltage

Equivalent input noise current

0.31

shutdown characteristics

†

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

25°C

3.4

Supply current in shutdown mode (per channel)

(TLV4110, TLV4113)

SHDN = 0 V

µA

DD(SHDN)

Full range

‡

Amplifier turn-on time

Amplifier turn-off time

(ON)

= 100 Ω

25°C

µs

‡

3.3

(Off)

†

‡

Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.

Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current

has reached half its final value.

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SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

1, 2

Input offset voltage

vs Common-mode input voltage

CMRR

Common-mode rejection ratio

High-level output voltage

Low-level output voltage

Output impedance

vs Frequency

vs High-level output current

vs Low-level output current

vs Frequency

4, 6

5, 7

Supply current

vs Supply voltage

vs Frequency

Power supply voltage rejection ratio

Differential voltage amplification and phase

Gain-bandwidth product

SVR

vs Frequency

vs Supply voltage

vs Temperature

vs Frequency

Slew rate

Total harmonic distortion+noise

Equivalent input voltage noise

Phase margin

vs Frequency

vs Capacitive load

Voltage-follower signal pulse response

Inverting large-signal pulse response

Small-signal inverting pulse response

Crosstalk

18, 19

20, 21

vs Frequency

Shutdown forward and reverse isolation

Shutdown supply current

vs Free-air temperature

Shutdown supply current/output voltage

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SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006

TYPICAL CHARACTERISTICS

INPUT OFFSET VOLTAGE

COMMON-MODE REJECTION RATIO

INPUT OFFSET VOLTAGE

COMMON-MODE INPUT VOLTAGE

FREQUENCY

COMMON-MODE INPUT VOLTAGE

6000

120

6000

= 5 V

= 25°C

= 3 V

= 25°C

= 3 V

110

100

= 25°C

4000

2000

4000

2000

−2000

−4000

−6000

−4000

−6000

−0.2

0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2

−0.2

0.4 0.8 1.2 1.6

2.4 2.8 3.2

100

1 k

10 k

100 k

1 M

10 M

− Common-Mode Input Voltage − V

ICR

f − Frequency − Hz

Figure 1

Figure 2

Figure 3

HIGH-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

LOW-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT CURRENT

3.0

2.9

1.0

0.9

0.8

5.0

= 3 V

= 5 V

4.9

4.8

4.7

4.6

4.5

= 70°C

2.8

2.7

2.6

2.5

= 25°C

= 0°C

0.7

0.6

= 125°C

= −40°C

0.5

0.4

0.3

= 0°C

= 125°C

= 0°C

2.4

2.3

= 25°C

= 70°C

4.4

4.3

= 25°C

= 70°C

2.2

0.2

0.1

0.0

4.2

4.1

4.0

2.1

2.0

100

150

200

250

300

100

150

200

250

300

100

150

200

250

300

− High-Level Output Current − mA

− Low-Level Output Current − mA

− High-Level Output Current − mA

Figure 4

Figure 5

Figure 6

LOW-LEVEL OUTPUT VOLTAGE

LOW-LEVEL OUTPUT CURRENT

OUTPUT IMPEDANCE

SUPPLY CURRENT

SUPPLY VOLTAGE

FREQUENCY

1.0

0.9

100

1200

= 5 V

= 3 & 5 V

= 25°C

= 1

= 125°C

= V /2 V

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

1000

800

= 70°C

= 25°C

= 70°C

= 25°C

= 0°C

600

= −40°C

A = 100

A = 10

= 125°C

400

200

A = 1

0.0

0.10

100

150

200

250

300

100

10k

100k

10M

− Low-Level Output Current − mA

f − Frequency − Hz

− Supply Voltage − V

Figure 7

Figure 8

Figure 9

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SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006

TYPICAL CHARACTERISTICS

DIFFERENTIAL VOLTAGE

POWER SUPPLY REJECTION RATIO

AMPLIFICATION AND PHASE

FREQUENCY

100

120

135

= 3 & 5 V

= 1 kΩ

100

R = 100 Ω

PHASE

= 0 V

= 25°C

GAIN

= 3 & 5 V

= 100 kΩ

= 10 pF

−20

−40

= 25°C

−45

100

1 k

10 k

100 k

1 M

10 M

100

1 k

10 k

100 k

1 M

10 M

f − Frequency − Hz

Figure 10

Figure 11

SLEW RATE

TEMPERATURE

GAIN-BANDWIDTH PRODUCT

SLEW RATE

SUPPLY VOLTAGE

4.0

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

= 1

= 100 Ω

= 10 pF

= 3 & 5 V

= 1

= 100 Ω

= 10 pF

3.5

3.0

2.5

SR+

SR−

2.0

1.5

= 25°C

= 100 Ω

= 10 pF

1.0

0.5

0.0

f = 1 kHz

=open loop

2.5

3.5

4.5

5.5

2.5

3.5

4.5

5.5

−40−25−10

20 35 50 65 80 95 110 125

− Supply Voltage − V

− Temperature − °C

Figure 13

Figure 14

Figure 12

EQUIVALENT INPUT VOLTAGE NOISE

PHASE MARGIN

CAPACITIVE LOAD

TOTAL HARMONIC DISTORTION+NOISE

FREQUENCY

100

160

140

= 3 & 5 V

= 100

= 5 V

= 100 Ω

= V /2

O(PP)

= 1, 10, & 100

= 25°C

= 5 V

120

100

= 3 V

= 600

= 20

NULL

A = 100

= 20

NULL

0.1

= 0

NULL

A = 10

A = 1

= 0

NULL

0.01

100

1 k

10 k

100 k

100

1 k

10 k

100 k

100

1 k

10 k

100 k

Capacitive Load − pF

f − Frequency − Hz

Figure 15

Figure 16

Figure 17

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SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006

TYPICAL CHARACTERISTICS

INVERTING LARGE-SIGNAL

PULSE RESPONSE

VOLTAGE-FOLLOWER

LARGE-SIGNAL PULSE RESPONSE

VOLTAGE-FOLLOWER

SMALL-SIGNAL PULSE RESPONSE

2.6

2.55

2.5

= 5 V

= −1

= 1

= 100 Ω

= 10 pF

= 25°C

= 100 Ω

= 50 pF

= 25°C

= 2.5 V

−1

−2

2.45

2.55

2.5

= 100 mV

= 5 V

= 1

= 100 Ω

= 10 pF

= 25°C

2.45

2.4

−1

−2

10 12 14

−0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

t − TIME − µs

Figure 19

Figure 20

Figure 18

CROSSTALK

FREQUENCY

INVERTING LARGE-SIGNAL

PULSE RESPONSE

SMALL-SIGNAL INVERTING

PULSE RESPONSE

2.58

= 3 & 5 V

= 100 Ω

2.54

2.5

−20

= 5 V

= −1

All Channels

= 100 Ω

= 50 pF

= 25°C

= 2.5 V

= 5 V

= −1

= 100 Ω

= 50 pF

= 25°C

= 2.5 V

−1

−2

−40

−60

2.46

2.42

2.54

2.5

= 4 V

−80

−100

−120

2.46

2.42

= 2 V

−1

0 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0

100

1 k

10 k

100 k

t − TIME − µs

f − Frequency − Hz

Figure 21

Figure 22

Figure 23

SHUTDOWN SUPPLY CURRENT

SHUTDOWN FORWARD AND

REVERSE ISOLATION

FREE-AIR TEMPERATURE

−20

−40

−60

= 3 and 5 V,

= 100 Ω,

= 50 pF,

= 1.

= 3 and 5 V

= V /2,

No Load

= 25°C

−80

−100

−120

= 0.1 V

= 2.5 V

1 k

−140

−160

100

10 k 100 k

1 M 10 M

−40 −25 −10 5 20 35 50 65 80 95 110 125

f − Frequency − Hz

− Free-Air Temperature − °C

Figure 24

Figure 25

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SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006

TYPICAL CHARACTERISTICS

SHUTDOWN SUPPLY CURRENT / OUTPUT VOLTAGE

= 3 V

= 1

1.5

= 100 Ω

= 10 pF

= V /2

= 25° C

0.5

DD(SD)

100

120

t − Time − µs

Figure 26

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SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006

APPLICATION INFORMATION

shutdown function

Two members of the TLV411x family (TLV4110/3) have a shutdown terminal for conserving battery life in

portable applications. When the shutdown terminal is tied low, the supply current is reduced to just nano amps

per channel, the amplifier is disabled, and the outputs are placed in a high impedance mode. In order to save

power in shutdown mode, an external pullup resistor is required, therefore, to enable the amplifier the shutdown

terminal must be pulled high. When the shutdown terminal is left floating, care should be taken to ensure that

parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into

shutdown.

driving a capacitive load

When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the

device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater

than 1 nF, it is recommended that a resistor be placed in series (R

) with the output of the amplifier, as shown

NULL

in Figure 27. A maximum value of 20 Ω should work well for most applications.

NULL

−

Input

Output

LOAD

Output

Snubber

(a)

(b)

Figure 27. Driving a Capacitive Load

offset voltage

The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times

the corresponding gains. The following schematic and formula can be used to calculate the output offset

voltage:

IB−

−

IB+

+ V

1 ) ǒ Ǔ " I

ǒ Ǔ ǒ Ǔ

IB)

IB–

Figure 28. Output Offset Voltage Model

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SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006

APPLICATION INFORMATION

null

Figure 29

general power design considerations

When driving heavy loads at high junction temperatures there is an increased probability of electromigration

affecting the long term reliability of ICs. Therefore for this not to be an issue either:

The output current must be limited (at these high junction temperatures).

The junction temperature must be limited.

The maximum continuous output current at a die temperature 150°C will be 1/3 of the current at 105°C.

The junction temperature will be dependent on the ambient temperature around the IC, thermal impedance from

the die to the ambient and power dissipated within the IC.

T = T + θ × P

DIS

Where:

is the IC power dissipation and is equal to the output current multiplied by the voltage dropped across the

DIS

output of the IC.

is the thermal impedance between the junction and the ambient temperature of the IC.

T is the junction temperature.

T is the ambient temperature.

Reducing one or more of these factors results in a reduced die temperature. The 8-pin SOIC (small outline

integrated circuit) has a thermal impedance from junction to ambient of 176°C/W. For this reason it is

recommended that the maximum power dissipation of the 8-pin SOIC package be limited to 350 mW, with peak

dissipation of 700 mW as long as the RMS value is less than 350 mW.

The use of the MSOP PowerPAD dramatically reduces the thermal impedance from junction to case. And with

correct mounting, the reduced thermal impedance greatly increases the IC’s permissible power dissipation and

output current handling capability. For example, the power dissipation of the PowerPAD is increased to above

1 W. Sinusoidal and pulse-width modulated output signals also increase the output current capability. The

equivalent dc current is proportional to the square-root of the duty cycle:

( )

duty cycle

+ I

DC(EQ)

Cont

CURRENT DUTY CYCLE

AT PEAK RATED CURRENT

EQUIVALENT DC CURRENT

AS A PERCENTAGE OF PEAK

100

Note that with an operational amplifier, a duty cycle of 70% would often result in the op amp sourcing current

70% of the time and sinking current 30%, therefore, the equivalent dc current would still be 0.84 times the

continuous current rating at a particular junction temperature.

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SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006

APPLICATION INFORMATION

general PowerPAD design considerations

The TLV411x is available in a thermally-enhanced PowerPAD family of packages. These packages are

constructed using a downset leadframe upon which the die is mounted [see Figure 30(a) and Figure 30(b)]. This

arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see

Figure 30(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance

can be achieved by providing a good thermal path away from the thermal pad.

The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.

During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be

soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,

heat can be conducted away from the package into either a ground plane or other heat dissipating device.

Soldering the PowerPAD to the PCB is always recommended, even with applications that have low-power

dissipation. This provides the necessary thermal and mechanical connection between the lead frame die pad

and the PCB.

The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of

surface mount with mechanical methods of heatsinking.

DIE

Side View (a)

Thermal

Pad

DIE

End View (b)

Bottom View (c)

NOTE A: The thermal pad is electrically isolated from all terminals in the package.

Figure 30. Views of Thermally-Enhanced DGN Package

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SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006

APPLICATION INFORMATION

Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the

recommended approach.

general PowerPAD design considerations (continued)

1. The thermal pad must be connected to the most negative supply voltage on the device, GND.

2. Prepare the PCB with a top side etch pattern as illustrated in the thermal land pattern mechanical drawings

at the end of this document. There should be etch for the leads as well as etch for the thermal pad.

3. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small

so that solder wicking through the holes is not a problem during reflow.

4. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps

dissipate the heat generated by the TLV411x IC. These additional vias may be larger than the 13-mil

diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad

area to be soldered so that wicking is not a problem.

5. Connect all holes to the internal ground plane that is at the same voltage potential as the device GND pin.

6. When connecting these holes to the ground plane, do not use the typical web or spoke via connection

methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat

transfer during soldering operations. This makes the soldering of vias that have plane connections easier.

In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore,

the holes under the TLV411x PowerPAD package should make their connection to the internal ground plane

with a complete connection around the entire circumference of the plated-through hole.

7. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five

holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This

prevents solder from being pulled away from the thermal pad area during the reflow process.

8. Apply solder paste to the exposed thermal pad area and all of the IC terminals.

9. With these preparatory steps in place, the TLV411x IC is simply placed in position and run through the solder

reflow operation as any standard surface-mount component. This results in a part that is properly installed.

For a given θ , the maximum power dissipation is shown in Figure 31 and is calculated by the following formula:

–T

MAX

ǒ Ǔ

Where:

= Maximum power dissipation of TLV411x IC (watts)

= Absolute maximum junction temperature (150°C)

= Free-ambient air temperature (°C)

MAX

= θ + θ

JC CA

= Thermal coefficient from junction to case

= Thermal coefficient from case to ambient air (°C/W)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢄꢄ

ꢅ

ꢆ

ꢀ

ꢁꢂ

ꢃ

ꢄ

ꢆ

ꢀꢁꢂ

ꢃ

ꢄꢄ

ꢇ

ꢆ

ꢀ

ꢁꢂ

ꢃ

ꢄꢄ

ꢈ

ꢉ

ꢊ

ꢋ

ꢒ

ꢌ

ꢁ

ꢌ

ꢍ

ꢉ

ꢎ

ꢉ

ꢔ

ꢏ

ꢗ

ꢌ

ꢘ

ꢐ

ꢌ

ꢏ

ꢀ

ꢎ

ꢏ

ꢑ

ꢗ

ꢀ

ꢏ

ꢒ

ꢑ

ꢀ

ꢓ

ꢔ

ꢌ

ꢖ

ꢂ

ꢕ

ꢎ

ꢒ

ꢕ

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SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006

APPLICATION INFORMATION

general PowerPAD design considerations (continued)

MAXIMUM POWER DISSIPATION

FREE-AIR TEMPERATURE

= 150°C

3.5

DGN Package

Low-K Test PCB

= 52.7°C/W

2.5

PDIP Package

Low-K Test PCB

= 104°C/W

SOIC Package

Low-K Test PCB

= 176°C/W

1.0

0.5

−55 −40 −25 −10

20 35 50 65 80 95 110 125

− Free-Air Temperature − °C

NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.

Figure 31. Maximum Power Dissipation vs Free-Air Temperature

The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent

power and output power. The designer should never forget about the quiescent heat generated within the

device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most

of the heat dissipation is at low output voltages with high output currents.

The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The

PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a

copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other

hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around

the device, θ decreases and the heat dissipation capability increases. The currents and voltages shown in

these graphs are for the total package. For the dual amplifier packages, the sum of the RMS output currents

and voltages should be used to choose the proper package.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢄꢄꢄ ꢆ ꢀ ꢁꢂꢃ ꢄꢄ ꢇꢆ ꢀꢁꢂ ꢃꢄꢄꢈ

ꢉꢊꢋ ꢌꢁꢍ ꢎ ꢉ ꢏꢌ ꢐꢏ ꢎ ꢑꢀ ꢒꢑꢀ ꢓꢔꢌ ꢂꢕ ꢎ ꢒꢕꢔꢊꢀꢌ ꢎ ꢖ ꢊꢁ

ꢊꢋ ꢒꢁ ꢌꢉ ꢌꢕ ꢔꢗ ꢘ ꢌꢀ ꢏ ꢗꢏꢑ ꢀꢓ ꢎ ꢘꢖ

SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006

APPLICATION INFORMATION

macromodel information

Macromodel information provided was derived using Microsim Parts, the model generation software used

with Microsim PSpice. The Boyle macromodel (see Note 3) and subcircuit in Figure 33 are generated using

the TLV411x typical electrical and operating characteristics at T = 25°C. Using this information, output

simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):

Maximum positive output voltage swing

Maximum negative output voltage swing

Slew rate

Unity-gain frequency

Common-mode rejection ratio

Phase margin

Quiescent power dissipation

Input bias current

DC output resistance

AC output resistance

Short-circuit output current limit

Open-loop voltage amplification

NOTE 3: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal

of Solid-State Circuits, SC-9, 353 (1974).

−

egnd

rd1

rd2

rss

ro2

css

vlim

−

IN+

IN−

−

ro1

gcm

ioff

OUT

dlp

dln

−

iss

vlp

hlim

vln

−

GND

+ 54

* TLV4112_5V operational amplifier ”macromodel” subcircuit

iss

13.800E−6

75E−9

* updated using Model Editor release 9.1 on 01/18/00 at 15:50

hlim

ioff

vlim 1K

Model Editor is an OrCAD product.

10 jx1

10 jx2

* connections: non−inverting input

rd1

rd2

ro1

ro2

rss

vlim

vlp

vln

.model

| inverting input

| | positive power supply

| | | negative power supply

| | | | output

| | | | |

1 2 3 4 5

100.00E3

5.9386E3

.subckt TLV4112_5V

3.3333E3

14.493E6

dc 0

2.2439E−12

10.000E−12

dc .86795

dc 0

dc 300

css

dlp

dln

egnd

454.55E−15

D(Is=800.00E−18)

.model dy

.model jx1

.model jx2

.ends

D(Is=800.00E−18 Rs=1m Cjo=10p)

poly(2) (3,0) (4,0) 0 .5 .5

poly(5) vb vc ve vlp vln 0

NJF(Is=150.00E−12 Beta=2.0547E−3 +Vto=−1)

NJF(Is=150.00E−12 Beta=2.0547E−3 + Vto=−1)

+ 33.395E6 −1E3 1E3 33E6 −33E6

gcm

12 168.39E−6

99 168.39E−12

Figure 32. Boyle Macromodel and Subcircuit

PSpice and Parts are trademarks of MicroSim Corporation.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

PACKAGING INFORMATION

Orderable Device

TLV4110ID

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

-40 to 125 4110I

-40 to 125 AHM

-40 to 125 4110I

-40 to 125 TLV4110I

TLV4110IDG4

TLV4110IDGNR

TLV4110IDGNRG4

TLV4110IDR

ACTIVE

DGN

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

2500

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

SOIC

PDIP

SOIC

Green (RoHS

& no Sb/Br)

TLV4110IDRG4

TLV4110IP

Green (RoHS

& no Sb/Br)

Pb-Free

(RoHS)

TLV4110IPE4

TLV4111CD

Pb-Free

(RoHS)

N / A for Pkg Type

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

0 to 70

4111C

AHN

TLV4111CDG4

TLV4111CDGN

TLV4111CDGNG4

TLV4111ID

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

DGN

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

AHN

SOIC

Green (RoHS

& no Sb/Br)

-40 to 125 4111I

-40 to 125 AHO

TLV4111IDG4

TLV4111IDGN

TLV4111IDGNG4

TLV4111IDGNR

SOIC

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

DGN

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

MSOP-

2500

Green (RoHS

& no Sb/Br)

PowerPAD

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

Orderable Device

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

TLV4111IDGNRG4

TLV4111IDR

ACTIVE

MSOP-

PowerPAD

DGN

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

-40 to 125 AHO

-40 to 125 4111I

SOIC

Green (RoHS

& no Sb/Br)

TLV4111IDRG4

TLV4112CD

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

0 to 70

4112C

TLV4112CDG4

TLV4112CDGN

TLV4112CDGNG4

TLV4112CP

Green (RoHS

& no Sb/Br)

4112C

MSOP-

PowerPAD

DGN

Green (RoHS

& no Sb/Br)

AHP

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

AHP

PDIP

SOIC

Pb-Free

(RoHS)

TLV4112C

TLV4112CPE4

TLV4112ID

Pb-Free

(RoHS)

N / A for Pkg Type

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

N / A for Pkg Type

-40 to 125 4112I

-40 to 125 AHQ

-40 to 125 4112I

-40 to 125 TLV4112I

TLV4112IDG4

TLV4112IDGN

TLV4112IDGNG4

TLV4112IDGNR

TLV4112IDGNRG4

TLV4112IDR

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

DGN

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

2500

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

SOIC

PDIP

Green (RoHS

& no Sb/Br)

TLV4112IDRG4

TLV4112IP

Green (RoHS

& no Sb/Br)

Pb-Free

(RoHS)

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

Orderable Device

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

TLV4112IPE4

TLV4113CDGQ

TLV4113CDGQG4

TLV4113CDGQR

TLV4113CDGQRG4

TLV4113ID

ACTIVE

PDIP

Pb-Free

(RoHS)

CU NIPDAU

N / A for Pkg Type

Level-1-260C-UNLIM

N / A for Pkg Type

-40 to 125 TLV4112I

MSOP-

PowerPAD

DGQ

Green (RoHS

& no Sb/Br)

0 to 70

AHR

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

2500

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

SOIC

Green (RoHS

& no Sb/Br)

-40 to 125 4113I

-40 to 125 AHS

-40 to 125 TLV4113I

TLV4113IDG4

SOIC

Green (RoHS

& no Sb/Br)

TLV4113IDGQ

TLV4113IDGQG4

TLV4113IDGQR

TLV4113IDGQRG4

TLV4113IN

MSOP-

PowerPAD

DGQ

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

2500

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

PDIP

Pb-Free

(RoHS)

TLV4113INE4

PDIP

Pb-Free

(RoHS)

N / A for Pkg Type

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾Only one of markings shown within the brackets will appear on the physical device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLV4113 :

Enhanced Product: TLV4113-EP

•

NOTE: Qualified Version Definitions:

Enhanced Product - Supports Defense, Aerospace and Medical Applications

•

Addendum-Page 4

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Dec-2011

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV4110IDGNR

MSOP-

Power

PAD

DGN

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

TLV4110IDR

SOIC

2500

330.0

12.4

6.4

5.3

5.2

3.4

2.1

1.4

8.0

12.0

TLV4111IDGNR

MSOP-

Power

PAD

DGN

TLV4111IDR

SOIC

2500

330.0

12.4

6.4

5.3

5.2

3.4

2.1

1.4

8.0

12.0

TLV4112IDGNR

MSOP-

Power

PAD

DGN

TLV4112IDGNR

MSOP-

Power

PAD

DGN

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

TLV4112IDR

SOIC

2500

330.0

12.4

6.4

5.3

5.2

3.4

2.1

1.4

8.0

12.0

TLV4113CDGQR

MSOP-

Power

PAD

DGQ

TLV4113IDGQR

MSOP-

Power

PAD

DGQ

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Dec-2011

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV4110IDGNR

TLV4110IDR

MSOP-PowerPAD

SOIC

DGN

2500

358.0

340.5

358.0

340.5

358.0

364.0

340.5

358.0

335.0

338.1

335.0

338.1

335.0

364.0

338.1

335.0

35.0

20.6

35.0

20.6

35.0

27.0

20.6

35.0

TLV4111IDGNR

TLV4111IDR

MSOP-PowerPAD

SOIC

DGN

TLV4112IDGNR

TLV4112IDR

MSOP-PowerPAD

SOIC

DGN

TLV4113CDGQR

TLV4113IDGQR

MSOP-PowerPAD

DGQ

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

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TLV4110IDGNR产品参数

型号:	TLV4110IDGNR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	MSOP
包装说明：	MSOP-8
针数：	8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.33.00.01
Factory Lead Time：	1 week
风险等级：	1.45
Samacsys Confidence：
Samacsys Status：	Released
Samacsys PartID：	607396
Samacsys Pin Count：	9
Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Other
Samacsys Footprint Name：	SOP65P490X110-9N
Samacsys Released Date：	2017-01-12 12:59:53
Is Samacsys：	N
放大器类型：	OPERATIONAL AMPLIFIER
架构：	VOLTAGE-FEEDBACK
最大平均偏置电流 (IIB)：	0.0005 µA
25C 时的最大偏置电流 (IIB)：	0.00005 µA
最小共模抑制比：	68 dB
标称共模抑制比：	68 dB
频率补偿：	YES
最大输入失调电流 (IIO)：	0.000025 µA
最大输入失调电压：	3500 µV
JESD-30 代码：	S-PDSO-G8
JESD-609代码：	e4
长度：	3 mm
低-偏置：	YES
低-失调：	NO
微功率：	NO
湿度敏感等级：	1
功能数量：	1
端子数量：	8
最高工作温度：	125 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	HTSSOP
封装等效代码：	TSSOP8,.19
封装形状：	SQUARE
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
包装方法：	TR
峰值回流温度（摄氏度）：	260
功率：	NO
电源：	3/5 V
可编程功率：	NO
认证状态：	Not Qualified
座面最大高度：	1.07 mm
最小摆率：	0.55 V/us
标称压摆率：	1.57 V/us
子类别：	Operational Amplifier
最大压摆率：	1 mA
供电电压上限：	6 V
标称供电电压 (Vsup)：	3 V
表面贴装：	YES
技术：	CMOS
温度等级：	AUTOMOTIVE
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
标称均一增益带宽：	2700 kHz
最小电压增益：	7943
宽带：	NO
宽度：	3 mm
Base Number Matches：	1

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