TLV62130RGTR全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

当前位置：IC37首页_>T字母起始型号索引_>T字母起始型号索引第444页更新时间：2024-12-04 18:33:15

产品型号TLV62130RGTR的概述

TLV62130RGTR芯片概述 TLV62130RGTR是一款高效的降压稳压器，广泛应用于各种电源管理方案中，特别适合对低功耗与高效率有要求的设备。这款芯片由德州仪器（Texas Instruments）公司生产，旨在满足现代电子设备对电源转换效率和体积的严格要求。TLV62130RGTR的设计采用了集成电路技术，兼具高性能与灵活性，使其成为众多应用领域的理想选择。 TLV62130RGTR的详细参数 TLV62130RGTR的主要技术参数包括： 1. 输入电压范围：此芯片的输入电压范围为4.5V至17V，能够支持多种电源输入。 2. 输出电压范围：最低输出电压可调至0.8V，适用于多种需求场景。 3. 输出电流：最大输出电流能力可达3A，能够驱动大功率负载。 4. 效率：其最高转换效率可达95%，在较大负载与输入电压范围内保持高效能，这使得该芯片在发热方面表现优异。 5. 开关频率...

产品型号TLV62130RGTR的Datasheet PDF文件预览

TLV62130

www.ti.com

SLVSB74 –FEBRUARY 2012

4-17V 3A Step-Down Converter with DCS-Control^TM

Check for Samples: TLV62130

FEATURES

DESCRIPTION

The TLV62130 is an easy to use synchronous step

down DC-DC converter optimized for applications

with high power density. A high switching frequency

of typically 2.5MHz allows the use of small inductors

and provides fast transient response as well as high

output voltage accuracy by utilization of the

DCS-Control™ topology.

•

DCS-Control ™Topology

Input Voltage Range: 4 to 17V

Up to 3A Output Current

Adjustable Output Voltage from 0.9 to 5V

Pin-Selectable Output Voltage (nominal, + 5%)

Programmable Soft Start and Tracking

Seamless Power Save Mode Transition

Quiescent Current of 19µA (typ.)

Selectable Operating Frequency

Power Good Output

With its wide operating input voltage range of 4V to

17V, the devices are ideally suited for systems

powered from either a Li-Ion or other batteries as well

as from 12V intermediate power rails. It supports up

to 3A continuous output current at output voltages

between 0.9V and 5V (with 100% duty cycle mode).

100% Duty Cycle Mode

The output voltage startup ramp is controlled by the

soft-start pin, which allows operation as either a

standalone power supply or in tracking configurations.

Power sequencing is also possible by configuring the

Enable and open-drain Power Good pins.

Short Circuit Protection

Over Temperature Protection

For Improved Feature Set, see TPS62130

Available in a 3 × 3 mm, QFN-16 Package

In Power Save Mode, the devices show quiescent

current of about 19μA from VIN. Power Save Mode,

entered automatically and seamlessly if load is small,

maintains high efficiency over the entire load range.

In Shutdown Mode, the device is turned off and

shutdown current consumption is less than 2μA.

APPLICATIONS

•

Standard 12V Rail Supplies

POL Supply from Single or Multiple Li-Ion

Battery

•

Embedded Systems

The device is packaged in a 16-pin QFN package

measuring 3 × 3 mm (RGT).

LDO replacement

Mobile PC's, Tablet, Modems, Cameras

spacing

(4 .. 17)V

1 / 2.2 µH

3.3V / 3A

PVIN

AVIN

VOS

100k

10uF

750k

240k

22uF

TLV62130

SS/TR

DEF

3.3nF

AGND

PGND

FSW

Figure 1. Typical Application and Efficiency

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DCS-Control is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TLV62130

SLVSB74 –FEBRUARY 2012

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION⁽¹⁾

T_A

OUTPUT VOLTAGE

PART NUMBER⁽²⁾

PACKAGE

ORDERING

PACKAGE

MARKING

-40°C to 85°C

adjustable

TLV62130

16-Pin QFN

TLV62130RGT

VUBI

(1) For detailed ordering information please check the PACKAGE OPTION ADDENDUM section at the end of this datasheet.

(2) Contact the factory to check availability of other fixed output voltage versions.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.3

MAX

UNIT

AVIN, PVIN

EN, SS/TR

V_IN+0.3

Pin voltage range⁽²⁾

DEF, FSW, FB, PG, VOS

Power Good sink current PG

Operating junction temperature range, T_J

–40

–65

125

150

Temperature range

ESD rating⁽³⁾

°C

Storage temperature range, T_stg

HBM Human body model

CDM Charge device model

0.5

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to network ground terminal.

(3) ESD testing is performed according to the respective JESD22 JEDEC standard.

THERMAL INFORMATION

TLV62130

THERMAL METRIC⁽¹⁾

UNITS

RGT 16 PINS

θ_JA

Junction-to-ambient thermal resistance

29.1

θ_JC(TOP)

θ_JB

Junction-to-case(top) thermal resistance

Junction-to-board thermal resistance

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

0.5

ψ_JB

θ_JC(BOTTOM)

3.5

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

RECOMMENDED OPERATING CONDITIONS

MIN TYP

MAX

UNIT

Supply Voltage, V_IN(at AVIN and PVIN)

Operating free air temperature, T_A

Operating junction temperature, T_J

–40

°C

125

°C

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

www.ti.com

SLVSB74 –FEBRUARY 2012

ELECTRICAL CHARACTERISTICS

over free-air temperature range (T_A=-40°C to +85°C), typical values at V_IN=12V and T_A=25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

SUPPLY

V_IN

Input voltage range⁽¹⁾

Operating quiescent current

Shutdown current⁽²⁾

µA

I_Q

EN=High, I_OUT=0mA, device not switching

1.5

2.7

200

160

I_SD

EN=Low

V_UVLO

Falling Input Voltage

Hysteresis

2.6

0.9

2.8

Undervoltage lockout threshold

T_SD

Thermal shutdown temperature

Thermal shutdown hysteresis

°C

CONTROL (EN, DEF, FSW, SS/TR, PG)

High level input threshold voltage (EN, DEF,

FSW)

V_H

V_L

Low level input threshold voltage (EN, DEF,

FSW)

0.3

I_LKG

Input leakage current (EN, DEF, FSW)

EN=V_INor GND; DEF, FSW=V_OUTor GND

0.01

µA

Rising (%V_OUT

)

V_{TH_PG}

Power good threshold voltage

Falling (%V_OUT

I_PG=-2mA

)

V_{OL_PG}

I_{LKG_PG}

I_SS/TR

Power good output low

Input leakage current (PG)

SS/TR pin source current

0.07

0.3

400

2.7

V_PG=1.8V

µA

2.3

3.6

0.9

2.5

POWER SWITCH

High-side MOSFET ON-resistance

_IN≥6V

mΩ

R_DS(ON)

Low-side MOSFET ON-resistance

High-side MOSFET forward current limit⁽³⁾

I_LIMF

V_IN=12V, T_A= 25°C

4.2

OUTPUT

VREF

Internal reference voltage⁽⁴⁾

Input leakage current (FB)

Output voltage range

0.8

I_{LKG_FB}

V_FB=0.8V

100

5.0

_IN≥ V_OUT

DEF=0 (GND)

DEF=1 (V_OUT

DEF (Output voltage programming)

VOUT

)

VOUT+5%

–2.5

Initial output voltage accuracy⁽⁵⁾

Load regulation⁽⁶⁾

Line regulation⁽⁶⁾

PWM mode operation, V_IN≥ V_OUT+1V

2.5

V_OUT

V_IN=12V, V_OUT=3.3V, PWM mode operation

0.05

0.02

%/A

%/V

4V ≤ V_IN≤ 17V, V_OUT=3.3V, I_OUT= 1A, PWM

mode operation

(1) The device is still functional down to Under Voltage Lockout (see parameter V_UVLO).

(2) Current into AVIN+PVIN pin.

(3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit And Short

Circuit Protection section).

(4) This is the voltage regulated at the FB pin.

(5) This is the accuracy provided by the device itself (line and load regulation effects are not included).

(6) Line and load regulation depend on external component selection and layout (see Figure 16 and Figure 17).

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

SLVSB74 –FEBRUARY 2012

www.ti.com

DEVICE INFORMATION

RGT PACKAGE

(TOP VIEW)

PVIN

AVIN

SS/TR

Exposed

Thermal Pad

Terminal Functions

PIN⁽¹⁾

I/O

DESCRIPTION

NAME

NO.

1,2,3

Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and

output capacitor.

Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires

pull-up resistor; goes high impedance, when device is switched off)

Voltage feedback. Connect resistive voltage divider to this pin.

Analog Ground

Switching Frequency Select (Low ≈ 2.5MHz, High ≈ 1.25MHz for typical operation)⁽²⁾

Output Voltage Scaling (Low = nominal, High = nominal + 5%)⁽²⁾

AGND

FSW

DEF

Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise

time. It can be used for tracking and sequencing.

SS/TR

AVIN

PVIN

11,12

Supply voltage for control circuitry. Connect to same source as PVIN.

Supply voltage for power stage. Connect to same source as AVIN.

Enable input (High = enabled, Low = disabled)⁽²⁾

VOS

PGND

Output voltage sense pin and connection for the control loop circuitry.

Power ground

15,16

Exposed

Thermal Pad

Must be connected to AGND. Must be soldered to achieve appropriate power dissipation and mechanical

reliability.

(1) For more information about connecting pins, see DETAILED DESCRIPTION and APPLICATION INFORMATION sections.

(2) An internal pull-down resistor keeps logic level low, if pin is floating.

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

www.ti.com

SLVSB74 –FEBRUARY 2012

FUNCTIONAL BLOCK DIAGRAM

AVIN

PVIN PVIN

Soft

start

Thermal

Shtdwn

UVLO

PG control

HS lim

comp

EN^*

SS/TR

power

control

gate

drive

control logic

DEF^*

FSW^*

comp

LS lim

direct control

compensation

VOS

ramp

comparator

timer t_ON

error

amplifier

DCS - Control^TM

^*This pin is connected to a pull down resistor internally

(see Detailed Description section).

AGND

PGND PGND

Figure 2. TLV62130

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

SLVSB74 –FEBRUARY 2012

www.ti.com

PARAMETER MEASUREMENT INFORMATION

List of Components

REFERENCE

DESCRIPTION

MANUFACTURER

17V, 3A Step-Down Converter, QFN

2.2µH, 0.165 x 0.165 in

10µF, 25V, Ceramic

TLV62130RGT, Texas Instruments

XFL4020-222MEB, Coilcraft

Standard

Cin

Cout

22µF, 6.3V, Ceramic

Standard

3300pF, 25V, Ceramic

depending on Vout

100kΩ, Chip, 0603, 1/16W, 1%

Standard

spacing

VIN

VOUT

PVIN

AVIN

VOS

CIN

COUT

TLV62130

SS/TR

DEF

FSW

CSS

AGND

PGND

Figure 3. Measurement Setup

TYPICAL CHARACTERISTICS

Table of Graphs

DESCRIPTION

FIGURE

Efficiency

vs Output Current, vs Input Voltage

5 - 16

vs Output current (Load regulation), vs Input Voltage

(Line regulation)

Output voltage

17, 18

vs Input Voltage

Switching Frequency

vs Output Current

Quiescent Current

vs Input Voltage

Shutdown Current

vs Input Voltage

Power FET RDS(on)

Output Voltage Ripple

Maximum Output Current

vs Input Voltage (High-Side, Low-Side)

vs output Current

23, 24

vs Input Voltage

Power Supply Rejection Ratio (PSSR)

vs Frequency

27, 28

PWM-PSM-PWM Mode Transition

Load Transient Response

Startup

30 - 32

33, 34

Waveforms

Typical PWM Mode Operation

Typical Power Save Mode Operation

vs Load Current

Maximum Ambient Temperature

vs Power Dissipation

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

www.ti.com

SLVSB74 –FEBRUARY 2012

EFFICIENCY

OUTPUT CURRENT

INPUT VOLTAGE

100.0

90.0

80.0

70.0

60.0

50.0

40.0

30.0

20.0

10.0

0.0

100.0

90.0

80.0

70.0

60.0

50.0

40.0

30.0

20.0

10.0

0.0

VIN=17V

VIN=12V

IOUT=10mA

IOUT=1A

IOUT=1mA

IOUT=100mA

VOUT=5.0V

L=2.2uH (XFL4020)

Cout=22uF

VOUT=5.0V

L=2.2uH (XFL4020)

Cout=22uF

0.0001

0.001

0.01

0.1

Output Current (A)

Input Voltage (V)

G001

Figure 4. Efficiency with 1.25MHz, Vout=5V

Figure 5. Efficiency with 1.25MHz, Vout=5V

EFFICIENCY

OUTPUT CURRENT

EFFICIENCY

INPUT VOLTAGE

100.0

90.0

80.0

70.0

60.0

50.0

40.0

30.0

20.0

10.0

0.0

100.0

90.0

80.0

70.0

60.0

50.0

40.0

30.0

20.0

10.0

0.0

VIN=17V

VIN=12V

IOUT=10mA

IOUT=1A

IOUT=1mA

IOUT=100mA

VOUT=5.0V

L=2.2uH (XFL4020)

Cout=22uF

VOUT=5.0V

L=2.2uH (XFL4020)

Cout=22uF

0.0001

0.001

0.01

0.1

Output Current (A)

Input Voltage (V)

G001

Figure 6. Efficiency with 2.5MHz, Vout=5V

Figure 7. Efficiency with 2.5MHz, Vout=5V

EFFICIENCY

OUTPUT CURRENT

EFFICIENCY

INPUT VOLTAGE

100.0

90.0

80.0

70.0

60.0

50.0

40.0

30.0

20.0

10.0

0.0

100.0

90.0

80.0

70.0

60.0

50.0

40.0

30.0

20.0

10.0

0.0

VIN=12V

VIN=17V

VIN=5V

IOUT=1A IOUT=100mA IOUT=10mA

IOUT=1mA

VOUT=3.3V

L=2.2uH (XFL4020)

Cout=22uF

VOUT=3.3V

L=2.2uH (XFL4020)

Cout=22uF

0.0001

0.001

0.01

0.1

10 11 12 13 14 15 16 17

Output Current (A)

Input Voltage (V)

G001

Figure 8. Efficiency with 1.25MHz, Vout=3.3V

Figure 9. Efficiency with 1.25MHz, Vout=3.3V

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

SLVSB74 –FEBRUARY 2012

www.ti.com

EFFICIENCY

OUTPUT CURRENT

INPUT VOLTAGE

100.0

90.0

80.0

70.0

60.0

50.0

100.0

90.0

80.0

70.0

60.0

50.0

40.0

30.0

20.0

10.0

0.0

VIN=12V

VIN=17V

IOUT=100mA

IOUT=1mA

VIN=5V

IOUT=10mA

IOUT=1A

40.0

30.0

20.0

10.0

0.0

VOUT=3.3V

L=2.2uH (XFL4020)

Cout=22uF

VOUT=3.3V

L=2.2uH (XFL4020)

Cout=22uF

0.0001

0.001

0.01

0.1

10 11 12 13 14 15 16 17

Output Current (A)

Input Voltage (V)

G001

Figure 10. Efficiency with 2.5MHz, Vout=3.3V

Figure 11. Efficiency with 2.5MHz, Vout=3.3V

EFFICIENCY

OUTPUT CURRENT

INPUT VOLTAGE

100.0

90.0

80.0

70.0

60.0

50.0

40.0

30.0

20.0

10.0

0.0

100.0

90.0

80.0

70.0

60.0

50.0

40.0

30.0

20.0

10.0

0.0

VIN=12V

VIN=17V

IOUT=1A

IOUT=100mA

IOUT=10mA

VIN=5V

IOUT=1mA

VOUT=1.8V

L=2.2uH (XFL4020)

Cout=22uF

VOUT=1.8V

L=2.2uH (XFL4020)

Cout=22uF

0.0001

0.001

0.01

0.1

10 11 12 13 14 15 16 17

Output Current (A)

Input Voltage (V)

G001

Figure 12. Efficiency with 1.25MHz, Vout=1.8V

Figure 13. Efficiency with 1.25MHz, Vout=1.8V

EFFICIENCY

OUTPUT CURRENT

INPUT VOLTAGE

100.0

90.0

80.0

70.0

60.0

50.0

40.0

30.0

20.0

10.0

0.0

100.0

90.0

80.0

70.0

60.0

50.0

40.0

30.0

20.0

10.0

0.0

VIN=12V

VIN=17V

IOUT=1A

IOUT=100mA

IOUT=10mA

IOUT=1mA

VIN=5V

VOUT=0.9V

L=2.2uH (XFL4020)

Cout=22uF

VOUT=0.9V

L=2.2uH (XFL4020)

Cout=22uF

0.0001

0.001

0.01

0.1

10 11 12 13 14 15 16 17

Output Current (A)

Input Voltage (V)

G001

Figure 14. Efficiency with 1.25MHz, Vout=0.9V

Figure 15. Efficiency with 1.25MHz, Vout=0.9V

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

www.ti.com

SLVSB74 –FEBRUARY 2012

OUTPUT VOLTAGE

OUTPUT CURRENT

INPUT VOLTAGE

3.40

3.35

3.30

3.25

3.20

VIN=17V

VIN=12V

IOUT=10mA

IOUT=1mA

IOUT=1A

3.35

3.30

3.25

3.20

VIN=5V

IOUT=100mA

VOUT=3.3V

L=2.2uH (XFL4020)

Cout=22uF

VOUT=3.3V

L=2.2uH (XFL4020)

Cout=22uF

0.0001

0.001

0.01

0.1

Input Voltage (V)

Output Current (A)

G001

Figure 16. Output Voltage Accuracy (Load Regulation)

Figure 17. Output Voltage Accuracy (Line Regulation)

SWITCHING FREQUENCY

INPUT VOLTAGE

OUTPUT CURRENT

3.5

IOUT=2A

IOUT=3A

2.5

IOUT=0.5A

IOUT=1A

1.5

VOUT=3.3V

VIN=12V, VOUT=3.3V

L=2.2uH (XFL4020)

Cout=22uF

L=2.2uH (XFL4020)

FSW=Low

0.5

1.5

2.5

Input Voltage (V)

Output Current (A)

G000

Figure 18. Switching Frequency

Figure 19. Switching Frequency

INPUT CURRENT

INPUT VOLTAGE

50.0

45.0

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

85°C

25°C

85°C

−40°C

12.0

25°C

−40°C

0.0

3.0

6.0

9.0

12.0

15.0

18.0 20.0

3.0

6.0

9.0

15.0

18.0 20.0

Input Voltage (V)

G001

Figure 20. Quiescent Current

Figure 21. Shutdown Current

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

SLVSB74 –FEBRUARY 2012

www.ti.com

STATIC DRAIN-SOURCE-RESISTANCE (R_DSon

)

STATIC DRAIN-SOURCE-RESISTANCE (R_DSon

)

INPUT VOLTAGE

200.0

180.0

160.0

140.0

120.0

100.0

80.0

100.0

80.0

60.0

40.0

20.0

0.0

125°C

85°C

25°C

85°C

25°C

−10°C

60.0

−40°C

40.0

−40°C

20.0

0.0

3.0

6.0

9.0

12.0

15.0

18.0 20.0

0.0

3.0

6.0

9.0

12.0

15.0

18.0 20.0

Input Voltage (V)

G001

Figure 22. High-Side Switch Resistance

Figure 23. Low-Side Switch Resistance

OUTPUT VOLTAGE

OUTPUT CURRENT

INPUT VOLTAGE

0.05

0.04

0.03

0.02

0.01

5.5

VOUT=3.3V,

L=2.2uH (XFL4020)

Cout=22uF

−40°C

4.5

3.5

VIN=17V

VIN=5V

25°C

2.5

85°C

1.5

VOUT=3.3V

L=2.2uH (XFL4020)

Cout=22uF

0.5

VIN=12V

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7

Output Current (A)

10 11 12 13 14 15 16 17

Input Voltage (V)

G000

Figure 24. Output Voltage Ripple

Figure 25. Maximum Output Current

POWER SUPPLY REJECTION RATIO

FREQUENCY

100

VIN=12V

VIN=5V

VIN=12V

VIN=17V

VOUT=3.3V, IOUT=1A

L=2.2uH (XFL4020)

Cin=10uF, Cout=22uF

VOUT=3.3V, IOUT=0.1A

L=2.2uH (XFL4020)

Cin=10uF, Cout=22uF

100

10k

100k

100

10k

100k

Frequency (Hz)

G000

Figure 26. Power Supply Rejection Ratio, f_SW=2.5MHz

Figure 27. Power Supply Rejection Ratio, f_SW=2.5MHz

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

www.ti.com

SLVSB74 –FEBRUARY 2012

OUTPUT VOLTAGE

TIME

Figure 28. PWM-PSM-Transition (V_IN=12V, V_OUT=3.3V with

50mV/div)

Figure 29. Load Transient Response (I_OUT= 0.5 to 3 to 0.5

A, V_IN=12V, V_OUT=3.3V)

OUTPUT VOLTAGE

TIME

Figure 30. Load Transient Response of Figure 29, rising

edge

Figure 31. Load Transient Response of Figure 29, falling

edge

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

SLVSB74 –FEBRUARY 2012

www.ti.com

OUTPUT VOLTAGE

TIME

Figure 32. Startup into 100mA (VIN=12V, VOUT=3.3V)

Figure 33. Startup into 3A (VIN=12V, VOUT=3.3V)

PWM SIGNALS

POWER SAVE MODE SIGNALS

TIME

Figure 34. Typical Operation in PWM Mode (I_OUT=1A)

Figure 35. Typical Operation in Power Save Mode

(I_OUT=10mA)

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

www.ti.com

SLVSB74 –FEBRUARY 2012

AMBIENT TEMPERATURE

OUTPUT CURRENT

OUTPUT POWER

125

115

105

115

105

TLV62130 EVM

L=2.2uH (XFL4020)

L=2.2uH(XFL4020)

VIN=12V, VOUT=3.3V

0.5

1.5

2.5

3.5

Output Current (A)

Output Power (W)

G000

Figure 36. Maximum Ambient Temperature (f_SW=2.5MHz)

Figure 37. Maximum Ambient Temperature (f_SW=2.5MHz)

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

SLVSB74 –FEBRUARY 2012

www.ti.com

DETAILED DESCRIPTION

Device Operation

The TLV62130 synchronous switched mode power converters are based on DCS-Control™ (Direct Control with

Seamless Transition into Power Save Mode), an advanced regulation topology, that combines the advantages of

hysteretic, voltage mode and current mode control including an AC loop directly associated to the output voltage.

This control loop takes information about output voltage changes and feeds it directly to a fast comparator stage.

It sets the switching frequency, which is constant for steady state operating conditions, and provides immediate

response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The

internally compensated regulation network achieves fast and stable operation with small external components

and low ESR capacitors.

The DCS-Control^TMtopology supports PWM (Pulse Width Modulation) mode for medium and heavy load

conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in

continuous conduction mode. This frequency is typically about 2.5MHz with a controlled frequency variation

depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain

high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly with the

load current. Since DCS-Control^TMsupports both operation modes within one single building block, the transition

from PWM to Power Save Mode is seamless without effects on the output voltage. An internal current limit

supports nominal output currents of up to 3A.

The TLV62130 offers both excellent DC voltage and superior load transient regulation, combined with very low

output voltage ripple, minimizing interference with RF circuits.

Pulse Width Modulation (PWM) Operation

The TLV62130 operates with pulse width modulation in continuous conduction mode (CCM) with a nominal

switching frequency of 2.5 MHz or 1.25MHz, selectable with the FSW pin. The frequency variation in PWM is

controlled and depends on V_IN, V_OUTand the inductance. The device operates in PWM mode as long the output

current is higher than half the inductor's ripple current. To maintain high efficiency at light loads, the device

enters Power Save Mode at the boundary to discontinuous conduction mode (DCM). This happens if the output

current becomes smaller than half the inductor's ripple current.

Power Save Mode Operation

The TLV62130's built in Power Save Mode will be entered seamlessly, if the load current decreases. This

secures a high efficiency in light load operation. The device remains in Power Save Mode as long as the inductor

current is discontinuous.

In Power Save Mode the switching frequency decreases linearly with the load current maintaining high efficiency.

The transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in

both directions.

TLV62130 includes a fixed on-time circuitry. This on-time, in steady-state operation, can be estimated as:

V_OUT

t_ON

× 400ns

V_IN

(1)

For very small output voltages, an absolute minimum on-time of about 80ns is kept to limit switching losses.

Using t_ON, the typical peak inductor current in Power Save Mode can be approximated by:

(V_IN-V_OUT

)

I_{LPSM ( peak )}

×t_ON

(2)

When V_INdecreases to typically 15% above VOUT, the TLV62130 won't enter Power Save Mode, regardless of

the load current. The device maintains output regulation in PWM mode.

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

www.ti.com

SLVSB74 –FEBRUARY 2012

100% Duty-Cycle Operation

The duty cycle of the buck converter is given by D=Vout/Vin and increases as the input voltage comes close to

the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch

100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal

setpoint. This allows the conversion of small input to output voltage differences, e.g. for longest operation time of

battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.

The minimum input voltage to maintain output voltage regulation, depending on the load current and the output

voltage level, can be calculated as:

( )

R_{DS( on )}+ R_L

V_IN(min)=V_OUT(min)+ I_OUT

(3)

where

I_OUTis the output current,

R_DS(on)is the R_DS(on)of the high-side FET and

R_Lis the DC resistance of the inductor used.

Enable / Shutdown (EN)

When Enable (EN) is set High, the device starts operation.

Shutdown is forced if EN is pulled Low with a shutdown current of typically 1.5µA. During shutdown, the internal

power MOSFETs as well as the entire control circuitry are turned off. The internal resistive divider pulls down the

output voltage smoothly. An internal pull-down resistor of about 400kΩ is connected and keeps EN logic low, if

the pin is floating. It is disconnected if the pin is High.

Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple

power rails.

Soft Start / Tracking (SS/TR)

The internal soft start circuitry controls the output voltage slope during startup. This avoids excessive inrush

current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from

high-impedance power sources or batteries. When EN is set to start device operation, the device starts switching

after a delay of about 50µs and VOUT rises with a slope controlled by an external capacitor connected to the

SS/TR pin. See Figure 32 and Figure 33 for typical startup operation.

Connecting SS/TR directly to AVIN provides fastest startup behavior. The TLV62130 can start into a pre-biased

output. During monotonic pre-biased startup, the low-side MOSFET is not allowed to turn on until the device's

internal ramp sets an output voltage above the pre-bias voltage. As long as the output is below about 0.5V a

reduced current limit of typically 1.6A is set internally. If the device is set to shutdown (EN=GND), undervoltage

lockout or thermal shutdown, an internal resistor pulls the SS/TR pin down to ensure a proper low level.

Returning from those states causes a new startup sequence as set by the SS/TR connection.

A voltage supplied to SS/TR can be used for tracking a master voltage. The output voltage will follow this voltage

in both directions up and down (see APPLICATION INFORMATION).

Current Limit And Short Circuit Protection

The TLV62130 device is protected against heavy load and short circuit events. If a short circuit is detected

(VOUT drops below 0.5V), the current limit is reduced to 1.6A typically. If the output voltage rises above 0.5V,

the device will run in normal operation again. At heavy loads, the current limit determines the maximum output

current. If the current limit is reached, the high-side FET will be turned off. Avoiding shoot through current, the

low-side FET will be switched on to sink the inductor current. The high-side FET will turn on again, only if the

current in the low-side FET has decreased below the low side current limit threshold.

The output current of the device is limited by the current limit (see ELECTRICAL CHARACTERISTICS). Due to

internal propagation delay, the actual current can exceed the static current limit during that time. The dynamic

current limit can be calculated as follows:

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

SLVSB74 –FEBRUARY 2012

www.ti.com

V_L

I _peak(typ)= I_LIMF

× t_PD

(4)

where

I_LIMFis the static current limit, specified in the ELECTRICAL CHARACTERISTICS,

L is the inductor value,

V_Lis the voltage across the inductor (V_IN- V_OUT) and

t_PDis the internal propagation delay.

The current limit can exceed static values, especially if the input voltage is high and very small inductances are

used. The dynamic high side switch peak current can be calculated as follows:

₊(^V_IN-V_OUT)_×30ns

I _peak(typ)= I_LIMF

(5)

Power Good (PG)

The TLV62130 has a built in power good (PG) function to indicate whether the output voltage has reached its

appropriate level or not. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an

open-drain output that requires a pull-up resistor (to any voltage below 7V). It can sink 2mA of current and

maintain its specified logic low level. It is high impedance when the device is turned off due to EN, UVLO or

thermal shutdown.

Pin-Selectable Output Voltage (DEF)

The output voltage of the TLV62130 devices can be increased by 5% above the nominal voltage by setting the

DEF pin to High⁽¹⁾. When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal

voltage allows adapting the power supply voltage to the variations of the application hardware. More detailed

information on voltage margining using TLV62130 can be found in SLVA489. A pull down resistor of about

400kOhm is internally connected to the pin, to ensure a proper logic level if the pin is high impedance or floating.

The resistor is disconnected if the pin is High.

Frequency Selection (FSW)

To get high power density with very small solution size, a high switching frequency allows the use of small

external components for the output filter. However switching losses increase with the switching frequency. If

efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz

typ.) by pulling FSW to High⁽¹⁾. Pull FSW to Low for high frequency operation (2.5 MHz typ.). Running with lower

frequency a higher efficiency, but also a higher output voltage ripple, is achieved. To get low ripple and full output

current at the lower switching frequency, it's recommended to use an inductor of at least 2.2uH. The switching

frequency can be changed during operation, if needed. A pull down resistor of about 400kOhm is internally

connected to the pin, to ensure a proper logic level if the pin is high impedance or floating. The resistor is

disconnected if the pin is High.

Under Voltage Lockout (UVLO)

If the input voltage drops, the under voltage lockout prevents misoperation of the device by switching off both the

power FETs. The under voltage lockout threshold is set typically to 2.7V. The device is fully operational for

voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts

operation again once the input voltage exceeds the threshold by a hysteresis of typically 200mV.

Thermal Shutdown

The junction temperature (Tj) of the device is monitored by an internal temperature sensor. If Tj exceeds 160°C

(typ), the device goes into thermal shut down. Both the high-side and low-side power FETs are turned off and PG

goes high impedance. When Tj decreases below the hysteresis amount, the converter resumes normal

operation, beginning with Soft Start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented

on the thermal shut down temperature.

(1) Maximum allowed voltage is 7V. Therefore, it's recommended to connect it to VOUT, not VIN.

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

www.ti.com

SLVSB74 –FEBRUARY 2012

APPLICATION INFORMATION

The following information is intended to be a guideline through the individual power supply design process.

Programming The Output Voltage

The TLV62130 can be programmed for output voltages from 0.9V to 5V by using a resistive divider from VOUT

to AGND. The voltage at the FB pin is regulated to 800mV. The value of the output voltage is set by the selection

of the resistive divider from Equation 6 (see Figure 3). It is recommended to choose resistor values which allow a

current of at least 2uA, meaning the value of R2 shouldn't exceed 400kΩ. Lower resistor values are

recommended for highest accuracy and most robust design.

V_OUT

V_REF

R₁= R₂

-1

(6)

In case the FB pin gets opened, the device clamps the output voltage at the VOS pin internally to about 7.4V.

External Component Selection

The external components have to fulfill the needs of the application, but also the stability criteria of the devices

control loop. The TLV62130 is optimized to work within a range of external components. The LC output filters

inductance and capacitance have to be considered together, creating a double pole, responsible for the corner

frequency of the converter (see Output Filter And Loop Stability). Table 1 can be used to simplify the output filter

component selection.

Table 1. Recommended LC Output Filter Combinations⁽¹⁾

4.7µF

10µF

22µF

47µF

100µF

200µF

400µF

0.47µH

1µH

√

(2)

2.2µH

3.3µH

4.7µH

√

(1) The values in the table are nominal values.

(2) This LC combination is the standard value and recommended for most applications.

spacing

The TLV62130 can be run with an inductor as low as 1µH. FSW should be set Low in this case. However, for

applications running with the low frequency setting (FSW=High) or with low input voltages, 2.2µH is

recommended. More detailed information on further LC combinations can be found in SLVA463.

Inductor Selection

The inductor selection is affected by several effects like inductor ripple current, output ripple voltage,

PWM-to-PSM transition point and efficiency. In addition, the inductor selected has to be rated for appropriate

saturation current and DC resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current

under static load conditions.

spacing

DI_L(max)

I_L(max)= I_OUT(max)

(7)

V_OUT

V_IN(max)

DI_L(max)= V_OUT

L_(min)× f_SW

(8)

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

SLVSB74 –FEBRUARY 2012

www.ti.com

where

I_L(max) is the maximum inductor current,

ΔI_Lis the Peak to Peak Inductor Ripple Current,

L(min) is the minimum effective inductor value and

f_SWis the actual PWM Switching Frequency.

spacing

Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation

current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also

useful to get lower ripple current, but increases the transient response time and size as well. The following

inductors have been used with the TLV62130 and are recommended for use:

Table 2. List of Inductors

Type

Inductance [µH]

Current [A]⁽¹⁾

Dimensions [LxBxH]

MANUFACTURER

XFL4020-102ME_

XFL4020-152ME_

XFL4020-222ME_

IHLP1212BZ-11

SRP4020-3R3M

VLC5045T-3R3N

1.0 µH, ±20%

1.5 µH, ±20%

2.2 µH, ±20%

1.0 µH, ±20%

2.2 µH, ±20%

3.3µH, ±20%

3.3µH, ±30%

4.7

4.2

3.8

4.5

3.0

3.3

4.0

4 x 4 x 2.1

3 x 3.6 x 2

4.8 x 4 x 2

5 x 5 x 4.5

Coilcraft

Vishay

Bourns

TDK

(1) Lower of I_RMSat 40°C rise or I_SATat 30% drop.

spacing

The inductor value also determines the load current at which Power Save Mode is entered:

I_{load(PSM )}

DI_L

(9)

Using Equation 8, this current level can be adjusted by changing the inductor value.

Capacitor Selection

Output Capacitor

The recommended value for the output capacitor is 22uF. The architecture of the TLV62130 allows the use of

tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output

voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow

capacitance variation with temperature, it's recommended to use X7R or X5R dielectric. Using a higher value can

have some advantages like smaller voltage ripple and a tighter DC output accuracy in Power Save Mode (see

SLVA463).

Note: In power save mode, the output voltage ripple depends on the output capacitance, its ESR and the peak

inductor current. Using ceramic capacitors provides small ESR and low ripple.

Input Capacitor

For most applications, 10µF will be sufficient and is recommended, though a larger value reduces input current

ripple further. The input capacitor buffers the input voltage for transient events and also decouples the converter

from the supply. A low ESR multilayer ceramic capacitor is recommended for best filtering and should be placed

between PVIN and PGND as close as possible to those pins. Even though AVIN and PVIN must be supplied

from the same input source, it's required to place a capacitance of 0.1uF from AVIN to AGND, to avoid potential

noise coupling. An RC, low-pass filter from PVIN to AVIN may be used but is not required.

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

www.ti.com

SLVSB74 –FEBRUARY 2012

Soft Start Capacitor

A capacitance connected between SS/TR pin and AGND allows a user programmable start-up slope of the

output voltage. A constant current source supports 2.5µA to charge the external capacitance. The capacitor

required for a given soft-start ramp time for the output voltage is given by:

2.5mA

C_SS= t_SS×

[^F]

1.25V

(10)

where

C_SSis the capacitance (F) required at the SS/TR pin and

t_SSis the desired soft-start ramp time (s).

spacing

NOTE

DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will

have a strong influence on the final effective capacitance. Therefore the right capacitor

value has to be chosen carefully. Package size and voltage rating in combination with

dielectric material are responsible for differences between the rated capacitor value and

the effective capacitance.

spacing

Tracking Function

If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external

tracking voltage. The output voltage tracks that voltage. If the tracking voltage is between 50mV and 1.2V, the

FB pin will track the SS/TR pin voltage as described in Equation 11 and shown in Figure 38.

spacing

V_FB» 0.64×V_{SS /TR}

(11)

VSS/TR

[V]

1.2

0.8

0.4

VFB [V]

0.2

0.4

0.6

0.8

Figure 38. Voltage Tracking Relationship

This works for rising and falling tracking voltages with the same behavior, as long as the input voltage is inside

the recommended operating conditions. When driving the SS/TR pin with an external voltage, do not exceed the

voltage rating of the SS/TR pin which is V_IN+0.3V.

If the input voltage drops into undervoltage lockout or even down to zero, the output voltage will go to zero,

independent of the tracking voltage. Figure 39 shows how to connect devices to get ratiometric and simultaneous

sequencing by using the tracking function.

spacing

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

SLVSB74 –FEBRUARY 2012

www.ti.com

VOUT1

PVIN

AVIN

VOS

TLV62130

SS/TR

DEF

AGND

PGND

FSW

VOUT2

PVIN

AVIN

VOS

TLV62130

SS/TR

DEF

AGND

PGND

FSW

Figure 39. Sequence for Ratiometric and Simultaneous Startup

The resistive divider of R1 and R2 can be used to change the ramp rate of VOUT2 faster, slower or the same as

VOUT1.

A sequential startup is achieved by connecting the PG pin of VOUT1 to the EN pin of VOUT2. Ratiometric start

up sequence happens if both supplies are sharing the same soft start capacitor. Equation 10 calculates the soft

start time, though the SS/TR current has to be doubled. Details about these and other tracking and sequencing

circuits are found in SLVA470.

Note: If the voltage at the FB pin is below its typical value of 0.8V, the output voltage accuracy may have a wider

tolerance than specified.

Output Filter And Loop Stability

The TLV62130 is internally compensated to be stable with L-C filter combinations corresponding to a corner

frequency to be calculated with Equation 12:

f_LC

2p L × C

(12)

Proven nominal values for inductance and ceramic capacitance are given in Table 1 and are recommended for

use. Different values may work, but care has to be taken on the loop stability which will be affected. More

information including a detailed LC stability matrix can be found in SLVA463.

The TLV62130 device includes an internal 25pF feedforward capacitor, connected between the VOS and FB

pins. This capacitor impacts the frequency behavior and sets a pole and zero in the control loop with the resistors

of the feedback divider, per equation Equation 13 and Equation 14:

spacing

f_zero

2p × R × 25pF

(13)

spacing

f _pole

2p × 25pF

(14)

spacing

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

www.ti.com

SLVSB74 –FEBRUARY 2012

Though the TLV62130 is stable without the pole and zero being in a particular location, adjusting their location to

the specific needs of the application can provide better performance in Power Save mode and/or improved

transient response. An external feedforward capacitor can also be added. A more detailed discussion on the

optimization for stability vs. transient response can be found in SLVA289 and SLVA466.

Layout Considerations

A proper layout is critical for the operation of a switched mode power supply, even more at high switching

frequencies. Therefore the PCB layout of the TLV62130 demands careful attention to ensure operation and to

get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability

and accuracy weaknesses, increased EMI radiation and noise sensitivity.

Provide low inductive and resistive paths for loops with high di/dt. Therefore paths conducting the switched load

current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for

wires with high dv/dt. Therefore the input and output capacitance should be placed as close as possible to the IC

pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct an

alternating current should outline an area as small as possible, as this area is proportional to the energy radiated.

Also sensitive nodes like FB and VOS should be connected with short wires, not nearby high dv/dt signals (e.g.

SW). As they carry information about the output voltage, they should be connected as close as possible to the

actual output voltage (at the output capacitor). Signals not assigned to power transmission (e.g. feedback divider,

SS/TR capacitor) should refer to the signal ground (AGND) and always be separated from the power ground

(PGND).

In summary, the input capacitor should be placed as close as possible to the PVIN and PGND pins of the IC.

This connections should be done with wide and short traces. The output capacitor should be placed such that its

ground is as close as possible to the IC's PGND pins - avoiding additional voltage drop in traces. This connection

should also be made short and wide. The inductor should be placed close to the SW pin and connect directly to

the output capacitor - minimizing the loop area between the SW pin, inductor, output capacitor and PGND pin.

The feedback resistors, R₁and R₂, should be placed close to the IC and connect directly to the AGND and FB

pins. Those connections (including VOUT) to the resistors and even more to the VOS pin should stay away from

noise sources, such as the inductor. The VOS pin should connect in the shortest way to VOUT at the output

capacitor, while the VOUT connection to the feedback divider can connect at the load. The capacitor on the

SS/TR pin should be kept close to the IC and its return should be connected to AGND

See Figure 40 for the recommended layout of the TLV62130. AGND is connected to the Exposed Thermal Pad,

which is also connected to PGND and internal metal layers to get best thermal performance. The regulation loop

is closed from COUT directly to AGND with vias down to the AGND bottom layer. More detailed information can

be found in the EVM Users Guide, SLAU416.

The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve

appropriate power dissipation. Although the Exposed Thermal Pad can be connected to a floating circuit board

trace, the device will have better thermal performance if it is connected to a larger ground plane. The Exposed

Thermal Pad is electrically connected to AGND.

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

SLVSB74 –FEBRUARY 2012

www.ti.com

AGND

AVIN

CIN

VOUT

COUT

PGND

Figure 40. Layout Example

THERMAL INFORMATION

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires

special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added

heat sinks and convection surfaces, and the presence of other heat-generating components affect the

power-dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are listed below:

•

Improving the power dissipation capability of the PCB design

Improving the thermal coupling of the component to the PCB by soldering the Exposed Thermal Pad

Introducing airflow in the system

For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics

Application Note (SZZA017), and (SPRA953).

The TLV62130 is designed for a maximum operating junction temperature (T_j) of 125°C. Therefore the maximum

output power is limited by the power losses that can be dissipated over the actual thermal resistance, given by

the package and the surrounding PCB structures. If the thermal resistance of the package is given, the size of

the surrounding copper area and a proper thermal connection of the IC can reduce the thermal resistance. To

get an improved thermal behavior, it's recommended to use top layer metal to connect the device with wide and

thick metal lines. Internal ground layers can connect to vias directly under the IC for improved thermal

performance.

If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.

Experimental data, taken from the TLV62130 EVM, shows the maximum ambient temperature (without additional

cooling like airflow or heat sink), that can be allowed to limit the junction temperature to at most 125°C (see ).

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

www.ti.com

SLVSB74 –FEBRUARY 2012

Application Example As Power LED Supply

The TLV62130 can be used as a power supply for power LEDs. The FB pin can be easily set down to lower

values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low to avoid

excessive power loss. Since this pin provides 2.5µA, the feedback pin voltage can be adjusted by an external

resistor per Equation 15. This drop, proportional to the LED current, is used to regulate the output voltage (anode

voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with the TLV62130.

Figure 41 shows an application circuit, tested with analog dimming:

spacing

(4 .. 17) V

2.2µH

PVIN

AVIN

VOS

4.7uF

22uF

ADIM

TLV62130

SS/TR

DEF

187k

0.1R

AGND

PGND

FSW

Figure 41. 3A Single LED Power Supply

The resistor at SS/TR sets the FB voltage to a level of about 300mV and is calculated from Equation 15.

spacing

V_FB= 0.64 × 2.5mA × R_{SS / TR}

(15)

spacing

The device now supplies a constant current, set by the resistor at the FB pin, by regulating the output voltage

accordingly. The minimum input voltage has to be rated according the forward voltage needed by the LED used.

More information is available in the Application Note SLVA451.

Application Example As Inverting Power Supply

The TLV62130 can be used as inverting power supply by rearranging external circuitry as shown in Figure 42. As

the former GND node now represents a voltage level below system ground, the voltage difference between VIN

and VOUT has to be limited for operation to the maximum supply voltage of 17V (see Equation 16).

spacing

V_IN+V_OUT£V_{IN max}

(16)

spacing

10uF

2.2µH

(3 .. 12)V

VIN

AVIN

VOS

680k

130k

100k

10uF

22uF

TLV62130

SS/TR

DEF

FSW

-5V

PGND

AGND

Figure 42. -5V Inverting Power Supply

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

SLVSB74 –FEBRUARY 2012

www.ti.com

Typical Applications

spacing

1 / 2.2 µH

(5 .. 17)V

5V / 3A

PVIN

AVIN

VOS

100k

10uF

680k

130k

22uF

TLV62130

SS/TR

DEF

3.3nF

AGND

PGND

FSW

Figure 43. 5V/3A Power Supply

spacing

1 / 2.2 µH

(4 .. 17)V

3.3V / 3A

PVIN

AVIN

VOS

100k

10uF

750k

240k

22uF

TLV62130

SS/TR

DEF

AGND

PGND

FSW

Figure 44. 3.3V/3A Power Supply

spacing

1 / 2.2 µH

(4 .. 17)V

2.5V / 3A

PVIN

AVIN

VOS

100k

10uF

510k

240k

22uF

TLV62130

SS/TR

DEF

AGND

PGND

FSW

Figure 45. 2.5V/3A Power Supply

spacing

Submit Documentation Feedback

Product Folder Link(s): TLV62130

TLV62130

www.ti.com

SLVSB74 –FEBRUARY 2012

1 / 2.2 µH

(4 .. 17)V

1.8V / 3A

PVIN

AVIN

VOS

100k

10uF

300k

240k

22uF

TLV62130

SS/TR

DEF

3.3nF

AGND

PGND

FSW

Figure 46. 1.8V/3A Power Supply

spacing

1 / 2.2 µH

(4 .. 17)V

1.5V / 3A

PVIN

AVIN

VOS

100k

10uF

130k

150k

22uF

TLV62130

SS/TR

DEF

AGND

PGND

FSW

Figure 47. 1.5V/3A Power Supply

spacing

1 / 2.2 µH

(4 .. 17)V

1.2V / 3A

PVIN

AVIN

VOS

100k

10uF

75k

22uF

TLV62130

SS/TR

DEF

150k

AGND

PGND

FSW

Figure 48. 1.2V/3A Power Supply

spacing

1 / 2.2 µH

(4 .. 17)V

1V / 3A

PVIN

AVIN

VOS

100k

10uF

51k

22uF

TLV62130

SS/TR

DEF

200k

AGND

PGND

FSW

Figure 49. 1V/3A Power Supply

Submit Documentation Feedback

Product Folder Link(s): TLV62130

PACKAGE OPTION ADDENDUM

www.ti.com

5-Mar-2012

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

TLV62130RGTR

TLV62130RGTT

ACTIVE

QFN

RGT

3000

250

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Mar-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV62130RGTR

TLV62130RGTT

QFN

RGT

3000

250

330.0

180.0

12.4

3.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Mar-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV62130RGTR

TLV62130RGTT

QFN

RGT

3000

250

552.0

346.0

185.0

36.0

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Audio

Applications

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

www.ti.com/security

Medical

Logic

Security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense www.ti.com/space-avionics-defense

microcontroller.ti.com

www.ti-rfid.com

Video and Imaging

www.ti.com/video

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community Home Page

e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TLV62130RGTR相关文章

配单直通车

首天国际（深圳）科技有限公司服务专线: 0755-82807802/82807803 在线联系:

QQ：528164397 复制

QQ：1318502189 复制

柒号芯城电子商务（深圳）有限公司服务专线: 18922803401 在线联系:

QQ：2881677436 复制

QQ：2881620402 复制

北京元坤伟业科技有限公司服务专线: 010-62104931621064316210489162104791 在线联系:

QQ：857273081 复制

QQ：1594462451 复制

深圳市芯福林电子有限公司服务专线: 13418564337 在线联系:

QQ：2881495808 复制

QQ：308365177 复制

深圳市中利达电子科技有限公司服务专线: 0755-13686833545 在线联系:

QQ：1902134819 复制

QQ：2881689472 复制

TLV62130RGTR产品参数

型号:	TLV62130RGTR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
包装说明：	HVQCCN, LCC16,.12SQ,20
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	0.86
其他特性：	ALSO HAS CURRENT CONTROL MODE; ALSO OPERATES IN ADJUSTABLE MODE FROM 0.9V TO 5V
模拟集成电路 - 其他类型：	SWITCHING REGULATOR
控制模式：	VOLTAGE-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	17 V
最小输入电压：	4 V
标称输入电压：	12 V
JESD-30 代码：	S-PQCC-N16
JESD-609代码：	e4
长度：	3 mm
湿度敏感等级：	2
功能数量：	1
端子数量：	16
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出电流：	3 A
最大输出电压：	5.5 V
最小输出电压：	0.9 V
封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN
封装等效代码：	LCC16,.12SQ,20
封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	BUCK
最大切换频率：	2500 kHz
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3 mm
Base Number Matches：	1

电子百科

产品导航

产品型号TLV62130RGTR的概述

产品型号TLV62130RGTR的Datasheet PDF文件预览

TLV62130RGTR相关产品

TLV62130RGTR相关文章

IC37:专业IC行业平台