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  • TNY179PN图
  • 深圳市欧立现代科技有限公司

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  • 数量60000 
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  • 数量10000 
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  • 深圳市浩兴林电子有限公司

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  • 数量1012 
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  • TNY179PN
  • 数量9328 
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  • 封装DIP-8.直插 
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  • 深圳市拓亿芯电子有限公司

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  • TNY179PN
  • 数量30000 
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  • 深圳市毅创腾电子科技有限公司

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  • TNY179PN
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  • 深圳市宗天技术开发有限公司

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  • TNY179PN
  • 数量72 
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  • 数量50 
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  • 数量16680 
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  • TNY179PN
  • 数量21016 
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  • 万三科技(深圳)有限公司

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  • 数量6500000 
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  • 深圳德田科技有限公司

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产品型号TNY179PN的概述

芯片TNY179PN的概述 TNY179PN是一款由世界知名半导体公司——Power Integrations生产的集成电源管理芯片。它专为适用于各种小型电源应用而设计,特别是在低功耗、小型开关电源(SMPS)的场景中广泛使用。TNY179PN可以提供高效、紧凑的方案,适合于电源适配器、LED驱动器以及其他需要高效率和小尺寸的电源设计。该芯片采用高电压集成结构,内置了一系列保护功能,如过压保护、过流保护和短路保护,确保了系统在不同工作条件下的安全和稳定性。 TNY179PN的详细参数 TNY179PN的电气特性使其格外引人注目。该芯片的输入电压范围为85V至265V AC,能够适应全球各地的电源标准。峰值开关频率约为100kHz,具有高转换效率。这一频率的选择能够有效降低开关损耗并提高输出功率。此外,该芯片的输出功率范围通常为5W到20W,适宜多种低功耗应用。 以下是一些关键参数: -...

产品型号TNY179PN的Datasheet PDF文件预览

TNY174-180  
®
TinySwitch-LT Family  
Energy Efcient, Ofine Switcher with  
Enhanced Flexibility and Extended Power Range  
Product Highlights  
+
AC  
Input  
DC  
Output  
Lowest System Cost with Enhanced Flexibility  
650 V rating optimized for non-active PFC applications  
Simple ON/OFF control, no loop compensation needed  
Selectable current limit through BP/M capacitor value  
-
D
S
EN  
-
-
-
Higher current limit extends peak power or, in open  
frame applications, maximum continuous power  
Lower current limit improves efciency in enclosed  
adapters/chargers  
Allows optimum TinySwitch-LT choice by swapping  
devices with no other circuit redesign  
BP/M  
TinySwitch-LT  
PI-4770-073107  
Figure 1. Typical Application.  
Tight I2f parameter tolerance reduces system cost  
-
-
Maximizes MOSFET and magnetics power delivery  
Minimizes max overload power, reducing cost of  
transformer, primary clamp & secondary components  
OUTPUT POWER TABLE  
230 VAC ±15%  
85-265 VAC  
ON-time extension – extends low line regulation range/  
hold-up time to reduce input bulk capacitance  
Self-biased: no bias winding or bias components  
Frequency jittering reduces EMI lter costs  
Pin-out simplies heatsinking to the PCB  
Peak or  
Peak or  
PRODUCT3  
Adapter1 Open Adapter1 Open  
Frame2  
Frame2  
8.5 W  
11.5 W  
15 W  
TNY174PN  
TNY175PN  
TNY176PN  
TNY177PN  
TNY178PN  
TNY179PN  
TNY180PN  
6 W  
8.5 W  
10 W  
13 W  
16 W  
18 W  
20 W  
11 W  
5 W  
6 W  
15 W  
SOURCE pins are electrically quiet for low EMI  
19 W  
7 W  
Enhanced Safety and Reliability Features  
23.5 W  
28 W  
8 W  
18 W  
Accurate hysteretic thermal shutdown protection with  
automatic recovery eliminates need for manual reset  
Auto-restart delivers <3% of maximum power in short  
circuit and open loop fault conditions  
10 W  
12 W  
14 W  
21.5 W  
25 W  
32 W  
36.5 W  
28.5 W  
Output overvoltage shutdown with optional Zener  
Very low component count enhances reliability and  
enables single-sided printed circuit board layout  
High bandwidth provides fast turn on with no overshoot  
and excellent transient load response  
Table 1. Notes: 1. Minimum continuous power in a typical non-  
ventilated enclosed adapter measured at 50 °C ambient. Use of an  
external heatsink will increase power capability 2. Minimum peak  
power capability in any design or minimum continuous power in an  
open frame design (see KeyApplication Considerations). 3. Packages:  
P: DIP-8C, G: SMD-8C. See Part Ordering Information.  
Extended creepage between DRAIN and all other pins  
improves eld reliability  
EcoSmart®– Extremely Energy Efcient  
Easily meets all global energy efciency regulations  
No-load <150 mW at 265 VAC without bias winding,  
<50 mW with bias winding  
ON/OFF control provides constant efciency down to  
very light loads – ideal for mandatory CEC regulations  
Description  
TinySwitch-LTincorporatesa650VpowerMOSFET,oscillator,  
high voltage switched current source, current limit (user  
selectable) and thermal shutdown circuitry. The IC family uses  
anON/OFFcontrolschemeandoffersadesignexiblesolution  
with a low system cost and extended power capability.  
Applications  
Chargers/adapters for cell/cordless phones, PDAs, digital  
cameras, MP3/portable audio, shavers, etc.  
DVD/PVR and other low power set top decoders  
Supplies for appliances, industrial systems, metering, etc.  
August 2007  
TNY174-180  
BYPASS/  
MULTI-FUNCTION  
(BP/M)  
DRAIN  
(D)  
REGULATOR  
5.85 V  
115 μA  
FAULT  
PRESENT  
BYPASS PIN  
UNDER-VOLTAGE  
+
-
AUTO-  
RESTART  
COUNTER  
BYPASS  
CAPACITOR  
SELECT AND  
CURRENT  
LIMIT STATE  
MACHINE  
5.85 V  
4.9 V  
VILIMIT  
RESET  
CURRENT LIMIT  
COMPARATOR  
-
ENABLE  
+
JITTER  
CLOCK  
1.0 V + VT  
1.0 V  
THERMAL  
SHUTDOWN  
DC  
MAX  
OSCILLATOR  
S
R
Q
Q
ENABLE  
(EN)  
LEADING  
EDGE  
BLANKING  
OVP  
LATCH  
SOURCE  
(S)  
PI-4771-073107  
Figure 2. Functional Block Diagram.  
Pin Functional Description  
P Package (DIP-8C)  
DRAIN (D) Pin:  
This pin is the power MOSFET drain connection. It provides  
internal operating current for both startup and steady-state  
operation.  
EN  
S
S
1
2
8
7
BP/M  
BYPASS/MULTI-FUNCTION (BP/M) Pin:  
This pin has multiple functions:  
6
5
S
S
4
D
1. It is the connection point for an external bypass capacitor  
for the internally generated 5.85 V supply.  
2. It is a mode selector for the current limit value, depending  
on the value of the capacitance added. Use of a 0.1 μF  
capacitor results in the standard current limit value. Use of  
a 1 μF capacitor results in the current limit being reduced to  
that of the next smaller device size. Use of a 10 μF capacitor  
results in the current limit being increased to that of the next  
larger device size for TNY175-180.  
PI-4772-07307  
Figure 3. Pin Conguration.  
witha Zener connectedfrom the BP/Mpintoa bias winding  
supply.  
3. It provides a shutdown function. When the current into  
the bypass pin exceeds ISD, the device latches off until the  
BP/M voltage drops below 4.9 V, during a power down.  
This can be used to provide an output overvoltage function  
ENABLE (EN) Pin:  
The switching of the power MOSFET is controlled by this pin.  
MOSFET switching is terminated when a current greater than  
A
08/07  
2
TNY174-180  
a threshold current is drawn from this pin. Switching resumes  
when the current being pulled from the pin drops to less than  
a threshold current. A modulation of the threshold current  
reduces group pulsing. The threshold current is between 75  
μA and 115 μA.  
jitter is set to 1 kHz to optimize EMI reduction for both average  
and quasi-peak emissions. The frequency jitter should be  
measured with the oscilloscope triggered at the falling edge of  
the DRAIN waveform. The waveform in Figure 4 illustrates  
the frequency jitter.  
SOURCE (S) Pin:  
Enable Input and Current Limit State Machine  
This pin is internally connected to the output MOSFET source  
for high voltage power return and control circuit common.  
TheenableinputcircuitattheENpinconsistsofalowimpedance  
source follower output set at 1.2 V. The current through the  
source follower is limited to 115 μA. When the current out  
of this pin exceeds the threshold current, a low logic level  
(disable) is generated at the output of the enable circuit, until  
the current out of this pin is reduced to less than the threshold  
current. This enable circuit output is sampled at the beginning  
of each cycle on the rising edge of the clock signal. If high, the  
powerMOSFETisturnedonforthatcycle(enabled). Iflow, the  
power MOSFET remains off (disabled). Since the sampling is  
done only at the beginning of each cycle, subsequent changes  
in the EN pin voltage or current during the remainder of the  
cycle are ignored.  
TinySwitch-LT Functional  
Description  
TinySwitch-LT combines a high voltage power MOSFET  
switch with a power supply controller in one device. Unlike  
conventional PWM (pulse width modulator) controllers, it uses  
a simple ON/OFF control to regulate the output voltage.  
Thecontrollerconsistsofanoscillator,enablecircuit(senseand  
logic), current limit state machine, 5.85 V regulator, BYPASS/  
MULTI-FUNCTIONpinundervoltage,overvoltagecircuit,and  
current limit selection circuitry, over- temperature protection,  
current limit circuit, leading edge blanking, and a 700 V power  
MOSFET. TinySwitch-LT incorporates additional circuitry for  
auto-restart, adaptive switching cycle on-time extension, and  
frequency jitter. Figure 2 shows the functional block diagram  
with the most important features.  
The current limit state machine reduces the current limit by  
discrete amounts at light loads when TinySwitch-LT is likely to  
switch in the audible frequency range. The lower current limit  
raises the effective switching frequency above the audio range  
andreducesthetransformeruxdensity,includingtheassociated  
audible noise. The state machine monitors the sequence of  
enable events to determine the load condition and adjusts the  
current limit level accordingly in discrete amounts.  
Oscillator  
The typical oscillator frequency is internally set to an average  
of 132 kHz. Two signals are generated from the oscillator: the  
maximum duty cycle signal (DCMAX) and the clock signal that  
indicates the beginning of each cycle.  
Undermostoperatingconditions(exceptwhenclosetono-load),  
the low impedance of the source follower keeps the voltage  
on the EN pin from going much below 1.2 V in the disabled  
state. This improves the response time of the optocoupler that  
is usually connected to this pin.  
The oscillator incorporates circuitry that introduces a small  
amount of frequency jitter, typically 8 kHz peak-to-peak, to  
minimize EMI emission. The modulation rate of the frequency  
5.85 V Regulator and 6.4 V Shunt Voltage Clamp  
The 5.85 V regulator charges the bypass capacitor connected  
to the BYPASS pin to 5.85 V by drawing a current from the  
voltage on the DRAIN pin whenever the MOSFET is off. The  
BYPASS/MULTI-FUNCTIONpinistheinternalsupplyvoltage  
node. When the MOSFET is on, the device operates from the  
energy stored in the bypass capacitor. Extremely low power  
consumption of the internal circuitry allows TinySwitch-LT to  
operate continuously from current it takes from the DRAIN  
pin. A bypass capacitor value of 0.1 μF is sufcient for both  
high frequency decoupling and energy storage.  
600  
500  
VDRAIN  
400  
300  
200  
100  
In addition, there is a 6.4 V shunt regulator clamping the  
BYPASS/MULTI-FUNCTION pin at 6.4 V when current  
is provided to the BYPASS/MULTI-FUNCTION pin  
through an external resistor. This facilitates powering of  
TinySwitch-LT externally through a bias winding to decrease  
the no-load consumption to well below 50 mW.  
0
136 kHz  
128 kHz  
0
5
10  
Time (μs)  
Figure 4. Frequency Jitter.  
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TNY174-180  
BYPASS/MULTI-FUNCTION Pin Undervoltage  
isnormallydisabledfor2.5seconds.Theauto-restartalternately  
enables and disables the switching of the power MOSFET until  
the fault condition is removed. Figure 5 illustrates auto-restart  
circuit operation in the presence of an output short circuit.  
The BYPASS/MULTI-FUNCTION pin undervoltage circuitry  
disables the power MOSFET when the BYPASS/MULTI-  
FUNCTION pin voltage drops below 4.9 V in steady state  
operation.OncetheBYPASS/MULTI-FUNCTIONpinvoltage  
drops below 4.9 V in steady state operation, it must rise back  
to 5.85 V to enable (turn-on) the power MOSFET.  
Adaptive Switching Cycle On-Time Extension  
Adaptive switching cycle on-time extension keeps the cycle  
on until current limit is reached, instead of prematurely  
terminating after the DCMAX signal goes low. This feature  
reduces the minimum input voltage required to maintain  
regulation, extending hold-up time and minimizing the size  
of bulk capacitor required. The on-time extension is disabled  
during the startup of the power supply, until the power supply  
output reaches regulation.  
Over Temperature Protection  
Thethermalshutdowncircuitrysensesthedietemperature. The  
threshold is typically set at 142 °C with 75 °C hysteresis. When  
thedietemperaturerisesabovethisthresholdthepowerMOSFET  
is disabled and remains disabled until the die temperature falls  
by 75 °C, at which point it is re-enabled. A large hysteresis of  
75 °C (typical) is provided to prevent overheating of the PC  
board due to a continuous fault condition.  
TinySwitch-LT Operation  
Current Limit  
TinySwitch-LTdevicesoperateinthecurrentlimitmode. When  
enabled, the oscillator turns the power MOSFET on at the  
beginning of each cycle. The MOSFET is turned off when the  
current ramps up to the current limit or when the DCMAX limit is  
reached. Since the highest current limit level and frequency of  
a TinySwitch-LT design are constant, the power delivered to the  
loadisproportionaltotheprimaryinductanceofthetransformer  
and peak primary current squared. Hence, designing the supply  
involves calculating the primary inductance of the transformer  
for the maximum output power required. If the TinySwitch-LT  
is appropriately chosen for the power level, the current in the  
calculated inductance will ramp up to current limit before the  
DCMAX limit is reached.  
ThecurrentlimitcircuitsensesthecurrentinthepowerMOSFET.  
When this current exceeds the internal threshold (ILIMIT), the  
powerMOSFETisturnedofffortheremainderofthatcycle.The  
current limit state machine reduces the current limit threshold  
by discrete amounts under medium and light loads.  
The leading edge blanking circuit inhibits the current limit  
comparator for a short time (tLEB) after the power MOSFET is  
turned on. This leading edge blanking time has been set so that  
currentspikescausedbycapacitanceandsecondary-siderectier  
reverse recovery time will not cause premature termination of  
the switching pulse.  
Auto-Restart  
Enable Function  
In the event of a fault condition such as output overload, output  
short circuit, or an open loop condition, TinySwitch-LT enters  
into auto-restart operation. An internal counter clocked by the  
oscillator is reset every time the EN pin is pulled low. If the EN  
pin is not pulled low for 64 ms, the power MOSFET switching  
TinySwitch-LTsenses the EN pin to determine whether or not to  
proceed with the next switching cycle. The sequence of cycles  
is used to determine the current limit. Once a cycle is started,  
it always completes the cycle (even when the EN pin changes  
state half way through the cycle). This operation results in a  
power supply in which the output voltage ripple is determined  
by the output capacitor, amount of energy per switch cycle and  
the delay of the feedback.  
300  
200  
The EN pin signal is generated on the secondary by comparing  
the power supply output voltage with a reference voltage. The  
EN pin signal is high when the power supply output voltage is  
less than the reference voltage.  
100  
0
10  
In a typical implementation, the EN pin is driven by an  
optocoupler. The collector of the optocoupler transistor is  
connected to the EN pin and the emitter is connected to the  
SOURCEpin.TheoptocouplerLEDisconnectedinserieswith  
a Zener diode across the DC output voltage to be regulated.  
When the output voltage exceeds the target regulation voltage  
level (optocoupler LED voltage drop plus Zener voltage), the  
optocoupler LED will start to conduct, pulling the EN pin low.  
The Zener diode can be replaced by a TL431 reference circuit  
5
0
2500  
5000  
0
Time (ms)  
Figure 5. Auto-Restart Operation.  
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for improved accuracy.  
At near maximum load, TinySwitch-LT will conduct during  
nearly all of its clock cycles (Figure 6). At slightly lower load,  
it will “skip” additional cycles in order to maintain voltage  
regulation at the power supply output (Figure 7). At medium  
loads,cycleswillbeskippedandthecurrentlimitwillbereduced  
(Figure 8).At very light loads, the current limit will be reduced  
even further (Figure 9). Only a small percentage of cycles will  
occur to satisfy the power consumption of the power supply.  
ON/OFF Operation with Current Limit State Machine  
The internal clock of the TinySwitch-LT runs all the time.At the  
beginning of each clock cycle, it samples the EN pin to decide  
whether or not to implement a switch cycle, and based on the  
sequence of samples over multiple cycles, it determines the  
appropriate current limit. At high loads, the state machine sets  
the current limit to its highest value. At lighter loads, the state  
machine sets the current limit to reduced values.  
The response time of the ON/OFF control scheme is very fast  
compared to PWM control. This provides tight regulation and  
excellent transient response.  
V
EN  
Power Up/Down  
The TinySwitch-LT requires only a 0.1 μF capacitor on the  
BYPASS/MULTI-FUNCTION pin to operate with standard  
current limit. Because of its small size, the time to charge this  
capacitor is kept to an absolute minimum, typically 0.6 ms. The  
time to charge will vary in proportion to the BYPASS/MULTI-  
FUNCTIONpincapacitorvaluewhenselectingdifferentcurrent  
limits. Due to the high bandwidth of the ON/OFF feedback,  
there is no overshoot at the power supply output.  
CLOCK  
D
MAX  
I
DRAIN  
Figure 10 shows typical power up timing waveforms.  
Understartupandoverloadconditions,whentheconductiontime  
is less than 400 ns, the device reduces the switching frequency  
to maintain control of the peak drain current.  
V
DRAIN  
During power down, the power MOSFET will switch for 64  
ms after the output loses regulation.  
PI-2749-050301  
Figure 6. Operation at Near Maximum Loading.  
V
V
EN  
EN  
CLOCK  
CLOCK  
D
DC  
MAX  
MAX  
I
I
DRAIN  
DRAIN  
V
DRAIN  
V
DRAIN  
PI-2377-082305  
PI-2667-090700  
Figure 8. Operation at Medium Loading.  
Figure 7. Operation at Moderately Heavy Loading.  
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TNY174-180  
200  
100  
V
V
EN  
DC-INPUT  
0
CLOCK  
10  
D
MAX  
V
5
0
BYPASS  
I
400  
200  
0
DRAIN  
V
DRAIN  
1
2
0
Time (ms)  
V
DRAIN  
Figure 10. Power Up.  
PI-2661-072400  
200  
100  
Figure 9. Operation at Very Light Load.  
V
DC-INPUT  
Figure 11 illustrates a typical power down timing waveform.  
0
400  
300  
No bias winding is needed to provide power to the chip  
because it draws the power directly from the DRAIN pin (see  
Functional Description above). This has two main benets.  
First, for a nominal application, this eliminates the cost of a  
bias winding and associated components. Secondly, for battery  
charger applications, the current-voltage characteristic often  
allows the output voltage to fall close to zero volts while still  
delivering power. TinySwitch-LT accomplishes this without a  
forward bias winding and its many associated components. For  
applications that require very low no-load power consumption  
(50 mW), a resistor from a bias winding to the BYPASS/  
MULTI-FUNCTION pin can provide the power to the chip.  
The minimum recommended current supplied is 1 mA. The  
BYPASS/MULTI-FUNCTION pin in this case will be clamped  
at 6.4 V. This method will eliminate the power draw from the  
DRAIN pin, thereby reducing the no-load power consumption  
and improving full-load efciency.  
V
200  
100  
DRAIN  
0
0
.5  
1
Time (s)  
Figure 11. Normal Power Down Timing.  
limit of the next smaller device and a 10 μF BP/M pin capacitor  
will select a higher current limit equal to the standard current  
limit of the next larger device. The higher current limit level of  
the TNY180 is set to 850 mA typical. The TNY174 MOSFET  
does not have the capability for increased current limit so this  
feature is not available in this device.  
Current Limit Operation  
Each switching cycle is terminated when the DRAIN current  
reaches the current limit of the device. Current limit operation  
providesgoodlineripplerejectionandrelativelyconstantpower  
delivery independent of input voltage.  
BYPASS/MULTI-FUNCTION Pin Capacitor  
The BYPASS/MULTI-FUNCTION pin can use a ceramic  
capacitor as small as 0.1 μF for decoupling the internal power  
supplyofthedevice.Alargercapacitorsizecanbeusedtoadjust  
the current limit. For TNY175-180, a 1 μF BP/M pin capacitor  
will select a lower current limit equal to the standard current  
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TNY174-180  
C5  
2.2 nF  
250 VAC  
L2  
D7  
Ferrite Bead  
3.5 × 7.6 mm  
VR1  
BYV28-200  
T1  
+12 V, 1 A  
P6KE150A  
NC  
8
6
J3  
J4  
C11  
100 μF  
25 V  
C10  
1000 μF  
25 V  
D1  
1N4007  
D2  
1N4007  
R2  
1
3
100 Ω  
F1  
3.15 A  
RTN  
C4  
10 nF  
1 kV  
J1  
R1  
C1  
6.8 μF  
400 V  
C2  
22 μF  
400 V  
1 kΩ  
R7  
20 Ω  
4
85-265  
VAC  
RV1  
275 VAC  
D5  
1N4007GP  
2
5
D6  
UF4003  
J2  
D3  
1N4007  
D4  
1N4007  
VR2  
1N5255B  
28 V  
L1  
1 mH  
C6  
VR3  
BZX79-C11  
11 V  
1 μF  
60 V  
R3  
47 Ω  
1/8 W  
*R5 is optional  
R6  
390 Ω  
1/8 W  
R8*  
21 kΩ  
1%  
C7 is configurable to adjust  
U1 current limit, see circuit  
description  
U2  
PC817A  
D
EN  
BP/M  
S
S
R4  
2 kΩ  
1/8 W  
C7 †  
100 nF  
50 V  
TinySwitch-LT  
U1  
TNY178P  
PI-4773-073107  
Figure 12. TNY178P, 12 V, 1 A Universal Input Power Supply.  
LED forward drop, current will ow in the optocoupler LED.  
This will cause the transistor of the optocoupler to sink current.  
When this current exceeds the ENABLE pin threshold current  
the next switching cycle is inhibited. When the output voltage  
fallsbelowthefeedbackthreshold,aconductioncycleisallowed  
to occur and, by adjusting the number of enabled cycles, output  
regulation is maintained. As the load reduces, the number of  
enabled cycles decreases, lowering the effective switching  
frequencyandscalingswitchinglosseswithload. Thisprovides  
almost constant efciency down to very light loads, ideal for  
meeting energy efciency requirements.  
Applications Example  
The circuit shown in Figure 12 is a low cost, high efciency,  
yback power supply designed for 12 V, 1 A output from  
universal input using the TNY178.  
Thesupplyfeaturesprimarysensedoutputovervoltagelatching  
shutdown protection, high efciency (>80%), and very low no-  
load consumption (<50 mW at 265 VAC). Output regulation is  
accomplished using a simple zener reference and optocoupler  
feedback.  
The rectied and ltered input voltage is applied to the primary  
winding of T1. The other side of the transformer primary is  
driven by the integrated MOSFET in U1. Diode D5, C2, R1,  
R2, and VR1 comprise the clamp circuit, limiting the leakage  
inductance turn-off voltage spike on the DRAIN pin to a safe  
value. The use of a combination a Zener clamp and parallel  
RC optimizes both EMI and energy efciency. Resistor R2  
allows the use of a slow recovery, low cost, rectier diode by  
limiting the reverse current through D5. The selection of a  
slow diode also improves efciency and conducted EMI but  
should be a glass passivated type, with a specied recovery  
time of 2 μs.  
As the TinySwitch-LT devices are completely self-powered,  
there is no requirement for an auxiliary or bias winding on the  
transformer. However by adding a bias winding, the output  
overvoltage protection feature can be congured, protecting  
the load against open feedback loop faults.  
When an overvoltage condition occurs, such that bias voltage  
exceeds the sum ofVR2 and the BYPASS/MULTIFUNCTION  
(BP/M) pinvoltage(28V+5.85V),currentbeginstoowintothe  
BP/M pin. When this current exceeds ISD the internal latching  
shutdown circuit in TinySwitch-LT is activated. This condition  
is reset when the BP/M pin voltage drops below 2.6 V after  
removal of the AC input. In the example shown, on opening  
the loop, the OVP trips at an output of 17 V.  
The output voltage is regulated by the Zener diode VR3. When  
theoutputvoltageexceedsthesumoftheZenerandoptocoupler  
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TNY174-180  
For lower no-load input power consumption, the bias winding  
may also be used to supply the TinySwitch-LT device. Resistor  
R8 feeds current into the BP/M pin, inhibiting the internal high  
voltage current source that normally maintains the BP/M pin  
capacitor voltage (C7) during the internal MOSFET off time.  
This reduces the no-load consumption of this design from  
140 mW to 40 mW at 265 VAC.  
1. The minimum DC input voltage is 100 V or higher for  
85 VAC input, or 220 V or higher for 230 VAC input or  
115 VAC with a voltage doubler. The value of the input  
capacitance should be sized to meet these criteria for AC  
input designs.  
2. Efciency of 75%.  
3. Minimum data sheet value of I2f.  
4. Transformer primary inductance tolerance of ±10%.  
5. Reected output voltage (VOR) of 135 V.  
6. Voltage only output of 12 V with a fast PN rectier diode.  
7. Continuous conduction mode operation with transient KP*  
value of 0.25.  
8. Increased current limit is selected for peak and open frame  
power columns and standard current limit for adapter  
columns.  
9. The part is board mounted with SOURCE pins soldered to  
a sufcient area of copper and/or a heatsink is used to keep  
the SOURCE pin temperature at or below 110 °C.  
10. Ambient temperature of 50 °C for open frame designs and  
40 °C for sealed adapters.  
In addition to the simple input pi lter (C1, L1, C2) for  
differential mode EMI, this design makes use of E-Shield™  
shielding techniques in the transformer to reduce common  
mode EMI displacement currents, and R2 and C4 as a damping  
network to reduce high frequency transformer ringing. These  
techniques, combined with the frequency jitter of TNY178,  
give excellent conducted and radiated EMI performance with  
this design achieving >12 dBμV of margin to EN55022 Class  
B conducted EMI limits.  
For design exibility the value of C7 can be selected to pick one  
of the 3 current limits options in U1. This allows the designer  
to select the current limit appropriate for the application.  
*Below a value of 1, KP is the ratio of ripple to peak primary  
current. To prevent reduced power capability due to premature  
termination of switching cycles a transient KP limit of 0.25  
Standardcurrentlimit(ILIMIT)isselectedwitha0.1μFBP/M  
pin capacitor and is the normal choice for typical enclosed  
adapter applications.  
When a 1 μF BP/M pin capacitor is used, the current  
limit is reduced (ILIMITred or ILIMIT-1) offering reduced RMS  
device currents and therefore improved efciency, but at  
the expense of maximum power capability. This is ideal  
for thermally challenging designs where dissipation must  
be minimized.  
When a 10 μF BP/M pin capacitor is used, the current  
limit is increased (ILIMITinc or ILIMIT+1), extending the power  
capability for applications requiring higher peak power or  
continuous power where the thermal conditions allow.  
is recommended. This prevents the initial current limit (IINIT  
from being exceeded at MOSFET turn on.  
)
For reference, Table 2 provides the minimum practical power  
deliveredfromeachfamilymemberatthethreeselectablecurrent  
limitvalues. Thisassumesopenframeoperation(notthermally  
limited) and otherwise the same conditions as listed above.  
These numbers are useful to identify the correct current limit  
to select for a given device and output power requirement.  
Overvoltage Protection  
The output overvoltage protection provided by TinySwitch-LT  
uses an internal latch that is triggered by a threshold current  
of approximately 5.5 mA into the BP/M pin. In addition to an  
internal lter, the BP/M pin capacitor forms an external lter  
providing noise immunity from inadvertent triggering. For the  
bypass capacitor to be effective as a high frequency lter, the  
capacitorshouldbelocatedascloseaspossibletotheSOURCE  
and BP/M pins of the device.  
Furtherexibilitycomesfromthecurrentlimitsbetweenadjacent  
TinySwitch-LTfamilymembersbeingcompatible. Thereduced  
current limit of a given device is equal to the standard current  
limitofthenextsmallerdeviceandtheincreasedcurrentlimitis  
equal to the standard current limit of the next larger device.  
Key Application Considerations  
TinySwitch-LT Design Considerations  
For best performance of the OVP function, it is recommended  
thatarelativelyhighbiaswindingvoltageisused,intherangeof  
15V-30V. Thisminimizestheerrorvoltageonthebiaswinding  
due to leakage inductance and also ensures adequate voltage  
during no-load operation from which to supply the BP/M pin  
for reduced no-load consumption.  
Output Power Table  
The data sheet output power table (Table 1) represents the  
minimum practical continuous output power level that can be  
obtained under the following assumed conditions:  
Selecting the Zener diode voltage to be approximately 6 V  
above the bias winding voltage (28 V for 22 V bias winding)  
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TNY174-180  
OUTPUT POWER TABLE  
230 VAC 15%  
85-265 VAC  
PRODUCT  
ILIMIT-1  
ILIMIT  
ILIMIT+1  
ILIMIT-1  
ILIMIT  
ILIMIT+1  
TNY174PN  
TNY175PN  
TNY176PN  
TNY177PN  
TNY178PN  
TNY179PN  
TNY180PN  
9
10.9  
12  
9.1  
15.1  
19.4  
23.7  
28  
7.1  
8.4  
8.5  
9.3  
7.1  
10.8  
11.8  
15.1  
19.4  
23.7  
28  
11.8  
15.1  
18.5  
21.8  
25.2  
28.5  
15.3  
19.6  
24  
9.2  
11.9  
15.3  
18.6  
22  
11.8  
15.1  
18.5  
21.8  
28.4  
32.7  
32.2  
36.6  
25.4  
Table 2. Minimum Practical Power at Three Selectable Current Limit Levels.  
gives good OVP performance for most designs, but can be  
adjusted to compensate for variations in leakage inductance.  
Adding additional ltering can be achieved by inserting a low  
value (10 Ω to 47 Ω) resistor in series with the bias winding  
diode and/or the OVP Zener as shown by R7 and R3 in  
Figure 12. The resistor in series with the OVPZener also limits  
the maximum current into the BP/M pin.  
in clamp circuits, may also generate audio noise. If this is the  
case, try replacing them with a capacitor having a different  
dielectric or construction, for example a lm type.  
TinySwitch-LT Layout Considerations  
Layout  
See Figure 13 for a recommended circuit board layout for  
Reducing No-load Consumption  
TinySwitch-LT.  
AsTinySwitch-LTisself-poweredfromtheBP/Mpincapacitor,  
there is no need for an auxillary or bias winding to be provided  
onthetransformerforthispurpose. Typicalno-loadconsumption  
whenself-poweredis<150mWat265VACinput. Theaddition  
ofabiaswindingcanreducethisdownto<50mWbysupplying  
theTinySwitch-LTfromthelowerbiasvoltageandinhibitingthe  
internal high voltage current source. To achieve this, select the  
value of the resistor (R8 in Figure 12) to provide the data sheet  
DRAIN supply current. In practice, due to the reduction of the  
bias voltage at low load, start with a value equal to 40% greater  
thanthedatasheetmaximumcurrent,andthenincreasethevalue  
of the resistor to give the lowest no-load consumption.  
Single Point Grounding  
Useasinglepointgroundconnectionfromtheinputltercapacitor  
to the area of copper connected to the SOURCE pins.  
Bypass Capacitor (CBP)  
The BP/M pin capacitor should be located as near as possible  
to the BP/M and SOURCE pins.  
EN Pin  
Keep traces connected to the EN pin short and, as far as is  
practical, away from all other traces and nodes above source  
potentialincluding,butnotlimitedto,theBYPASSandDRAIN  
pins.  
Audible Noise  
The cycle skipping mode of operation used in TinySwitch-LT  
can generate audio frequency components in the transformer.  
To limit this audible noise generation the transformer should  
be designed such that the peak core ux density is below  
3000 Gauss (300 mT). Following this guideline and using the  
standard transformer production technique of dip varnishing  
practically eliminates audible noise. Vacuum impregnation  
of the transformer should not be used due to the high primary  
capacitanceandincreasedlossesthatresult.Higheruxdensities  
are possible, however careful evaluation of the audible noise  
performance should be made using production transformer  
samples before approving the design.  
Primary Loop Area  
The area of the primary loop that connects the input lter  
capacitor, transformer primary and TinySwitch-LT together  
should be kept as small as possible.  
Primary Clamp Circuit  
Aclamp is used to limit peak voltage on the DRAIN pin at turn  
off. This can be achieved by using an RCD clamp or a Zener  
(~200 V) and diode clamp across the primary winding. In all  
cases, to minimize EMI, care should be taken to minimize the  
circuit path from the clamp components to the transformer and  
TinySwitch-LT.  
Ceramic capacitors that use dielectrics such as Z5U, when used  
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TNY174-180  
Maximize hatched copper  
Safety Spacing  
areas (  
) for optimum  
heatsinking  
Y1-  
Capacitor  
Output  
Rectifier  
+
Output Filter  
Capacitor  
HV  
-
Input Filter Capacitor  
PRI  
T
r
a
n
s
f
o
r
m
e
r
SEC  
BIAS  
PRI  
D
S
S
S
S
BP/M  
BIAS  
TOP VIEW  
CBP  
EN  
Opto-  
coupler  
DC  
-
+
OUT  
PI-4779-073107  
Figure 13. Recommended Circuit Board Layout for TinySwitch-LT with Undervoltage Lock Out Resistor.  
Thermal Considerations  
secondary winding, the output diode and the output lter  
capacitor, should be minimized. In addition, sufcient copper  
area should be provided at the anode and cathode terminals  
of the diode for heatsinking. A larger area is preferred at the  
quiet cathode terminal. A large anode area can increase high  
frequency radiated EMI.  
The four SOURCE pins are internally connected to the IC lead  
frameandprovidethemainpathtoremoveheatfromthedevice.  
ThereforealltheSOURCEpinsshouldbeconnectedtoacopper  
area underneath the TinySwitch-LT to act not only as a single  
point ground, but also as a heatsink. As this area is connected  
to the quiet source node, this area should be maximized for  
good heatsinking. Similarly for axial output diodes, maximize  
the PCB area connected to the cathode.  
PC Board Leakage Currents  
TinySwitch-LT is designed to optimize energy efciency across  
thepowerrangeandparticularlyinstandby/no-loadconditions.  
Current consumption has therefore been minimized to achieve  
this performance. The EN pin for example operates with very  
low threshold current levels and it is therefore recommended  
to limit parasitic currents into and out of the EN pin to levels  
below 1 μA.  
Y-Capacitor  
The placement of the Y-capacitor should be directly from the  
primary input lter capacitor positive terminal to the common/  
return terminal of the transformer secondary. Such a placement  
will route high magnitude common mode surge currents away  
from the TinySwitch-LT device. Note – if an input π (C, L, C)  
EMI lter is used then the inductor in the lter should be placed  
between the negative terminals of the input lter capacitors.  
ParasiticleakagecurrentsintotheENpinarenormallywellbelow  
this 1μA level when PC board assembly is in a well controlled  
productionfacility. However,highhumidityconditionstogether  
with board and/or package contamination, either from no-clean  
ux or other contaminants, can reduce the surface resistivity  
enough to allow parasitic currents >1 μA to ow into the EN  
pin. Thesecurrentscanowfromhighervoltageexposedsolder  
pads close to the EN pin such as the BP/M pin solder pad.  
Optocoupler  
Place the optocoupler physically close to the TinySwitch-LT  
to minimizing the primary-side trace lengths. Keep the high  
current, high voltage drain and clamp traces away from the  
optocoupler to prevent noise pick up.  
Output Diode  
If the contamination levels in the PC board assembly facility  
areunknown, theapplicationisopenframeoroperatesinahigh  
For best performance, the area of the loop connecting the  
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TNY174-180  
pollution degree environment, then an optional 390 kΩ resistor  
should be added from EN pin to SOURCE pin to ensure that  
the parasitic leakage current into the EN pin is low.  
Note that typical values for surface insulation resistance (SIR)  
whereno-cleanuxhasbeenappliedaccordingtothesuppliers’  
guidelines are >>10 MΩ and do not cause this issue.  
Quick Design Checklist  
As with any power supply design, all TinySwitch-LT designs  
should be veried on the bench to make sure that component  
specicationsarenotexceededunderworstcaseconditions. The  
following minimum set of tests is strongly recommended:  
1. Maximum drain voltage – Verify that the worst case VDS  
does not exceed 650 V at highest input voltage and peak  
(overload) output power.  
2. Maximumdraincurrent–Atmaximumambienttemperature,  
maximum input voltage and peak output (overload) power,  
verify drain current waveforms for any signs of transformer  
saturation and excessive leading edge current spikes at  
startup. Repeatundersteadystateconditionsandverifythat  
the leading edge current spike event is below ILIMIT(Min) at the  
endofthetLEB(Min). Underallconditions, themaximumdrain  
current should be below the specied absolute maximum  
ratings.  
3. Thermal Check – At specied maximum output power,  
minimuminputvoltageandmaximumambienttemperature,  
verify that the temperature specications are not exceeded  
for TinySwitch-LT, transformer, output diode, and output  
capacitors. Enough thermal margin should be allowed for  
part-to-part variation of the RDS(ON) of TinySwitch-LT as  
speciedinthedatasheet. Underlowline,maximumpower,  
a maximum TinySwitch-LT SOURCE pin temperature of  
110 °C is recommended to allow for these variations.  
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TNY174-180  
ABSOLUTE MAXIMUM RATINGS(1,5)  
DRAIN Voltage ................................................-0.3 V to 650 V Lead Temperature(4) ....................................................... 260 °C  
DRAIN Peak Current: TNY174.......................400 (750) mA(2)  
TNY175.....................560 (1050) mA(2) Notes:  
TNY176.....................720 (1350) mA(2) 1. All voltages referenced to SOURCE, TA = 25 °C.  
TNY177.....................880 (1650) mA(2) 2. The higher peak DRAIN current is allowed while the  
TNY178...................1040 (1950) mA(2)  
DRAIN voltage is simultaneously less than 400 V.  
TNY179.................. 1200 (2250) mA(2) 3. Normally limited by internal circuitry.  
TNY180.................. 1360 (2550) mA(2) 4. 1/16 in. from case for 5 seconds.  
EN Voltage .......................................................... -0.3 V to 9 V 5. Maximum ratings specied may be applied one at a time,  
EN Current .................................................................. 100 mA  
BP/M Voltage ......................................................-0.3 V to 9 V  
Storage Temperature ......................................-65 °C to 150 °C  
Operating Junction Temperature(3) .................-40 °C to 150 °C  
without causing permanent damage to the product.  
Exposure to Absolute Maximum Rating conditions for  
extended periods of time may affect product reliability.  
THERMAL IMPEDANCE  
Notes:  
Thermal Impedance: P Package:  
(θJA) ........................... 70 °C/W(2); 60 °C/W(3)  
(θJC)(1) ............................................... 11 °C/W  
1. Measured on the SOURCE pin close to plastic interface.  
2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.  
3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.  
Conditions  
SOURCE = 0 V; TJ = -40 to 125 °C  
See Figure 14  
Parameter  
Symbol  
Min  
Typ  
Max  
Units  
(Unless Otherwise Specied)  
CONTROL FUNCTIONS  
Average  
124  
132  
8
140  
Output Frequency  
fOSC  
TJ = 25 °C  
See Figure 4  
kHz  
%
in Standard Mode  
Peak-to-peak Jitter  
Maximum Duty  
DCMAX  
Cycle  
S1 Open  
62  
65  
EN Pin Upper  
IDIS  
-150  
-115  
-90  
μA  
Turnoff Threshold  
Current  
IEN = 25 μA  
IEN = -25 μA  
1.8  
0.8  
2.2  
1.2  
2.6  
1.6  
EN Pin  
Voltage  
VEN  
V
EN Current > IDIS (MOSFET Not  
Switching) See Note A  
IS1  
290  
μA  
TNY174PN  
TNY175PN  
275  
295  
310  
365  
445  
510  
630  
360  
400  
430  
460  
540  
640  
760  
DRAIN Supply  
Current  
EN Open (MOS-  
FET  
TNY176PN  
TNY177PN  
TNY178PN  
TNY179PN  
TNY180PN  
IS2  
μA  
Switching at fOSC  
)
See Note B  
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TNY174-180  
Conditions  
SOURCE = 0 V; TJ = -40 to 125 °C  
See Figure 14  
Parameter  
Symbol  
Min  
Typ  
Max  
Units  
(Unless Otherwise Specied)  
CONTROL FUNCTIONS (cont.)  
TNY174  
TNY175-179  
TNY180  
-6  
-3.8  
-5.4  
-6.8  
-2.3  
-3.5  
-4.6  
5.85  
-1.8  
-2.5  
-3.9  
-1  
VBP/M = 0 V,  
TJ = 25 °C  
See Note C, D  
ICH1  
-8.3  
-9.7  
-4.1  
-5  
BP/M Pin Charge  
Current  
mA  
TNY174  
VBP/M = 4 V,  
TJ = 25 °C  
See Note C, D  
ICH2  
TNY175-179  
TNY180  
-1.5  
-2.1  
6.15  
-6.6  
5.6  
VBP/M  
See Note C  
V
V
BP/M Pin Voltage  
BP/M Pin Voltage  
Hysteresis  
VBP/MH  
0.80  
6.0  
0.95  
6.4  
1.20  
6.7  
BP/M Pin Shunt  
Voltage  
VSHUNT  
IBP = 2 mA  
V
CIRCUIT PROTECTION  
di/dt = 50 mA/μs  
TJ = 25 °C  
TNY174PN  
TNY175PN  
TNY176PN  
TNY177PN  
233  
256  
326  
419  
250  
275  
350  
450  
267  
294  
374  
481  
See Note E  
di/dt = 55 mA/μs  
TJ = 25 °C  
See Note E  
di/dt = 70 mA/μs  
TJ = 25 °C  
See Note E  
Standard Current  
Limit (BP/M  
di/dt = 90 mA/μs  
TJ = 25 °C  
ILIMIT  
mA  
Capacitor =  
0.1 μF)  
See Note E  
di/dt = 110 mA/μs  
TJ = 25 °C  
See Note D  
TNY178PN  
TNY179PN  
TNY180PN  
512  
605  
698  
550  
650  
750  
588  
695  
802  
See Note E  
di/dt = 130 mA/μs  
TJ = 25 °C  
See Note E  
di/dt = 150 mA/μs  
TJ = 25 °C  
See Note E  
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TNY174-180  
Parameter  
Conditions  
SOURCE = 0 V; TJ = -40 to 125 °C  
See Figure 14  
Symbol  
Min  
Typ  
Max  
Units  
(Unless Otherwise Specied)  
CIRCUIT PROTECTION (cont.)  
di/dt = 50 mA/μs  
TJ = 25 °C  
TNY174PN  
TNY175PN  
TNY176PN  
TNY177PN  
TNY178PN  
196  
233  
256  
326  
419  
210  
250  
275  
350  
450  
233  
277  
305  
388  
499  
See Note E  
di/dt = 55 mA/μs  
TJ = 25 °C  
See Note E  
di/dt = 70 mA/μs  
TJ = 25 °C  
See Notes E  
Reduced Current  
Limit (BP/M  
Capacitor = 1 μF)  
See Note D  
di/dt = 90 mA/μs  
TJ = 25 °C  
ILIMITred  
mA  
di/dt = 110 mA/μs  
TJ = 25 °C  
See Notes E  
di/dt = 130 mA/μs  
TJ = 25 °C  
TNY179PN  
TNY180P  
512  
605  
196  
326  
419  
550  
650  
210  
350  
450  
610  
721  
233  
388  
499  
See Notes E  
di/dt = 150 mA/μs  
TJ = 25 °C  
See Notes E  
di/dt = 50 mA/μs  
TJ = 25 °C  
See Notes E, F  
TNY174PN  
TNY175PN  
TNY176PN  
di/dt = 55 mA/μs  
TJ = 25 °C  
See Notes E  
di/dt = 70 mA/μs  
TJ = 25 °C  
See Notes E  
Increased Current  
Limit (BP/M  
Capacitor = 10 μF)  
See Note D  
di/dt = 90 mA/μs  
TJ = 25 °C  
ILIMITinc  
mA  
TNY177PN  
TNY178PN  
TNY179PN  
TNY180PN  
512  
605  
698  
791  
550  
650  
750  
850  
610  
721  
833  
943  
See Notes E  
di/dt = 110 mA/μs  
TJ = 25 °C  
See Notes E  
di/dt = 130 mA/μs  
TJ = 25 °C  
See Notes E  
di/dt = 150 mA/μs  
TJ = 25 °C  
See Notes E  
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TNY174-180  
Conditions  
SOURCE = 0 V; TJ = -40 to 125 °C  
See Figure 14  
Parameter  
Symbol  
Min  
Typ  
Max  
Units  
(Unless Otherwise Specied)  
CIRCUIT PROTECTION (cont.)  
Standard Current  
0.9 ×  
I2f  
1.12 ×  
I2f  
I2f  
2
Limit, I2f = ILIMIT(TYP)  
TNY174-180PN  
× fOSC(TYP)  
Reduced Current  
Limit, I2f =  
I2f  
A2Hz  
0.9 ×  
I2f  
1.16 ×  
I2f  
I2f  
I2f  
Power Coefcient  
TNY174-180PN  
TNY174-180PN  
2
ILIMITred(TYP)  
× fOSC(TYP)  
Increased Current  
Limit, I2f = ILIMITinc(TYP)  
× fOSC(TYP)  
0.9 ×  
I2f  
1.16 ×  
I2f  
2
See Figure 19  
TJ = 25 °C, See Note G  
0.75 ×  
ILIMIT(MIN)  
IINIT  
tLEB  
tILD  
mA  
ns  
Initial Current Limit  
Leading Edge  
Blanking Time  
TJ = 25 °C  
See Note G  
170  
135  
215  
150  
Current Limit  
Delay  
TJ = 25 °C  
See Note G, H  
ns  
Thermal Shut-  
down Temperature  
TSD  
142  
75  
150  
°C  
°C  
Thermal Shut-  
down Hysteresis  
TSDH  
BP/M Pin Shut-  
down Threshold  
Current  
ISD  
4
6.5  
2.6  
9
mA  
V
BP/M Pin Power  
up Reset Thresh-  
old Voltage  
VBP/M(RESET)  
1.6  
3.6  
OUTPUT  
TJ = 25 °C  
28  
42  
19  
29  
14  
21  
32  
48  
22  
33  
16  
24  
TNY174PN  
ID = 25 mA  
TJ = 100 °C  
TJ = 25 °C  
TJ = 100 °C  
TJ = 25 °C  
TJ = 100 °C  
ON-State  
Resistance  
TNY175PN  
ID = 28 mA  
RDS(ON)  
Ω
TNY176PN  
ID = 35 mA  
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TNY174-180  
Conditions  
SOURCE = 0 V; TJ = -40 to 125 °C  
See Figure 14  
Parameter  
Symbol  
Min  
Typ  
Max  
Units  
(Unless Otherwise Specied)  
OUTPUT (cont.)  
TJ = 25 °C  
TJ = 100 °C  
TJ = 25 °C  
TJ = 100 °C  
TJ = 25 °C  
TJ = 100 °C  
TJ = 25 °C  
TJ = 100 °C  
7.8  
11.7  
5.2  
7.8  
3.9  
5.8  
2.6  
3.9  
9.0  
13.5  
6.0  
9.0  
4.5  
6.7  
3.0  
4.5  
TNY177PN  
ID = 45 mA  
TNY178PN  
ID = 55 mA  
ON-State  
Resistance  
RDS(ON)  
Ω
TNY179PN  
ID = 65 mA  
TNY180PN  
ID = 75 mA  
VBP/M = 6.2 V  
TNY174-176  
TNY177-178  
TNY179-180  
50  
VEN = 0 V  
VDS = 520 V  
TJ = 125 °C  
See Note I  
IDSS1  
100  
200  
μA  
OFF-State Drain  
Leakage Current  
VDS = 375 V,  
TJ = 50 °C  
See Note G, I  
VBP/M = 6.2 V  
VEN = 0 V  
IDSS2  
15  
Breakdown  
Voltage  
VBP = 6.2 V, VEN = 0 V,  
See Note J, TJ = 25 °C  
BVDSS  
650  
50  
V
V
DRAIN Supply  
Voltage  
Auto-Restart  
ON-Time at fOSC  
TJ = 25 °C  
tAR  
64  
3
ms  
%
See Note K  
Auto-Restart  
Duty Cycle  
DCAR  
TJ = 25 °C  
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TNY174-180  
NOTES:  
A. IS1 is an accurate estimate of device controller current consumption at no-load, since operating frequency is so  
low under these conditions. Total device consumption at no-load is the sum of IS1 and IDSS2  
.
B Since the output MOSFET is switching, it is difcult to isolate the switching current from the supply current at the  
DRAIN. An alternative is to measure the BP/M pin current at 6.1 V.  
C. BP/M pin is not intended for sourcing supply current to external circuitry.  
D. To ensure correct current limit it is recommended that nominal 0.1 μF / 1 μF / 10 μF capacitors are used. In  
addition, the BP/M capacitor value tolerance should be equal or better than indicated below across the ambient  
temperature range of the target application. The minimum and maximum capacitor values are guaranteed by  
characterization.  
Tolerance Relative to Nominal  
Nominal BP/M  
Pin Cap Value  
Capacitor Value  
Min  
MAX  
+100%  
+100%  
NA  
0.1 μF  
1 μF  
-60%  
-50%  
-50%  
10 μF  
E. For current limit at other di/dt values, refer to Figure 21.  
F. TNY174 does not set an increased current limit value, but with a 10 μF BP/M pin capacitor the current limit is the  
same as with a 1 μF BP/M pin capacitor (reduced current limit value).  
G. This parameter is derived from characterization.  
H. This parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the ILIMIT  
specication.  
I. IDSS1 is the worst case OFF state leakage specication at 80% of BVDSS and maximum operating junction  
temperature. IDSS2 is a typical specication under worst case application conditions (rectied 265 VAC) for no-load  
consumption calculations.  
J. Breakdown voltage may be checked against minimum BVDSS specication by ramping the DRAIN pin voltage up  
to but not exceeding minimum BVDSS  
.
K. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to  
frequency).  
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TNY174-180  
470 Ω  
5 W  
S2  
470 Ω  
S
S
D
S1  
S
S
BP/M  
EN  
50 V  
10 V  
0.1 μF  
NOTE: This test circuit is not applicable for current limit or output characteristic measurements.  
PI-4774-073107  
Figure 14. General Test Circuit.  
DC  
(internal signal)  
MAX  
t
P
EN  
t
EN  
V
DRAIN  
1
tP  
=
fOSC  
PI-4780-073107  
Figure 16. Output Enable Timing.  
Figure 15. Duty Cycle Measurement.  
0.8  
Figure 17. Current Limit Envelope.  
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TNY174-180  
Typical Performance Characteristics  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
1.1  
1.0  
0.9  
0
-50 -25  
0
25  
50 75 100 125  
-50 -25  
0
25 50 75 100 125 150  
Junction Temperature (°C)  
Junction Temperature (°C)  
Figure 19. Frequency vs. Temperature.  
Figure 18. Breakdown vs. Temperature.  
1.2  
1
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.8  
Normalized  
di/dt = 1  
TNY174  
TNY175  
TNY176  
TNY177  
TNY178 110 mA/μs  
TNY179 130 mA/μs  
TNY180 150 mA/μs  
50 mA/μs  
55 mA/μs  
70 mA/μs  
90 mA/μs  
0.6  
0.4  
0.2  
Note: For the  
normalized current  
limit value, use the  
typical current limit  
specified for the  
appropriate BP/M  
capacitor.  
0
0
-50  
0
50  
100  
150  
1
2
3
4
Temperature (°C)  
Normalized di/dt  
Figure 20. Standard Current Limit vs. Temperature.  
Figure 21. Current Limit vs. di/dt.  
300  
1000  
Scaling Factors:  
TNY174 1.0  
250  
TNY175 1.5  
TNY176 2.0  
TNY177 3.5  
TNY178 5.5  
TNY179 7.3  
200  
100  
Scaling Factors:  
TNY174 1.0  
TNY175 1.5  
TNY176 2.0  
TNY177 3.5  
TNY178 5.5  
TNY179 7.3  
TNY180 11  
TNY180 11  
150  
100  
10  
1
TCASE=25 °C  
50  
T
CASE=100 °C  
0
0
2
4
6
8
10  
0
100 200 300 400 500 600  
DRAIN Voltage (V)  
Figure 22. Output Characteristic.  
Drain Voltage (V)  
Figure 23. COSS vs. Drain Voltage.  
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TNY174-180  
Typical Performance Characteristics (cont.)  
50  
Scaling Factors:  
TNY174 1.0  
40  
TNY175 1.5  
TNY176 2.0  
TNY177 3.5  
TNY178 5.5  
TNY179 7.3  
TNY180 11  
30  
20  
10  
0
0
200  
400  
600  
DRAIN Voltage (V)  
Figure 24. Drain Capacitance Power.  
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TNY174-180  
PART ORDERING INFORMATION  
TinySwitch-LT Product Family  
Series Number  
Package Identier  
P
Plastic DIP-8C  
Lead Finish  
Pure Matte Tin (Pb-Free)  
N
TNY 178 P N  
DIP-8C  
D S .004 (.10)  
Notes:  
-E-  
1. Package dimensions conform to JEDEC specification  
MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)  
package with .300 inch row spacing.  
2. Controlling dimensions are inches. Millimeter sizes are  
shown in parentheses.  
.240 (6.10)  
.260 (6.60)  
3. Dimensions shown do not include mold flash or other  
protrusions. Mold flash or protrusions shall not exceed  
.006 (.15) on any side.  
4. Pin locations start with Pin 1, and continue counter-clock-  
wise to Pin 8 when viewed from the top. The notch and/or  
dimple are aids in locating Pin 1. Pin 3 is omitted.  
5. Minimum metal to metal spacing at the package body for  
the omitted lead location is .137 inch (3.48 mm).  
6. Lead width measured at package body.  
Pin 1  
-D-  
.367 (9.32)  
.387 (9.83)  
7. Lead spacing measured with the leads constrained to be  
perpendicular to plane T.  
.057 (1.45)  
.068 (1.73)  
(NOTE 6)  
.125 (3.18)  
.145 (3.68)  
.015 (.38)  
MINIMUM  
-T-  
SEATING  
PLANE  
.008 (.20)  
.015 (.38)  
.120 (3.05)  
.140 (3.56)  
.300 (7.62) BSC  
(NOTE 7)  
.100 (2.54) BSC  
.048 (1.22)  
.053 (1.35)  
.137 (3.48)  
MINIMUM  
P08C  
.300 (7.62)  
.390 (9.91)  
.014 (.36)  
.022 (.56)  
T E D S .010 (.25) M  
PI-3933-100504  
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TNY174-180  
Revision Notes  
Date  
A
Initial Release  
08/07  
For the latest updates, visit our website: www.powerint.com  
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume  
any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY  
DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A  
PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.  
PATENT INFORMATION  
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S.  
and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations’ patents  
may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm.  
LIFE SUPPORT POLICY  
POWER INTEGRATIONS’ PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS  
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:  
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform,  
when properly used in accordance with instructions for use, can be reasonably expected to result in signicant injury or death to the user.  
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or effectiveness.  
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, Clampless, EcoSmart, E-Shield,  
Filterfuse, StackFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their  
respective companies. ©Copyright 2006, Power Integrations, Inc.  
Power Integrations Worldwide Sales Support Locations  
WORLD HEADQUARTERS  
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San Jose, CA 95138, USA.  
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ken, Japan 222-0033  
Phone: +81-45-471-1021  
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Phone: +91-80-41138020  
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UNITED KINGDOM  
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East Street, Farnham  
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Phone: +44 (0) 1252-730-140  
Fax: +44 (0) 1252-727-689  
e-mail: eurosales@powerint.com  
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Seoul, 135-728, Korea  
Phone: +82-2-2016-6610  
Fax: +82-2-2016-6630  
e-mail: koreasales@powerint.com  
ITALY  
CHINA (SHENZHEN)  
Via De Amicis 2  
SINGAPORE  
APPLICATIONS HOTLINE  
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Electronics Science & Technology Bldg.  
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Fax: +39-028-928-6009  
e-mail: eurosales@powerint.com  
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Phone: +65-6358-2160  
Fax: +65-6358-2015  
e-mail: singaporesales@powerint.com  
World Wide +1-408-414-9660  
APPLICATIONS FAX  
World Wide +1-408-414-9760  
China, 518031  
Phone: +86-755-8379-3243  
Fax: +86-755-8379-5828  
e-mail: chinasales@powerint.com  
A
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配单直通车
TNY253G产品参数
型号:TNY253G
是否无铅: 含铅
是否Rohs认证: 不符合
生命周期:Obsolete
IHS 制造商:POWER INTEGRATIONS INC
零件包装代码:SOIC
包装说明:SOP, GWDIP8,.4
针数:8
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:8.54
Is Samacsys:N
模拟集成电路 - 其他类型:SWITCHING REGULATOR
JESD-30 代码:R-PDSO-G8
JESD-609代码:e0
长度:9.59 mm
湿度敏感等级:4
功能数量:1
端子数量:8
最高工作温度:125 °C
最低工作温度:-40 °C
最大输出电流:0.4 A
封装主体材料:PLASTIC/EPOXY
封装代码:SOP
封装等效代码:GWDIP8,.4
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified
座面最大高度:3.73 mm
子类别:Power Management Circuits
最大供电电流 (Isup):0.38 mA
表面贴装:YES
切换器配置:SINGLE
最大切换频率:48 kHz
温度等级:AUTOMOTIVE
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子节距:2.54 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.35 mm
Base Number Matches:1
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