TPA6205现货热卖使用介绍供应商报价哪里找芯片批发报价-中国IC网-芯三七

TPA6205A1

ZQV

DRB

DGN

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SLOS490A–JULY 2006–REVISED AUGUST 2006

1.25-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER WITH 1.8-V INPUT

LOGIC THRESHOLDS

FEATURES

APPLICATIONS

•

Designed for Wireless Handsets, PDAs, and

other mobile devices

•

1.25 W Into 8Ω From a 5-V Supply at

THD = 1% (Typical)

•

Compatible with Low Power (1.8V Logic) I/O

Threshold control signals

•

Shutdown Pin has 1.8V Compatible

Thresholds

•

Low Supply Current: 1.7mA Typical

Shutdown Current < 10µA

DESCRIPTION

The TPA6205A1 is a 1.25-W mono fully differential

amplifier designed to drive a speaker with at least

8-Ω impedance while consuming less than 37 mm²

(ZQV package option) total printed-circuit board

(PCB) area in most applications. This device

operates from 2.5 V to 5.5 V, drawing only 1.7 mA of

quiescent supply current. The TPA6205A1 is

available in the space-saving 2 mm x 2 mm

MicroStar Junior™ BGA package, and the space

saving 3 mm x 3 mm QFN (DRB) package.

Only Five External Components

– Improved PSRR (90 dB) and Wide Supply

Voltage (2.5V to 5.5V) for Direct Battery

Operation

– Fully Differential Design Reduces RF

Rectification

– Improved CMRR Eliminates Two Input

Coupling Capacitors

– C_(BYPASS)Is Optional Due to Fully

Differential Design and High PSRR

Features like 85-dB PSRR from 90 Hz to 5 kHz,

improved RF-rectification immunity, and small PCB

area makes the TPA6205A1 ideal for wireless

handsets. A fast start-up time of 4 µs with minimal

pop makes the TPA6205A1 ideal for PDA

applications.

•

Available in 3 mm x 3 mm QFN Package

(DRB)

Available in an 8-Pin PowerPAD™ MSOP

(DGN)

Avaliable in a 2 mm x 2 mm MicroStar

Junior™ BGA Package (ZQV)

APPLICATION CIRCUIT

Actual Solution Size

V

DD

R

F

To Battery

R

F

C

s

R

I

-

IN-

C

V

_

+

O+

S

(1)

C

B

In From

DAC

5,25 mm

R

I

V

O-

+

IN+

R

I

R

I

R

F

GND

SHUTDOWN

Bias

Circuitry

R

F

6,9 mm

C _BYPASS

(

)

(Optional)

Applies to the ZQV Packages Only

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD, MicroStar Junior are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPA6205A1

www.ti.com

SLOS490A–JULY 2006–REVISED AUGUST 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PACKAGED DEVICES⁽¹⁾⁽²⁾

MicroStar Junior™

(ZQV)

QFN

(DRB)

MSOP

(DGN)

Device

TPA6205A1ZQVR

AANI

TPA6205A1DRB

AAOI

TPA6205A1DGN

AAPI

Symbolization

(1) The ZQV packages are only available taped and reeled. The suffix R designates taped and reeled parts.

(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted⁽¹⁾

UNIT

V_DD

V_I

Supply voltage

–0.3 V to 6 V

–0.3 V to V_DD+ 0.3 V

See Dissipation Rating Table

–40°C to 85°C

Input voltage

INx and SHUTDOWN pins

Continuous total power dissipation

Operating free-air temperature

Junction temperature

Storage temperature

T_A

T_J

–40°C to 125°C

T_stg

–65°C to 85°C

Lead temperature 1,6 mm (1/16 Inch)

from case for 10 seconds

ZQV, DRB, DGN

260°C

(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN

2.5

TYP

MAX UNIT

V_DDSupply voltage

5.5

V

V_IH

V_IL

V_IC

T_A

High-level input voltage

SHUTDOWN

1.15

Low-level input voltage

Common-mode input voltage

Operating free-air temperature

Load impedance

SHUTDOWN

0.50

V_DD–0.8

85

V

V_DD= 2.5 V, 5.5 V, CMRR ≤– 60 dB

0.5

–40

6.4

V

°C

Ω

Z_L

8

DISSIPATION RATINGS

T

_A≤ 25°C

T_A= 70°C

POWER RATING

T_A= 85°C

POWER RATING

PACKAGE

DERATING FACTOR

POWER RATING

ZQV

DGN

DRB

885 mW

8.8 mW/°C

17.1 mW/°C

21.8 mW/°C

486 mW

354 mW

2.13 W

1.36 W

1.11 W

2.7 W

1.7 W

1.4 W

2

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SLOS490A–JULY 2006–REVISED AUGUST 2006

ELECTRICAL CHARACTERISTICS

T_A= 25°C, Gain = 1 V/V

PARAMETER

TEST CONDITIONS

V_I= 0 V, V_DD= 2.5 V to 5.5 V

MIN

TYP MAX

UNIT

mV

Output offset voltage (measured

differentially)

|V_OO

|

9

PSRR

Power supply rejection ratio

V_DD= 2.5 V to 5.5 V

–90 –70

–70 –65

–62 –55

0.30 0.46

0.22

dB

V_DD= 3.6 V to 5.5 V, V_IC= 0.5 V to V_DD–0.8

V_DD= 2.5 V, V_IC= 0.5 V to 1.7 V

CMRR Common-mode rejection ratio

dB

V_DD= 5.5 V

V_DD= 3.6 V

V_DD= 2.5 V

V_DD= 5.5 V

V_DD= 3.6 V

V_DD= 2.5 V

R_L= 8 Ω, V_IN+= V_DD

V_IN–= 0 V or V_IN+= 0 V, V_IN–= V_DD

,

V_OL

Low-level output voltage

High-level output voltage

V

0.19 0.26

5.12

4.8

2.1

R_L= 8 Ω, V_IN+= V_DD

V_IN–= 0 V or V_IN+= 0 V, V_IN–= V_DD

,

V_OH

3.28

V

2.24

|I_IH

|

High-level input current

Low-level input current

Supply current

V_DD= 5.5 V, V_I= 5.8 V

V_DD= 5.5 V, V_I= –0.3 V

1.2

µA

|I_IL|

I_DD

1.2

V_DD= 2.5 V to 5.5 V, No load, SHUTDOWN = V_IH

1.7

2

mA

Supply current in shutdown

mode

I_DD(SD)

SHUTDOWN = V_IL, V_DD= 2.5 V to 5.5 V, No load

0.01

0.9

µA

OPERATING CHARACTERISTICS

T_A= 25°C, Gain = 1 V/V, R_L= 8 Ω

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_DD= 5 V

1.25

0.63

P_O

Output power

THD + N = 1%, f = 1 kHz

V_DD= 3.6 V

V_DD= 2.5 V

W

0.3

V_DD= 5 V, P_O= 1 W, f = 1 kHz

0.06%

0.07%

0.08%

Total harmonic

distortion plus noise

THD+N

V_DD= 3.6 V, P_O= 0.5 W, f = 1 kHz

V_DD= 2.5 V, P_O= 200 mW, f = 1 kHz

C_(BYPASS)= 0.47°F, V_DD= 3.6 V to 5.5 V,

Inputs ac-grounded with C_I= 2 µF

f = 217 Hz to 2 kHz,

V_RIPPLE= 200 mV_PP

-87

-82

Supply ripple rejection C_(BYPASS)= 0.47 µF, V_DD= 2.5 V to 3.6 V,

f = 217 Hz to 2 kHz,

V_RIPPLE= 200 mV_PP

k_SVR

dB

ratio

Inputs ac-grounded with C_I= 2 µF

C_(BYPASS)= 0.47 µF, V_DD= 2.5 V to 5.5 V,

Inputs ac-grounded with C_I= 2 µF

f = 40 Hz to 20 kHz,

V_RIPPLE= 200 mV_PP

≤–74

SNR

V_n

Signal-to-noise ratio

Output voltage noise

V_DD= 5 V, P_O= 1 W

104

17

dB

No weighting

A weighting

f = 20 Hz to 20 kHz

µV_RMS

13

V_DD= 2.5 V to 5.5 V,

Resistor tolerance = 0.1%,

Gain = 4V/V, V_ICM= 200 mV_PP

f = 20 Hz to 1 kHz

≤–85

Common-mode

rejection ratio

CMRR

dB

f = 20 Hz to 20 kHz

≤–74

Z_I

Input impedance

2

MΩ

Z_O

Output impedance

Shutdown mode

>10k

Shutdown attenuation f = 20 Hz to 20 kHz, R_F= R_I= 20 kΩ

-80

dB

3

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SLOS490A–JULY 2006–REVISED AUGUST 2006

MicroStar Junior™ (ZQV) PACKAGE

(TOP VIEW)

GND

1 2

3

A

B

C

V

DD

O+

O-

SHUTDOWN

BYPASS

IN-

IN+

(SIDE VIEW)

8-PIN QFN (DRB) PACKAGE

(TOP VIEW)

1

2

3

4

8

7

6

5

SHUTDOWN

BYPASS

IN+

V

O-

GND

V

DD

IN-

V

O+

8-PIN MSOP (DGN) PACKAGE

(TOP VIEW)

V

8

SHUTDOWN

BYPASS

IN+

1

O-

GND

7

6

5

2

3

4

V

DD

IN-

V

O+

Terminal Functions

TERMINAL

I/O

DESCRIPTION

DRB,

DGN

NAME

ZQV

BYPASS

GND

C1

B2

C3

C2

B1

A3

B3

A1

N/A

2

7

4

3

1

6

5

8

I

Mid-supply voltage. Adding a bypass capacitor improves PSRR.

High-current ground

IN-

I

Negative differential input

IN+

I

Positive differential input

SHUTDOWN

V_DD

I

Shutdown terminal (active low logic)

Supply voltage terminal

I

V_O+

O

Positive BTL output

V_O-

Negative BTL output

Connect to ground. Thermal pad must be soldered down in all applications to properly secure

device on the PCB.

Thermal Pad

4

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SLOS490A–JULY 2006–REVISED AUGUST 2006

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

vs Supply voltage

vs Load resistance

vs Output power

1

P_O

P_D

Output power

2, 3

Power dissipation

4, 5

Maximum ambient temperature

vs Power dissipation

vs Output power

6

7, 8

Total harmonic distortion + noise

vs Frequency

9, 10, 11, 12

vs Common-mode input voltage

vs Frequency

13

Supply voltage rejection ratio

GSM Power supply rejection

14, 15, 16, 17

vs Common-mode input voltage

vs Time

18

19

20

21

22

23

24

25

26

vs Frequency

CMRR Common-mode rejection ratio

vs Common-mode input voltage

vs Frequency

Closed loop gain/phase

Open loop gain/phase

vs Frequency

I_DD

Supply current

Start-up time

vs Supply voltage

vs Bypass capacitor

5

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SLOS490A–JULY 2006–REVISED AUGUST 2006

TYPICAL CHARACTERISTICS

OUTPUT POWER

vs

SUPPLY VOLTAGE

OUTPUT POWER

vs

LOAD RESISTANCE

OUTPUT POWER

vs

LOAD RESISTANCE

1.8

1.6

1.4

1.2

1

1.8

1.4

f = 1 kHz

THD+N = 10%

Gain = 1 V/V

R

= 8 Ω

f = 1 kHz

THD+N = 1%

Gain = 1 V/V

L

1.6

1.4

1.2

f = 1 kHz

Gain = 1 V/V

1.2

1

V

= 5 V

DD

V

= 5 V

DD

THD+N = 10%

V

= 3.6 V

V

DD

V

= 3.6 V

DD

0.8

0.6

0.4

1

0.8

V

= 2.5 V

DD

0.8

0.6

0.4

= 2.5 V

DD

0.6

0.4

0.2

THD+N = 1%

0.2

0

0.2

0

2.5

3

3.5

4

4.5

5

8

13

18

23

28

32

8

13

18

23

28

32

V

- Supply Voltage - V

R

L

- Load Resistance - Ω

DD

R

L

- Load Resistance - Ω

Figure 1.

Figure 2.

Figure 3.

MAXIMUM AMBIENT

TEMPERATURE

vs

POWER DISSIPATION

vs

OUTPUT POWER

POWER DISSIPATION

vs

OUTPUT POWER

POWER DISSIPATION

0.4

0.35

0.3

90

80

70

60

50

40

30

20

10

0

0.7

V

= 5 V

V

= 3.6 V

DD

0.6

0.5

0.4

0.3

0.2

0.1

0

8 Ω

0.25

0.2

0.15

0.1

16 Ω

ZQV Package Only

0.05

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

0

0.2

0.4

0.6

0.8

0

0.2 0.4

0.6

0.8

1

1.2 1.4

P - Power Dissipation - W

D

P

- Output Power - W

P

- Output Power - W

O

Figure 4.

Figure 5.

Figure 6.

TOTAL HARMONIC DISTORTION +

NOISE

vs

NOISE

vs

NOISE

vs

OUTPUT POWER

FREQUENCY

10

5

R

= 16 Ω

V

= 5 V

L

DD

C = 2 µF

5

2

50 mW

f = 1 kHz

I

2

1

C

= 0 to 1 µF

R = 8 Ω

L

(Bypass)

2.5 V

2

1

Gain = 1 V/V

C

= 0 to 1 µF

(Bypass)

3.6 V

0.5

Gain = 1 V/V

1

0.2

0.1

250 mW

0.5

5 V

0.5

2.5 V

3.6 V

5 V

0.05

0.2

0.1

0.2

0.1

0.02

0.01

1 W

0.05

R

C

= 8 Ω, f = 1 kHz

0.005

L

= 0 to 1 µF

(Bypass)

0.02

0.01

0.02

0.01

0.002

0.001

Gain = 1 V/V

10 m

100 m

1

2

3

10 m

100 m

1

2

20

100 200

1 k 2 k

10 k 20 k

f - Frequency - Hz

P

- Output Power - W

P

- Output Power - W

O

Figure 7.

Figure 8.

Figure 9.

6

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SLOS490A–JULY 2006–REVISED AUGUST 2006

TYPICAL CHARACTERISTICS (continued)

TOTAL HARMONIC DISTORTION +

NOISE

vs

NOISE

vs

NOISE

vs

FREQUENCY

10

5

10

5

10

5

V

= 3.6 V

DD

C = 2 µF

V

= 2.5 V

V

= 3.6 V

25 mW

DD

C = 2 µF

DD

C = 2 µF

I

15 mW

I

2

1

2

1

2

1

R

C

= 8 Ω

L

25 mW

R

C

= 8 Ω

R

C

= 16 Ω

L

= 0 to 1 µF

(Bypass)

L

= 0 to 1 µF

(Bypass)

= 0 to 1 µF

(Bypass)

Gain = 1 V/V

0.5

Gain = 1 V/V

0.2

0.1

0.2

0.1

0.2

0.1

125 mW

75 mW

0.05

0.02

0.01

0.02

0.01

0.02

0.01

500 mW

200 mW

250 mW

0.005

0.002

0.001

0.002

0.001

0.002

0.001

20

50 100 200 500 1 k 2 k 5 k 10 k 20 k

20

50 100 200 500 1 k 2 k 5 k 10 k 20 k

20

50 100 200 500 1 k 2 k 5 k 10 k 20 k

f - Frequency - Hz

Figure 10.

Figure 11.

Figure 12.

TOTAL HARMONIC DISTORTION +

SUPPLY VOLTAGE REJECTION

NOISE

RATIO

vs

RATIO

vs

COMMON MODE INPUT VOLTAGE

FREQUENCY

0

-10

-20

0

-10

-20

10

Gain = 5 V/V

f = 1 kHz

C = 2 µF

I

C = 2 µF

I

P

= 200 mW

R = 8 Ω

L

O

R

C

V

= 8 Ω

L

C

= 0.47 µF

(Bypass)

= 200 mV

= 0.47 µF

(Bypass)

= 200 mV

V

p-p

-30

-40

-50

-60

-70

-80

-30

-40

-50

-60

-70

-80

p-p

Inputs ac-Grounded

Gain = 1 V/V

1

V

=2. 5 V

DD

V

= 2.5 V

DD

V

= 5 V

DD

V

=2. 5 V

DD

0.10

0.01

V

= 5 V

DD

= 3.6 V

DD

V

= 3.6 V

DD

-90

V

= 3.6 V

DD

-100

20 50 100 200 500 1 k 2 k 5 k 10 k 20 k

0

0.5

1

1.5

2

2.5

3

3.5

f - Frequency - Hz

V

- Common Mode Input Voltage - V

IC

Figure 13.

Figure 14.

Figure 15.

SUPPLY VOLTAGE REJECTION

RATIO

vs

RATIO

vs

RATIO

vs

FREQUENCY

COMMON MODE INPUT VOLTAGE

0

-10

-20

0

-10

-20

-10

-20

-30

-40

-50

-60

-70

f = 217 Hz

V

= 3.6 V

C = 2 µF

DD

C = 2 µF

I

C

R

= 0.47 µF

(Bypass)

R

L

= 8 Ω

I

= 8 Ω

R

= 8 Ω

L

Inputs Floating

Gain = 1 V/V

L

Gain = 1 V/V

Inputs ac-Grounded

Gain = 1 V/V

-30

-40

-50

-60

-70

-80

-30

-40

-50

-60

-70

-80

V

= 2.5 V

V

= 3.6 V

DD

C

= 0

(Bypass)

C

= 0.47 µF

(Bypass)

V

=2. 5 V

DD

C

= 1 µF

(Bypass)

V

= 5 V

DD

V

= 3.6 V

DD

C

= 0.1 µF

(Bypass)

-80

-90

V

= 5 V

-90

DD

-100

20 50 100 200 500 1 k 2 k 5 k 10 k 20 k

0

1

2

3

4

5

V

- Common Mode Input Voltage - V

IC

f - Frequency - Hz

Figure 16.

Figure 17.

Figure 18.

7

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SLOS490A–JULY 2006–REVISED AUGUST 2006

TYPICAL CHARACTERISTICS (continued)

GSM POWER SUPPLY

REJECTION

vs

REJECTION

vs

COMMON MODE REJECTION RATIO

vs

TIME

FREQUENCY

0

V

DD

V

R

= 2.5 V to 5 V

DD

C1

Frequency

217.41 Hz

-10

-20

-30

-40

-50

-60

-70

-80

= 200 mV

IC

p-p

-50

= 8 Ω

L

Gain = 1 V/V

C1 - Duty

20 %

-100

-150

C1 High

3.598 V

0

V

C

Shown in Figure 19

= 2 µF,

DD

I

-50

C1 Pk-Pk

504 mV

= 0.47 µF,

(Bypass)

Inputs ac-Grounded

Gain = 1V/V

V

O

-100

-150

-90

Ch1 100 mV/div

Ch4 10 mV/div

2 ms/div

0

200 400 600 800 1k 1.2k 1.4k1.6k1.8k 2k

-100

f - Frequency - Hz

20 50 100 200 500 1 k 2 k 5 k 10 k 20 k

t - Time - ms

f - Frequency - Hz

Figure 19.

Figure 20.

Figure 21.

COMMON MODE REJECTION RATIO

vs

COMMON MODE INPUT VOLTAGE

CLOSED LOOP GAIN/PHASE

OPEN LOOP GAIN/PHASE

vs

FREQUENCY

40

30

20

10

220

200

150

100

50

200

0

Phase

V

R

= 3.6 V

DD

= 8 Ω

180

140

100

60

R

= 8 Ω

-10

-20

-30

-40

L

150

100

50

L

Gain = 1 V/V

Gain

0

-10

-20

-30

-40

-50

20

V

= 2.5 V

DD

0

-50

-60

-70

-80

-20

V

= 5 V

DD

-50

-60

-50

Phase

-100

-140

-180

-220

-100

V

R

= 3.6 V

DD

= 8 Ω

L

-150

-200

-150

-200

-60

-70

Gain = 1 V/V

-90

V

= 3.6 V

DD

-100

10 100 1 k

10 k 100 k 1 M

10 M

100

1 k

10 k

100 k

1 M

10 M

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5 5

f - Frequency - Hz

V

- Common Mode Input Voltage - V

IC

Figure 22.

Figure 23.

Figure 24.

SUPPLY CURRENT

vs

SUPPLY VOLTAGE

START-UP TIME⁽¹⁾

vs

BYPASS CAPACITOR

6

5

1.8

1.6

1.4

1.2

4

3

2

1

0

1

0.8

0.6

0.4

0.2

0

0.5

(Bypass)

1

1.5

2

C

- Bypass Capacitor - µF

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

(1)

Start-Up time is the time it takes (from

a

V

- Supply Voltage - V

DD

low-to-high transition on SHUTDOWN) for the

gain of the amplifier to reach -3 dB of the final

gain.

Figure 25.

Figure 26.

8

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SLOS490A–JULY 2006–REVISED AUGUST 2006

APPLICATION INFORMATION

•

Mid-supply bypass capacitor, C_(BYPASS), not

required: The fully differential amplifier does not

require a bypass capacitor. This is because any

shift in the mid-supply affects both positive and

negative channels equally and cancels at the

differential output. However, removing the

bypass capacitor slightly worsens power supply

rejection ratio (k_SVR), but a slight decrease of

k_SVRmay be acceptable when an additional

component can be eliminated (see Figure 17).

FULLY DIFFERENTIAL AMPLIFIER

The TPA6205A1 is a fully differential amplifier with

differential inputs and outputs. The fully differential

amplifier consists of a differential amplifier and a

common- mode amplifier. The differential amplifier

ensures that the amplifier outputs a differential

voltage that is equal to the differential input times the

gain. The common-mode feedback ensures that the

common-mode voltage at the output is biased

around V_DD/2 regardless of the common- mode

voltage at the input.

•

Better RF-immunity: GSM handsets save power

by turning on and shutting off the RF transmitter

at a rate of 217 Hz. The transmitted signal is

picked-up on input and output traces. The fully

differential amplifier cancels the signal much

better than the typical audio amplifier.

Advantages of Fully Differential Amplifiers

•

Input coupling capacitors not required: A fully

differential amplifier with good CMRR, like the

TPA6205A1, allows the inputs to be biased at

voltage other than mid-supply. For example, if a

DAC has mid-supply lower than the mid-supply

of the TPA6205A1, the common-mode feedback

circuit adjusts for that, and the TPA6205A1

outputs are still biased at mid-supply of the

TPA6205A1. The inputs of the TPA6205A1 can

be biased from 0.5 V to V_DD- 0.8 V. If the inputs

are biased outside of that range, input coupling

capacitors are required.

APPLICATION SCHEMATICS

Figure 27 through Figure 31 show application

schematics for differential and single-ended inputs.

Typical values are shown in Table 1.

Table 1. Typical Component Values

COMPONENT

VALUE

10 kΩ

0.22 µF

1 µF

R_I

R_F

(1)

C_(BYPASS)

C_S

C_I

0.22 µF

(1) C_(BYPASS)is optional

V

DD

R

F

To Battery

C

s

R

-

I

IN-

_

+

V

O+

In From

DAC

V

R

I

O-

+

IN+

R

F

GND

SHUTDOWN

Bias

Circuitry

C _BYPASS

(

)

(Optional)

Figure 27. Typical Differential Input Application Schematic

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V

DD

R

F

To Battery

C

I

C

s

R

I

IN-

-

_

+

V

O+

IN

+

R

I

V

O-

IN+

C

I

R

F

GND

SHUTDOWN

Bias

Circuitry

C _BYPASS

(

(Optional)

)

Figure 28. Differential Input Application Schematic Optimized With Input Capacitors

V

DD

R

F

To Battery

C

I

C

s

R

I

IN-

_

+

V

O+

IN

R

V

I

O-

IN+

C

I

R

F

GND

SHUTDOWN

C _BYPASS

Bias

Circuitry

(

)

(Optional)

Figure 29. Single-Ended Input Application Schematic

C

R

I2

-

Differential

Input 2

R

C

V

I2

DD

+

R

F

To Battery

C

S

C

R

I1

-

IN-

O+

_

+

Differential

Input 1

V

C

O-

I1

+

I1

IN+

R

F

GND

SHUTDOWN

Bias

Circuitry

C _BYPASS

(

(Optional)

)

Figure 30. Application Schematic With TPA6205A1 Summing Two Differetial Inputs

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C

I2

R

I2

V

DD

Single Ended

Input 2

R

F

To Battery

C

I1

C

s

I1

Single Ended

Input 1

IN-

_

+

V

O+

R

V

P

O-

IN+

C

P

R

F

GND

SHUTDOWN

C _BYPASS

Bias

Circuitry

(

)

(Optional)

Figure 31. Application Schematic With TPA6205A1 Summing Two Single-Ended Inputs

Input Capacitor (C_I)

SELECTING COMPONENTS

The TPA6205A1 does not require input coupling

capacitors if using a differential input source that is

biased from 0.5 V to V_DD- 0.8 V. Use 1% tolerance

or better gain-setting resistors if not using input

coupling capacitors.

Resistors (R_Fand R_I)

The input (R_I) and feedback resistors (R_F) set the

gain of the amplifier according to Equation 1.

Gain − R_F/R_I

(1)

In the single-ended input application an input

capacitor, C_I, is required to allow the amplifier to bias

the input signal to the proper dc level. In this case, C_I

and R_Iform a high-pass filter with the corner

frequency determined in Equation 2.

R_Fand R_Ishould range from 1 kΩ to 100 kΩ. Most

graphs were taken with R_F= R_I= 20 kΩ.

Resistor matching is very important in fully

differential amplifiers. The balance of the output on

the reference voltage depends on matched ratios of

the resistors. CMRR, PSRR, and the cancellation of

the second harmonic distortion diminishes if resistor

mismatch occurs. Therefore, it is recommended to

use 1% tolerance resistors or better to keep the

performance optimized.

1

f

+

c

2pR C

I

(2)

–3 dB

Bypass Capacitor (C_BYPASS) and Start-Up Time

The internal voltage divider at the BYPASS pin of

this device sets a mid-supply voltage for internal

references and sets the output common mode

voltage to V_DD/2. Adding a capacitor to this pin filters

any noise into this pin and increases the k_SVR

.

C_(BYPASS)also determines the rise time of V_O+and V_O-

when the device is taken out of shutdown. The larger

the capacitor, the slower the rise time. Although the

output rise time depends on the bypass capacitor

value, the device passes audio 4 µs after taken out

of shutdown and the gain is slowly ramped up based

f

c

The value of C_Iis important to consider as it directly

affects the bass (low frequency) performance of the

circuit. Consider the example where R_Iis 10 kΩ and

the specification calls for a flat bass response down

to 100 Hz. Equation 2 is reconfigured as Equation 3.

on C_(BYPASS)

.

1

C

+

To minimize pops and clicks, design the circuit so

the impedance (resistance and capacitance)

detected by both inputs, IN+ and IN-, is equal.

I

2pR f

c

I

(3)

In this example, C_Iis 0.16 µF, so one would likely

choose a value in the range of 0.22 µF to 0.47 µF. A

further consideration for this capacitor is the leakage

path from the input source through the input network

(R_I, C_I) and the feedback resistor (R_F) to the load.

11

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Summing

a

Differential Input Signal and a

This leakage current creates a dc offset voltage at

the input to the amplifier that reduces useful

headroom, especially in high gain applications. For

this reason, a ceramic capacitor is the best choice.

When polarized capacitors are used, the positive

side of the capacitor should face the amplifier input

in most applications, as the dc level there is held at

V_DD/2, which is likely higher than the source dc level.

It is important to confirm the capacitor polarity in the

application.

Single-Ended Input Signal

Figure 31 shows how to sum a differential input

signal and a single-ended input signal. Ground noise

can couple in through IN+ with this method. It is

better to use differential inputs. To assure that each

input is balanced, the single-ended input must be

driven by a low-impedance source even if the input is

not in use. Both input nodes must see the same

impedance for optimum performance, thus the use of

R_Pand C_P.

Decoupling Capacitor (C_S)

V

R

O

I1

F

V

ǒ Ǔ

Gain 1 +

+ *

The TPA6205A1 is a high-performance CMOS audio

amplifier that requires adequate power supply

decoupling to ensure the output total harmonic

distortion (THD) is as low as possible. Power supply

decoupling also prevents oscillations for long lead

lengths between the amplifier and the speaker. For

higher frequency transients, spikes, or digital hash

on the line, a good low equivalent-series- resistance

(ESR) ceramic capacitor, typically 0.1 µF to 1 µF,

placed as close as possible to the device V_DDlead

works best. For filtering lower frequency noise

signals, a 10-µF or greater capacitor placed near the

audio power amplifier also helps, but is not required

in most applications because of the high PSRR of

this device.

V

I1

(6)

(7)

V

R

O

I2

F

V

ǒ Ǔ

Gain 2 +

+ *

R

I2

Where

C_P= C_I1// C_I2

R_P= R_I1// R_I2

USING LOW-ESR CAPACITORS

Low-ESR capacitors are recommended throughout

this applications section. A real (as opposed to ideal)

capacitor can be modeled simply as a resistor in

series with an ideal capacitor. The voltage drop

across this resistor minimizes the beneficial effects of

the capacitor in the circuit. The lower the equivalent

value of this resistance the more the real capacitor

behaves like an ideal capacitor.

SUMMING INPUT SIGNALS WITH THE

TPA6205A1

Most wireless phones or PDAs need to sum signals

at the audio power amplifier or just have two signal

sources that need separate gain. The TPA6205A1

makes it easy to sum signals or use separate signal

sources with different gains. Many phones now use

the same speaker for the earpiece and ringer, where

the wireless phone would require a much lower gain

for the phone earpiece than for the ringer. PDAs and

phones that have stereo headphones require

summing of the right and left channels to output the

stereo signal to the mono speaker.

DIFFERENTIAL OUTPUT VERSUS

SINGLE-ENDED OUTPUT

Figure 32 shows a Class-AB audio power amplifier

(APA) in

a fully differential configuration. The

TPA6205A1 amplifier has differential outputs driving

both ends of the load. There are several potential

benefits to this differential drive configuration, but

initially consider power to the load. The differential

drive to the speaker means that as one side is

slewing up, the other side is slewing down, and vice

versa. This in effect doubles the voltage swing on the

load as compared to a ground referenced load.

Plugging 2 × V_O(PP)into the power equation, where

voltage is squared, yields 4× the output power from

the same supply rail and load impedance (see

Equation 8).

Summing Two Differential Input Signals

Two extra resistors are needed for summing

differential signals (a total of 10 components). The

gain for each input source can be set independently

(see Equation 4 and Equation 5, and Figure 30).

V

R

O

I1

F

V

ǒ Ǔ

Gain 1 +

+ *

V

I1

(4)

(5)

V

R

O

I2

F

V

ǒ Ǔ

Gain 2 +

+ *

R

I2

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1

V

f

+

O(PP)

c

2pR C

V

+

(rms)

L C

(9)

Ǹ

2 2

For example, a 68-µF capacitor with an 8-Ω speaker

would attenuate low frequencies below 293 Hz. The

BTL configuration cancels the dc offsets, which

eliminates the need for the blocking capacitors.

Low-frequency performance is then limited only by

the input network and speaker response. Cost and

PCB space are also minimized by eliminating the

bulky coupling capacitor.

2

V

(rms)

Power +

R

L

(8)

V

DD

V

DD

V

O(PP)

V

O(PP)

C

2x V

V

O(PP)

R

O(PP)

L

R

L

V

DD

–V

O(PP)

–3 dB

Figure 32. Differential Output Configuration

In a typical wireless handset operating at 3.6 V,

bridging raises the power into an 8-Ω speaker from a

singled-ended (SE, ground reference) limit of 200

mW to 800 mW. In sound power that is a 6-dB

improvement—which is loudness that can be heard.

In addition to increased power there are frequency

response concerns. Consider the single-supply SE

f

c

Figure 33. Single-Ended Output and Frequency

Response

Increasing power to the load does carry a penalty of

increased internal power dissipation. The increased

dissipation is understandable considering that the

BTL configuration produces 4× the output power of

the SE configuration.

configuration shown in Figure 33.

A coupling

capacitor is required to block the dc offset voltage

from reaching the load. This capacitor can be quite

large (approximately 33 µF to 1000 µF) so it tends to

be expensive, heavy, occupy valuable PCB area,

and have the additional drawback of limiting

low-frequency performance of the system. This

frequency-limiting effect is due to the high pass filter

network created with the speaker impedance and the

coupling capacitance and is calculated with

Equation 9.

FULLY DIFFERENTIAL AMPLIFIER

EFFICIENCY AND THERMAL INFORMATION

Class-AB amplifiers are inefficient. The primary

cause of these inefficiencies is voltage drop across

the output stage transistors. There are two

components of the internal voltage drop. One is the

headroom or dc voltage drop that varies inversely to

output power. The second component is due to the

sinewave nature of the output. The total voltage drop

can be calculated by subtracting the RMS value of

the output voltage from V_DD. The internal voltage

drop multiplied by the average value of the supply

current, I_DD(avg), determines the internal power

dissipation of the amplifier.

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An easy-to-use equation to calculate efficiency starts

out as being equal to the ratio of power from the

power supply to the power delivered to the load. To

accurately calculate the RMS and average values of

power in the load and in the amplifier, the current

and voltage waveform shapes must first be

understood (see Figure 34).

Although the voltages and currents for SE and BTL

are sinusoidal in the load, currents from the supply

are very different between SE and BTL

configurations. In an SE application the current

waveform is a half-wave rectified shape, whereas in

BTL it is a full-wave rectified waveform. This means

RMS conversion factors are different. Keep in mind

that for most of the waveform both the push and pull

transistors are not on at the same time, which

supports the fact that each amplifier in the BTL

device only draws current from the supply for half the

waveform. The following equations are the basis for

calculating amplifier efficiency.

V

O

V

(LRMS)

I

DD

I

DD(avg)

Figure 34. Voltage and Current Waveforms for

BTL Amplifiers

P

L

Efficiency of a BTL amplifier +

P

SUP

where:

2

V rms

L

V

P

2R

P

+

, andV

+

, therefore, P

+

L

LRMS

L

Ǹ

R

2

L

p

2V

V

p

V

P

1

p

P

1

p

P

+

+ *

sin(t) dt

[cos(t)]

0

ŕ

P

+ V

I

avg

and

I

avg +

and

p R

SUP

DD DD

DD

R

L

0

L

Therefore,

2 V

V

DD

P

+

SUP

p R

L

P = Power delivered to load

substituting P and P

into equation 6,

2

L

SUP

P

V

= Power drawn from power supply

= RMS voltage on BTL load

SUP

V

P

2 R

L

LRMS

R = Load resistance

L

p V

P

Efficiency of a BTL amplifier +

V = Peak voltage on BTL load

+

P

DD

4 V

2 V

V

I

avg = Average current drawn from the

power supply

DD

p R

P

L

where:

V

DD

= Power supply voltage

η

= Efficiency of a BTL amplifier

BTL

V

+ Ǹ2 P R

L L

P

(10)

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Therefore,

1

Θ

+

+ 113°CńW

JA

0.0088

Derating Factor

(13)

p Ǹ2 P

R

L

Given θ_JA, the maximum allowable junction

temperature, and the maximum internal dissipation,

the maximum ambient temperature can be calculated

with the following equation. The maximum

recommended junction temperature for the

TPA6205A1 is 125°C.

h

+

BTL

4 V

DD

(11)

Table 2. Efficiency and Maximum Ambient

Temperature vs Output Power in 5-V 8-Ω BTL

Systems

T

Max + T Max * Θ

P

Power

From

Supply Temperature

(W)

0.75

1.12

1.59

1.78

Max

Ambient

A

J

JA Dmax

Output

Power

(W)

Internal

Dissipation

(W)

Efficiency

(%)

(

)

+ 125 * 113 0.634 + 53.3°C

(14)

(°C)

Equation 14 shows that the maximum ambient

temperature is 53.3°C at maximum power dissipation

with a 5-V supply.

0.25

0.50

1.00

1.25

31.4

44.4

62.8

70.2

0.55

0.62

0.59

0.53

62

54

58

Table 2 shows that for most applications no airflow is

required to keep junction temperatures in the

specified range. The TPA6205A1 is designed with

thermal protection that turns the device off when the

junction temperature surpasses 150°C to prevent

damage to the IC. Also, using more resistive than

8-Ω speakers dramatically increases the thermal

performance by reducing the output current.

65

Table 2 employs Equation 11 to calculate efficiencies

for four different output power levels. Note that the

efficiency of the amplifier is quite low for lower power

levels and rises sharply as power to the load is

increased resulting in a nearly flat internal power

dissipation over the normal operating range. Note

that the internal dissipation at full output power is

less than in the half power range. Calculating the

efficiency for a specific system is the key to proper

power supply design. For a 1.25-W audio system

with 8-Ω loads and a 5-V supply, the maximum draw

on the power supply is almost 1.8 W.

PCB LAYOUT

For the DRB (QFN/SON) and DGN (MSOP)

packages, it is good practice to minimize the

presence of voids within the exposed thermal pad

interconnection. Total elimination is difficult, but the

design of the exposed pad stencil is key. The stencil

design proposed in the Texas Instruments

application note "QFN/SON PCB Attachment"

(SLUA271) enables out-gassing of the solder paste

during reflow as well as regulating the finished solder

thickness. Typically the solder paste coverage is

approximately 50% of the pad area.

A final point to remember about Class-AB amplifiers

is how to manipulate the terms in the efficiency

equation to the utmost advantage when possible.

Note that in Equation 11, V_DDis in the denominator.

This indicates that as V_DDgoes down, efficiency

goes up.

A simple formula for calculating the maximum power

dissipated, P_Dmax, may be used for a differential

output application:

In making the pad size for the BGA balls, it is

recommended that the layout use solder-

mask-defined (SMD) land. With this method, the

copper pad is made larger than the desired land

area, and the opening size is defined by the opening

in the solder mask material. The advantages

normally associated with this technique include more

closely controlled size and better copper adhesion to

the laminate. Increased copper also increases the

thermal performance of the IC. Better size control is

the result of photo imaging the stencils for masks.

Small plated vias should be placed near the center

ball connecting ball B2 to the ground plane. Added

plated vias and ground plane act as a heatsink and

increase the thermal performance of the device.

Figure 35 shows the appropriate diameters for a 2

mm × 2 mm MicroStar Junior™ BGA layout.

2 V²

DD

+

P

p²R

D max

L

(12)

P_Dmaxfor a 5-V, 8-Ω system is 634 mW.

The maximum ambient temperature depends on the

heat sinking ability of the PCB system. The derating

factor for the 2 mm x 2 mm Microstar Junior™

package is shown in the dissipation rating table.

Converting this to θ_JA:

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It is very important to keep the TPA6205A1 external

components very close to the TPA6205A1 to limit

noise pickup. The TPA6205A1 evaluation module

(EVM) layout is shown in the next section as a layout

example.

0.38 mm

0.25 mm

0.28 mm

C1

B1

A1

VIAS to Ground Plane

C2

C3

B2

B3

Solder Mask

A3

Paste Mask (Stencil)

Copper Trace

Figure 35. MicroStar Junior™ BGA Recommended Layout

16

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PACKAGE OPTION ADDENDUM

www.ti.com

6-Nov-2006

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TPA6205A1DGN

ACTIVE

MSOP-

Power

PAD

DGN

8

80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPA6205A1DGNG4

TPA6205A1DGNR

TPA6205A1DGNRG4

ACTIVE

MSOP-

Power

PAD

DGN

80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

MSOP-

Power

PAD

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

MSOP-

Power

PAD

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPA6205A1DRBR

TPA6205A1DRBRG4

TPA6205A1DRBT

ACTIVE

SON

DRB

8

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

PREVIEW

Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

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Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

型号:	TPA6205A1DGN
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	MSOP
包装说明：	HTSSOP, TSSOP8,.19
针数：	8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.33.00.01
Factory Lead Time：	1 week
风险等级：	1.76
Samacsys Description：	Texas Instruments,TPA6205A1DGN,IC,Audio Texas Instruments TPA6205A1DGN Audio Amplifier IC, Class-AB Mono -70dB, 8-Pin MSOP
标称带宽：	20 kHz
商用集成电路类型：	AUDIO AMPLIFIER
谐波失真：	1%
JESD-30 代码：	S-PDSO-G8
JESD-609代码：	e4
长度：	3 mm
湿度敏感等级：	1
标称噪声指数：	104 dB
信道数量：	1
功能数量：	1
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-40 °C
标称输出功率：	1.25 W
封装主体材料：	PLASTIC/EPOXY
封装代码：	HTSSOP
封装等效代码：	TSSOP8,.19
封装形状：	SQUARE
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
电源：	3/5 V
认证状态：	Not Qualified
座面最大高度：	1.1 mm
子类别：	Audio/Video Amplifiers
最大压摆率：	2 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	2.5 V
表面贴装：	YES
技术：	CMOS
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3 mm

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