TPD4E02B04DQAR全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

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产品型号TPD4E02B04DQAR的概述

芯片TPD4E02B04DQAR的概述 TPD4E02B04DQAR是德州仪器（Texas Instruments）推出的一种高效保护芯片，设计用于保护敏感电子设备免受过电压和静电放电（ESD）的损害。在现代电子设备中，由于对高集成度与小型化的要求日益增加，这种保护方案显得尤为重要。TPD4E02B04DQAR专门针对USB接口、HDMI接口和其他I/O接口提供高达8千伏（kV）的ESD保护，同时具有较低的钳位电压，提高了系统的可靠性与性能。这种保护芯片的设计理念是采用了四通道的ESD保护结构，使其能够同时支持多个信号线的保护，同时保持较低的漏电流。TPD4E02B04DQAR的回应速度快，能有效地应对瞬时的电压尖峰，确保电路内部组件的安全。芯片TPD4E02B04DQAR的详细参数 TPD4E02B04DQAR的主要参数集中在其电气特性、封装形式及工作条件，具体如下： - 工作电...

产品型号TPD4E02B04DQAR的Datasheet PDF文件预览

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TPD4E02B04

ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016

TPD4E02B04 用于 USB Type-C 和 HDMI 2.0 的 4 通道 ESD 保护二极管

1 特性

•

接口

–

USB Type-C

•

IEC 61000-4-2 4 级静电放电 (ESD) 保护

USB 3.1 第 2 代

高清多媒体接口 (HDMI) 2.0/1.4

USB 3.0

–

±12kV 接触放电

±15kV 气隙放电

•

IEC 61000-4-4 瞬态放电 (EFT) 保护

80A (5/50ns)

IEC 61000-4-5 浪涌保护

2A (8/20µs)

DisplayPort 1.3

–

PCI Express 3.0

–

3 说明

•

IO 电容：0.27pF（典型值）、0.37pF（最大值）

直流击穿电压：5.5V（最小值）

TPD4E02B04 是一款双向瞬态电压抑制器 (TVS) ESD

保护二极管阵列，用于为 USB Type-C 和 HDMI 2.0

电路提供保护。TPD4E02B04 的额定 ESD 冲击消散

值等于 IEC 61000-4-2（4 级）国际标准中规定的最高

水平。

超低泄漏电流：10nA（最大值）

低静电放电 (ESD) 钳位电压：5A 传输线路脉冲

(TLP) 时为 8.8V

•

支持速率高达 10Gbps 的高速接口

工业温度范围：–40°C 至 125°C

简易直通布线封装

该器件的每条通道具有一个 0.27pF IO 电容，适用于

保护速率高达 10Gbps 的高速接口（例如 USB 3.1 第

2 代）。低动态电阻和低钳位电压可针对瞬变事件提供

系统级保护。

2 应用

•

终端设备

TPD4E02B04 采用符合工业标准的 USON-10 (DQA)

封装。该封装采用直通布线，其引脚间距为 0.5mm，

能够简化应用实现并缩短设计时间。

–

便携式计算机和台式机

机顶盒

电视和监视器

手机和平板电脑

器件信息⁽¹⁾

数字视频录像机 (DVR) 和网络视频录像机

器件型号

封装

封装尺寸（标称值）

(NVR)

TPD4E02B04

USON (10) 2.50mm x 1.00mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

典型应用电路原理图

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSD85

TPD4E02B04

ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016

www.ti.com.cn

7.4 Device Functional Modes........................................ 10

Application and Implementation ........................ 11

8.1 Application Information............................................ 11

8.2 Typical Application ................................................. 11

Power Supply Recommendations...................... 14

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 5

Detailed Description .............................................. 9

7.1 Overview ................................................................... 9

7.2 Functional Block Diagram ......................................... 9

7.3 Feature Description................................................... 9

10 Layout................................................................... 14

10.1 Layout Guidelines ................................................. 14

10.2 Layout Examples................................................... 14

11 器件和文档支持 ..................................................... 16

11.1 文档支持 ............................................................... 16

11.2 社区资源................................................................ 16

11.3 商标....................................................................... 16

11.4 静电放电警告......................................................... 16

11.5 Glossary................................................................ 16

12 机械、封装和可订购信息....................................... 16

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (Novemeber 2015) to Revision A

Page

•

已将器件状态由“产品预览”更改为“量产数据” .......................................................................................................................... 1

TPD4E02B04

www.ti.com.cn

ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016

5 Pin Configuration and Functions

DQA Package

10-Pin USON

Top View

IO1

IO2

10 NC

GND

IO3

GND

IO4

Pin Functions

TYPE

DESCRIPTION

NAME

GND

IO1

NO.

Ground

Ground. Connect to ground.

ESD Protected Channel

IO2

I/O

IO3

IO4

Not Connected; Used for optional straight-through routing. Can be left floating or

grounded.

TPD4E02B04

ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Electrical Fast Transient

Peak Pulse

IEC 61000-4-5 (5/50 ns)

IEC 61000-4-5 Power (t_p- 8/20 µs)

IEC 61000-4-5 Current (t_p- 8/20 µs)

Operating free-air temperature

Storage temperature

T_A

–40

–65

125

155

°C

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2500

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1000

V_(ESD)

Electrostatic discharge

IEC 61000-4-2 contact discharge

IEC 61000-4-2 air-gap discharge

±12000

±15000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

3.6

UNIT

V_IO

T_A

Input pin voltage

–3.6

–40

Operating free-air temperature

125

°C

6.4 Thermal Information

TPD4E02B04

THERMAL METRIC⁽¹⁾

DQA (USON)

10 PINS

348.7

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

214.1

270.7

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

81.7

ψ_JB

270.7

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

TPD4E02B04

www.ti.com.cn

ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_RWM

V_BRF

Reverse stand-off voltage

I_IO< 10 nA

-3.6

3.6

Breakdown Voltage, any IO pin to

GND⁽¹⁾

I_IO= 1 mA, T_A= 25°C

5.5

6.4

7.5

Breakdown Voltage, GND to any IO

pin⁽¹⁾

V_BRR

I_IO= 1 mA, T_A= 25°C

-5.5

-6.4

-7.5

V_HOLD

Holding voltage⁽²⁾

Clamping voltage

I_IO= 1 mA

5.8

6.6

8.8

6.6

8.8

I_PP= 1 A, TLP, from IO to GND

I_PP= 5 A, TLP, from IO to GND

I_PP= 1 A, TLP, from GND to IO

I_PP= 5A, TLP, from GND to IO

V_IO= ±2.5 V

V_CLAMP

I_LEAK

R_DYN

Leakage current, any IO to GND

Dynamic Resistance

IO to GND

0.47

GND to IO

V_IO= 0 V, f = 1 MHz, IO to GND, T_A

= 25°C

C_L

Line Capacitance

0.27

0.01

0.13

0.37

0.07

Delta of capacitance between any

two IO pins, V_IO= 0 V, f = 1 MHz, T_A

= 25°C, GND = 0 V

ΔC_L

Variation of Line Capacitance

Channel to Channel Capacitance

Capacitance from one IO to another,

V_IO= 0 V, f = 1 MHz, GND = 0 V

C_CROSS

(1) V_BRFand V_BRRare defined as the voltage when 1mA is applied in the positive-going direction, before the device latches into the

snapback state

(2) V_HOLDis defined as the voltage when 1mA is applied in the negative-going direction, after the device has successfully latched into the

snapback state

6.6 Typical Characteristics

Voltage (V)

C001

C002

Figure 1. Positive TLP Curve

Figure 2. Negative TLP Curve

TPD4E02B04

ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016

www.ti.com.cn

Typical Characteristics (continued)

160

140

120

100

Current

Power

2.5

1.5

0.5

-20

-5

-25

75 100 125 150 175 200 225

Time (ms)

Time (ns)

D001

Figure 3. Surge Curve (t_p= 8/20µs), any IO pin to GND

Figure 4. 8-kV IEC Waveform

0.5

0.45

0.4

-20

-40

-60

-80

0.35

0.3

0.25

0.2

-100

0.15

0.1

-120

-140

-160

0.05

-25

75 100 125 150 175 200 225

Time (ns)

-3.6 -3 -2.4 -1.8 -1.2 -0.6

0.6 1.2 1.8 2.4

3.6

Bias Voltage (V)

D001

Figure 5. –8-kV IEC Waveform

Figure 6. Capacitance vs. Bias Voltage

0.5

0.45

0.4

0.6

0.5

0.4

0.3

0.2

0.1

Bias = -2.5V

Bias = 2.5V

0.35

0.3

0.25

0.2

0.15

0.1

0.05

-40 -25 -10

20 35 50 65 80 95 110 125

Ambient Temperature (èC)

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature (èC)

D001

Figure 7. Capacitance vs. Ambient Temperature

Figure 8. Leakage Current vs. Temperature

TPD4E02B04

www.ti.com.cn

ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016

Typical Characteristics (continued)

0.5

0.4

0.3

0.2

0.1

0.75

0.5

0.25

-0.25

-0.5

-0.75

-1

-7 -6 -5 -4 -3 -2 -1

6E+8

1E+9

2E+9

3E+9

5E+9 7E+9 1E+10

Voltage (V)

Frequency (Hz)

D001

Figure 9. DC Voltage Sweep I-V Curve

Figure 10. Capacitance vs. Frequency

-5

-10

-15

-20

-25

-30

-35

-40

-45

-50

-5

-10

10 20 30 40 50 60 70 80 90 100 110

Time (ns)

-10

10 20 30 40 50 60 70 80 90 100 110

Time (ns)

D001

Figure 11. 8-kV IEC Waveform through 2m HDMI Cable

Figure 12. –8-kV IEC Waveform through 2m HDMI Cable

Figure 13. USB3.0 Eye Diagram (Bare Board)

Figure 14. USB3.0 Eye Diagram (with TPD4E02B04)

TPD4E02B04

ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016

www.ti.com.cn

Typical Characteristics (continued)

Figure 15. USB3.1 Gen 2 Eye Diagram (Bare Board)

Figure 16. USB3.1 Gen 2 Eye Diagram (with TPD4E02B04)

Figure 17. HDMI2.0 6Gbps TP2 Eye Diagram (Bare Board)

Figure 18. HDMI2.0 6Gbps TP2 Eye Diagram (with

TPD4E02B04)

-3

-6

-9

3E+5

1E+6

1E+7

1E+8

1E+9

1E+12E+1

D001

Frequency (Hz)

Figure 19. Differential Insertion Loss

TPD4E02B04

www.ti.com.cn

ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016

7 Detailed Description

7.1 Overview

The TPD4E02B04 is a bidirectional ESD Protection Diode with ultra-low capacitance. This device can dissipate

ESD strikes above the maximum level specified by the IEC 61000-4-2 International Standard. The ultra-low

capacitance makes this device ideal for protecting any super high-speed signal pins.

7.2 Functional Block Diagram

Lh1

Lh2

Lh3

Lh4

Db5

7.3 Feature Description

7.3.1 IEC 61000-4-2 ESD Protection

The I/O pins can withstand ESD events up to ±12-kV contact and ±15-kV air gap. An ESD/surge clamp diverts

the current to ground.

7.3.2 IEC 61000-4-4 EFT Protection

The I/O pins can withstand an electrical fast transient burst of up to 80 A (5/50 ns waveform, 4 kV with 50 Ω

impedance). An ESD/surge clamp diverts the current to ground.

7.3.3 IEC 61000-4-5 Surge Protection

The I/O pins can withstand surge events up to 2 A and 17 W (8/20 µs waveform). An ESD/surge clamp diverts

this current to ground.

7.3.4 IO Capacitance

The capacitance between each I/O pin to ground is 0.27 pF (typical) and 0.37 pF (maximum). This device

supports data rates up to 10 Gbps.

7.3.5 DC Breakdown Voltage

The DC breakdown voltage of each I/O pin is a minimum of ±5.5 V. This ensures that sensitive equipment is

protected from surges above the reverse standoff voltage of ±3.6 V.

7.3.6 Ultra Low Leakage Current

The I/O pins feature an ultra-low leakage current of 10 nA (max) with a bias of ±2.5 V

7.3.7 Low ESD Clamping Voltage

The I/O pins feature an ESD clamp that is capable of clamping the voltage to 8.8 V (I_PP= 5 A).

7.3.8 Supports High Speed Interfaces

This device is capable of supporting high speed interfaces up to 10 Gbps, because of the extremely low IO

capacitance.

TPD4E02B04

ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016

www.ti.com.cn

Feature Description (continued)

7.3.9 Industrial Temperature Range

This device features an industrial operating range of –40°C to 125°C.

7.3.10 Easy Flow-Through Routing Package

The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers

flow-through routing, requiring minimal modification to an existing layout.

7.4 Device Functional Modes

The TPD4E02B04 is a passive integrated circuit that triggers when voltages are above V_BRFor below V_BRR

During ESD events, voltages as high as ±15 kV (air) can be directed to ground via the internal diode network.

When the voltages on the protected line fall below the trigger levels of TPD4E02B04 (usually within 10s of nano-

seconds) the device reverts to passive.

TPD4E02B04

www.ti.com.cn

ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPD4E02B04 is a diode type TVS which is used to provide a path to ground for dissipating ESD events on

high-speed signal lines between a human interface connector and a system. As the current from ESD passes

through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the

protected IC. The low R_DYNof the triggered TVS holds this voltage, V_CLAMP, to a safe level for the protected IC.

8.2 Typical Application

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Figure 20. USB 3.1 Gen 2 Type-C ESD Schematic

TPD4E02B04

ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016

www.ti.com.cn

Typical Application (continued)

Figure 21. USB 3.1 Gen 2 SuperSpeed Layout

8.2.1 Design Requirements

For this design example two TPD4E02B04 devices and two TPD4E05U06 devices are being used in a USB 3.1

Gen 2 Type-C application. This will provide a complete ESD protection scheme.

Given the USB 3.1 Gen 2 Type-C application, the parameters listed in Table 1 are known.

Table 1. Design Parameters

DESIGN PARAMETER

VALUE

0 V to 3.6 V

5 GHz

Signal Range on SuperSpeed+ Lines

Operating Frequency on SuperSpeed+ Lines

Signal Range on CC, SBU, and DP/DM

Lines

0 V to 5 V

Operating Frequency on CC, SBU, and

DP/DM Lines

up to 480 MHz

TPD4E02B04

www.ti.com.cn

ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016

8.2.2 Detailed Design Procedure

8.2.2.1 Signal Range

The TPD4E02B04 supports signal ranges between -3.6 V and 3.6 V, which supports the SuperSpeed+ pairs on

the USB Type-C application. The TPD4E05U06 supports signal ranges between 0 and 5.5 V, which supports the

CC, SBU, and DP/DM lines.

8.2.2.2 Operating Frequency

The TPD4E02B04 has a 0.27 pF (typ) capacitance, which supports the USB3.1 Gen 2 data rates of 10 Gbps.

The layout example in Figure 21 is intended to negate some of the loading capacitance of the TPD4E02B04 by

narrowing the traces slightly over the device itself. The TPD4E05U06 has a 0.5 pF (typical) capacitance, which

easily supports the CC, SBU, and DP/DM data rates.

8.2.3 Application Curves

Figure 22. USB 3.1 Gen 2 10Gbps Eye Diagram (Bare

Board)

Figure 23. USB 3.1 Gen 2 10Gbps Eye Diagram (with

TPD4E02B04)

TPD4E02B04

ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016

www.ti.com.cn

9 Power Supply Recommendations

This device is a passive ESD device so there is no need to power it. Take care not to violate the recommended

I/O specification (-3.6 V to 3.6 V) to ensure the device functions properly.

10 Layout

10.1 Layout Guidelines

•

The optimum placement is as close to the connector as possible.

–

EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,

resulting in early system failures.

–

The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces

away from the protected traces which are between the TVS and the connector.

•

Route the protected traces as straight as possible.

Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded

corners with the largest radii possible.

–

Electric fields tend to build up on corners, increasing EMI coupling.

10.2 Layout Examples

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TPD4E02B04

www.ti.com.cn

ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016

Layout Examples (continued)

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TPD4E02B04

ZHCSEN2A –NOVEMBER 2015–REVISED FEBRUARY 2016

www.ti.com.cn

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档ꢀ

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TPD4E02B04DQAR产品参数

型号:	TPD4E02B04DQAR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
包装说明：	R-PDSO-N10
Reach Compliance Code：	compliant
ECCN代码：	EAR99
Factory Lead Time：	8 weeks
风险等级：	1.74
最大击穿电压：	7.5 V
最小击穿电压：	5.5 V
击穿电压标称值：	6.4 V
配置：	COMPLEX
二极管元件材料：	SILICON
二极管类型：	TRANS VOLTAGE SUPPRESSOR DIODE
JESD-30 代码：	R-PDSO-N10
JESD-609代码：	e4
湿度敏感等级：	1
最大非重复峰值反向功率耗散：	17 W
元件数量：	4
端子数量：	10
最高工作温度：	125 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
极性：	BIDIRECTIONAL
参考标准：	IEC-61000-4-2, 4-4, 4-5
最大重复峰值反向电压：	3.6 V
表面贴装：	YES
技术：	AVALANCHE
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	NO LEAD
端子位置：	DUAL
Base Number Matches：	1

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