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  • 北京元坤伟业科技有限公司

         该会员已使用本站17年以上

  • TPL5010DDCR
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  • 深圳市恒达亿科技有限公司

     该会员已使用本站12年以上
  • TPL5010DDCR 现货库存
  • 数量5000 
  • 厂家TI 
  • 封装SOT23-6 
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  • 集好芯城

     该会员已使用本站13年以上
  • TPL5010DDCR 现货库存
  • 数量18335 
  • 厂家TI(德州仪器) 
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  • 深圳市勤思达科技有限公司

     该会员已使用本站14年以上
  • TPL5010DDCR 现货库存
  • 数量6000 
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  • 封装SOT23-6 
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  • 深圳市宏捷佳电子科技有限公司

     该会员已使用本站6年以上
  • TPL5010DDCR 现货库存
  • 数量5300 
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  • 深圳市英德州科技有限公司

     该会员已使用本站2年以上
  • TPL5010DDCR 现货库存
  • 数量32500 
  • 厂家TI(德州仪器) 
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  • 深圳市恒达亿科技有限公司

     该会员已使用本站16年以上
  • TPL5010DDCR 现货库存
  • 数量8740 
  • 厂家TI 
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     该会员已使用本站10年以上
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  • 数量8000 
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  • 数量26800 
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  • 深圳市西昂特科技有限公司

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  • 数量30000 
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  • 深圳市驰天熠电子有限公司

     该会员已使用本站1年以上
  • TPL5010DDCR 现货库存
  • 数量38455 
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     该会员已使用本站11年以上
  • TPL5010DDCR 现货库存
  • 数量3000 
  • 厂家TI 
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  • 深圳市炎凯科技有限公司

     该会员已使用本站7年以上
  • TPL5010DDCR 现货库存
  • 数量8882 
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     该会员已使用本站6年以上
  • TPL5010DDCR 现货库存
  • 数量18500 
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     该会员已使用本站7年以上
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  • 数量14324 
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  • 深圳市富科达科技有限公司

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  • TPL5010DDCR 优势库存
  • 数量21688 
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  • 封装SOT23-6 
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  • 上海意淼电子科技有限公司

     该会员已使用本站14年以上
  • TPL5010DDCR 优势库存
  • 数量20000 
  • 厂家TI 
  • 封装SOT23-6 
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  • 原装现货热卖!请联系吴先生 13681678667
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  • 深圳市欧瑞芯科技有限公司

     该会员已使用本站11年以上
  • TPL5010DDCR 优势库存
  • 数量5800 
  • 厂家TI/德州仪器 
  • 封装SOT23-6 
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  • 上海意淼电子科技有限公司

     该会员已使用本站14年以上
  • TPL5010DDCR 热卖库存
  • 数量20000 
  • 厂家TI 
  • 封装SOT23-6 
  • 批号23+ 
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  • 深圳市拓森弘电子有限公司

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  • TPL5010DDCR
  • 数量6000 
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  • TPL5010DDCR
  • 数量9328 
  • 厂家TI-德州仪器 
  • 封装SOT-23-6 
  • 批号▉▉:2年内 
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  • 深圳市美思瑞电子科技有限公司

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  • 数量9000 
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  • 深圳市得捷芯城科技有限公司

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  • 数量16048 
  • 厂家TI(德州仪器) 
  • 封装SOT23-6 
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  • 深圳市积美福电子科技有限公司

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  • TPL5010DDCR
  • 数量6000 
  • 厂家TI/德州仪器 
  • 封装SOT-23 
  • 批号21+ 
  • 自己原包装现货 实单|原装| 现货
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  • 深圳市芯鹏泰科技有限公司

     该会员已使用本站8年以上
  • TPL5010DDCR
  • 数量8635 
  • 厂家Texas Instruments 
  • 封装SOT-23-THIN 
  • 批号23+ 
  • 时钟/定时 - 可编程定时器和振荡器
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  • 深圳市得捷芯城科技有限公司

     该会员已使用本站11年以上
  • TPL5010DDCR
  • 数量115240 
  • 厂家TI/德州仪器 
  • 封装NA/ 
  • 批号23+ 
  • 原装现货,当天可交货,原型号开票
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  • 北京耐芯威科技有限公司

     该会员已使用本站12年以上
  • TPL5010DDCR
  • 数量5000 
  • 厂家Texas Instruments 
  • 封装TSOT-23-6 
  • 批号21+ 
  • 全新原装、现货库存,欢迎询价
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  • 深圳市芯福林电子有限公司

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  • TPL5010DDCR
  • 数量98500 
  • 厂家TI 
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  • 深圳市华芯盛世科技有限公司

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  • TPL5010DDCR
  • 数量865000 
  • 厂家TI/德州仪器 
  • 封装20+ 
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  • 北京耐芯威科技有限公司

     该会员已使用本站13年以上
  • TPL5010DDCR
  • 数量5000 
  • 厂家Texas Instruments 
  • 封装TSOT-23-6 
  • 批号21+ 
  • 全新原装、现货库存,欢迎询价
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  • TPL5010DDCR
  • 数量7500 
  • 厂家TI/德州仪器 
  • 封装SOT-23-6 
  • 批号24+ 
  • 原装进口正品现货,假一罚十价格优势
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  • 数量5000 
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  • 封装SOT23-6 
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  • 羿芯诚只做原装 原厂渠道 价格优势
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  • 集好芯城

     该会员已使用本站13年以上
  • TPL5010DDCR
  • 数量16297 
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  • 封装SOT23-6 
  • 批号最新批次 
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  • 深圳市宏世佳电子科技有限公司

     该会员已使用本站13年以上
  • TPL5010DDCR
  • 数量5185 
  • 厂家TI 
  • 封装SOT-23-THIN 
  • 批号2023+ 
  • 全新原厂原装产品、公司现货销售
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  • 深圳市一呈科技有限公司

     该会员已使用本站9年以上
  • TPL5010DDCR
  • 数量5280 
  • 厂家TI(德州仪器) 
  • 封装SOT-23-Thin-6 
  • 批号23+ 
  • ▉原装正品▉力挺实单可含税可拆样
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  • 上海磐岳电子有限公司

     该会员已使用本站11年以上
  • TPL5010DDCR
  • 数量120000 
  • 厂家TI 
  • 封装 
  • 批号2024+ 
  • 全新原装现货,杜绝假货。
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  • TPL5010DDCR
  • 数量12600 
  • 厂家TI/德州仪器 
  • 封装SOT23-6 
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  • TPL5010DDCR
  • 数量30000 
  • 厂家TI/德州仪器 
  • 封装SOT23-6 
  • 批号23+ 
  • 全新原装代理现货,假一赔十
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产品型号TPL5010DDCR的概述

TPL5010DDCR概述 TPL5010DDCR是一款由Texas Instruments(德州市仪器公司)制造的低功耗、可编程延迟定时器。该芯片主要用于各种需要延迟功能的应用场景,具有快速的响应时间和出色的能效,非常适合在电池供电的设备中使用。TPL5010DDCR特别设计用于能够提供多种时间延迟设置的设备,能够满足不同的应用需求,从而使用户能够根据不同的工作环境来调节和优化性能。 详细参数 TPL5010DDCR的主要参数包括: - 工作电压范围: 1.8V至5.5V - 待机电流: 1µA(典型值) - 定时范围: 0.25秒至16分钟 - 定时精度: ±10% - 引脚配置: 8引脚VSSOP封装 - 温度范围: -40°C至85°C 该芯片支持多种外部电阻和电容的选择,从而使得用户可以通过简单的外部元件配置来实现不同的定时功能。 厂家、包装、封装 TPL5010DDCR由...

产品型号TPL5010DDCR的Datasheet PDF文件预览

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TPL5010  
ZHCSEK6A JANUARY 2015REVISED SEPTEMBER 2018  
具有看门狗功能的 TPL5010 纳瓦级功耗系统计时器  
1 特性  
3 说明  
1
电源电压范围为 1.8V 5.5V  
TPL5010 纳瓦级计时器是一款超低功耗计时器,其看  
门狗功能专为占空比、电池供电型 应用 (比如物联网  
中的应用)中的系统唤醒功能而设计。其中许多 应用  
需要使用 μC,因此,通常希望将 μC 维持在低功耗模  
式以更大限度节省电流,而仅在某些时间间隔内唤醒以  
收集数据或为中断提供服务。虽然 μC 的内部计时器可  
用于系统唤醒,但它可能单独消耗数微安的总系统电  
流。  
电压为 2.5V 时,电流消耗为 35nA(典型值)  
可选计时间隔:100ms 7200s  
计时器精度:1%(典型值)  
可通过电阻选择时间间隔  
看门狗功能  
手动复位  
2 应用  
TPL5010 仅消耗 35nA,可替代集成式 μC 计时器的功  
能。这样就可将 μC 置于低得多的功耗模式,将内部计  
时器关闭,并在被 TPL5010 中断时仅返回到激活模  
式。TPL5010 通过提供近两个数量级的功率节省,可  
以大幅减小能量采集或无线传感器 应用中所使用的电  
池尺寸。TPL5010 提供 100ms 7200s 的可选时间  
间隔,适用于中断驱动型 应用。出于安全考虑,某些  
标准(如 EN50271)要求实现看门狗功能。TPL5010  
不仅实现了看门狗功能,而且几乎没有增加功耗。  
TPL5010 采用 6 引脚小外形尺寸晶体管 (SOT23) 封  
装。  
电池供电系统  
物联网 (IoT)  
出入探测  
篡改检测  
家庭自动化传感器  
温度调节装置  
消费类电子产品  
远程传感器  
白色家电  
器件信息(1)  
器件编号  
TPL5010  
封装  
SOT23 (6)  
封装尺寸(标称值)  
3.00mm × 3.00mm  
(1) 如需了解所有可用封装,请参阅产品说明书末尾的可订购产品  
附录。  
简化应用电路原理图  
µC  
VOUT  
VIN  
Rp  
TPL5010  
RSTn  
VDD  
VDD  
GND  
RSTn  
GPIO  
GPIO  
Battery  
POWER MANAGEMENT  
GND  
WAKE  
DONE  
DELAY/  
M_RST  
REXT  
GND  
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确  
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。  
English Data Sheet: SNAS651  
 
 
 
TPL5010  
ZHCSEK6A JANUARY 2015REVISED SEPTEMBER 2018  
www.ti.com.cn  
目录  
8.3 Feature Description................................................... 9  
8.4 Device Functional Modes........................................ 10  
8.5 Programming .......................................................... 10  
Application and Implementation ........................ 16  
9.1 Application Information............................................ 16  
9.2 Typical Application ................................................. 16  
1
2
3
4
5
6
7
特性.......................................................................... 1  
应用.......................................................................... 1  
说明.......................................................................... 1  
修订历史记录 ........................................................... 2  
器件比较............................................................... 3  
Pin Configuration and Functions......................... 4  
Specifications......................................................... 5  
7.1 Absolute Maximum Ratings ...................................... 5  
7.2 ESD Ratings.............................................................. 5  
7.3 Recommended Operating Ratings ........................... 5  
7.4 Thermal Information ................................................. 5  
7.5 Electrical Characteristics........................................... 6  
7.6 Timing Requirements ............................................... 7  
7.7 Typical Characteristics.............................................. 8  
Detailed Description .............................................. 9  
8.1 Overview ................................................................... 9  
8.2 Functional Block Diagram ......................................... 9  
9
10 Power Supply Recommendations ..................... 18  
11 Layout................................................................... 18  
11.1 Layout Guidelines ................................................. 18  
11.2 Layout Example .................................................... 18  
12 器件和文档支持 ..................................................... 19  
12.1 接收文档更新通知 ................................................. 19  
12.2 社区资源................................................................ 19  
12.3 ....................................................................... 19  
12.4 静电放电警告......................................................... 19  
12.5 术语表 ................................................................... 19  
13 机械、封装和可订购信息....................................... 19  
8
4 修订历史记录  
Changes from Original (January 2015) to Revision A  
Page  
添加了 TPL5x1x 系列纳瓦级计时器................................................................................................................................... 3  
Changed TADC and RD equations in the Quantization Error section..................................................................................... 14  
添加了接收文档更新通知部分 ............................................................................................................................................... 19  
2
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TPL5010  
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5 器件比较表  
TPL5x1x 系列纳瓦级计时器  
输出  
器件编号  
TPL5010  
TPL5010Q  
特殊 特性  
评分  
目录  
汽车  
低功耗计时器、看门狗功能  
低功耗计时器、看门狗功能  
高电平有效  
高电平有效  
低功耗计时器、电源门控  
MOS 驱动器  
TPL5111  
TPL5110  
高电平有效  
低电平有效  
目录  
目录  
低功耗计时器、电源门控  
MOS 驱动器  
Copyright © 2015–2018, Texas Instruments Incorporated  
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TPL5010  
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6 Pin Configuration and Functions  
DDC Package  
6-Lead SOT-23  
Top View  
TPL5010  
1
2
3
VDD  
RSTn  
WAKE  
DONE  
6
5
4
GND  
DELAY/  
M_RST  
Pin Functions  
PIN  
TYPE(1)  
DESCRIPTION  
APPLICATION INFORMATION  
NO.  
1
NAME  
VDD  
P
G
I
Supply voltage  
Ground  
2
GND  
3
DELAY/  
M_RST  
Time Interval set and Manual Reset Resistance between this pin and GND is used to  
select the time interval. The reset switch is also  
connected to this pin.  
4
5
6
DONE  
WAKE  
RSTn  
I
Logic Input for watchdog  
functionality  
Digital signal driven by the µC to indicate successful  
processing of the WAKE signal.  
O
O
Timer output signal generated every Digital pulsed signal to wake up the µC at the end of  
tIP period.  
the programmed time interval.  
Reset Output (open drain output)  
Digital signal to RESET the µC, pullup resistance is  
required  
(1) G= Ground, P= Power, O= Output, I= Input.  
4
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TPL5010  
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ZHCSEK6A JANUARY 2015REVISED SEPTEMBER 2018  
7 Specifications  
7.1 Absolute Maximum Ratings(1)  
MIN  
–0.3  
–0.3  
–5  
MAX  
6
UNIT  
V
Supply Voltage (VDD-GND)  
Input Voltage at any pin(2)  
Input Current on any pin  
Junction Temperature, TJ(3)  
Storage Temperature, Tstg  
VDD + 0.3  
+5  
V
mA  
°C  
150  
–65  
150  
°C  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended  
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The voltage between any two pins should not exceed 6V.  
(3) The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power  
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a  
printed-circuit board (PCB).  
7.2 ESD Ratings  
VALUE  
±1000  
±250  
UNIT  
Human Body Model, per ANSI/ESDA/JEDEC JS-001(1)  
Charged-device model (CDM), per JEDEC specification JESD22-101(2)  
V(ESD)  
Electrostatic discharge  
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
7.3 Recommended Operating Ratings  
MIN  
MAX  
5.5  
UNIT  
V
Supply Voltage (VDD-GND)  
Temperature  
1.8  
–40  
105  
°C  
7.4 Thermal Information  
TPL5010  
THERMAL METRIC(1)  
DDC (SOT-23)  
UNIT  
6 PINS  
163  
26  
RθJA  
Junction-to-ambient thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
57  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
7.5  
ψJB  
57  
RθJC(bot)  
N/A  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report (SPRA953).  
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TPL5010  
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7.5 Electrical Characteristics(1)  
Specifications are for TA= 25°C, VDD-GND = 2.5 V, unless otherwise stated.  
PARAMETER  
TEST CONDITIONS  
MIN(2)  
TYP(3)  
MAX(2) UNIT  
POWER SUPPLY  
IDD  
Supply current(4)  
Operation mode  
35  
50  
nA  
µA  
Digital conversion of external  
resistance (Rext)  
200  
400  
TIMER  
tIP  
Time Interval Period  
1650 selectable  
Time Intervals  
Minimum time  
interval  
100  
ms  
s
Maximum time  
interval  
7200  
Time Interval Setting Accuracy(5)  
Excluding the precision of Rext  
±0.6%  
±25  
Timer Interval Setting Accuracy over 1.8 V VDD 5.5 V  
ppm/V  
supply voltage  
tOSC  
Oscillator Accuracy  
–0.5%  
0.5%  
Oscillator Accuracy over  
temperature(6)  
–40°C TA 105°C  
1.8 V VDD 5.5 V  
±100  
±0.4  
±400 ppm/°C  
Oscillator Accuracy over supply  
voltage  
%/V  
Oscillator Accuracy over life time(7)  
0.24%  
(6)  
tDONE  
tRSTn  
DONE Pulse width  
100  
ns  
ms  
ms  
RSTn Pulse width  
WAKE Pulse width  
Time to convert Rext  
320  
20  
tWAKE  
t_Rext  
100  
120  
ms  
DIGITAL LOGIC LEVELS  
VIH  
VIL  
Logic High Threshold DONE pin  
0.7 × VDD  
V
V
Logic Low Threshold DONE pin  
0.3 ×  
VDD  
Iout = 100 µA  
Iout = 1 mA  
VDD – 0.3  
VDD – 0.7  
V
V
VOH  
VOL  
Logic output High Level WAKE pin  
Logic output Low Level WAKE pin  
Iout = -100 µA  
Iout = –1 mA  
IOL = –1 mA  
VOHRSTn = VDD  
0.3  
0.7  
0.3  
V
V
VOLRSTn  
IOHRSTn  
VIHM_RST  
RSTn Logic output Low Level  
RSTn High Level output current  
V
1
nA  
V
Logic High Threshold  
DELAY/M_RST pin  
1.5  
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in  
very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables  
under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which  
the device may be permanently degraded, either mechanically or electrically.  
(2) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through  
correlations using statistical quality control (SQC) method.  
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary  
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped  
production material.  
(4) The supply current excludes load and pullup resistor current. Input pins are at GND or VDD.  
(5) The accuracy for time interval settings below 1 second is ±100 ms.  
(6) This parameter is specified by design and/or characterization and is not tested in production.  
(7) Operational life time test procedure equivalent to 10 years.  
6
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TPL5010  
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ZHCSEK6A JANUARY 2015REVISED SEPTEMBER 2018  
7.6 Timing Requirements  
MIN(1) NOM(2) MAX(1) UNIT  
(3)  
trRSTn  
tfRSTn  
trWAKE  
tfWAKE  
Rise Time RSTn  
Fall Time RSTn  
Capacitive load 50 pF, Rpullup 100 kΩ  
Capacitive load 50 pF, Rpullup 100 kΩ  
Capacitive load 50 pF  
11  
50  
µs  
ns  
ns  
ns  
ns  
(3)  
(3)  
Rise Time WAKE  
Fall Time WAKE  
50  
(3)  
Capacitive load 50 pF  
Minimum delay(4)  
50  
100  
DONE to RSTn or WAKE to DONE  
delay  
tDDONE  
tIP-  
(4)  
Maximum delay  
ms  
20ms  
tM_RST  
tDB  
Valid Manual Reset  
Observation time 30 ms  
20  
ms  
ms  
De-bounce Manual Reset  
20  
(1) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through  
correlations using statistical quality control (SQC) method.  
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary  
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped  
production material.  
(3) This parameter is specified by design and/or characterization and is not tested in production.  
(4) In case of RSTn from its falling edge, or in case of WAKE from its rising edge.  
VDD  
ttWAKE  
t
trWAKE  
WAKE  
DONE  
RSTn  
ttIPt  
ttDDONEt  
tfWAKE  
tDONE  
ttRSTn+ tIP  
t
trRSTn  
ttRSTn+tDB  
t
ttRSTnt  
ttR_EXT + tRSTn  
t
tfRSTn  
DELAY/  
M_RST  
ttM_RST  
Figure 1. TPL5010 Timing  
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TPL5010  
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7.7 Typical Characteristics  
80  
80  
70  
60  
50  
40  
30  
20  
TA= -40°C  
TA= 25°C  
TA= 70°C  
VDD= 1.8V  
VDD= 2.5V  
VDD= 3.3V  
VDD= 5.5V  
70  
60  
50  
40  
30  
20  
TA= 105°C  
1.5  
1.9  
2.3  
2.7  
3.1  
3.5  
3.9  
4.3  
4.7  
5.1  
5.5  
5.5  
1
-40  
-25  
-10  
5
20  
35  
50  
65  
80  
95  
110  
Supply Voltage (V)  
Temperature (°C)  
Figure 2. IDD vs. VDD  
Figure 3. IDD vs. Temperature  
2
1.5  
1
2
1.5  
1
TA= -40°C  
TA= 25°C  
TA= 70°C  
TA= 105°C  
VDD= 1.8V  
VDD= 2.5V  
VDD= 3.3V  
VDD= 5.5V  
0.5  
0
0.5  
0
-0.5  
-1  
-0.5  
-1  
1.5  
1.9  
2.3  
2.7  
3.1  
3.5  
3.9  
4.3  
4.7  
5.1  
-40  
-25  
-10  
5
20  
35  
50  
65  
80  
95  
110  
Supply Voltage (V)  
Temperature (°C)  
Figure 4. Oscillator Accuracy vs. VDD  
Figure 5. Oscillator Accuracy vs. Temperature  
1000  
100  
10  
40%  
POR  
REXT READING  
35%  
30%  
25%  
20%  
15%  
10%  
5%  
1
TIMER MODE  
0.1  
0.01  
0
0
0.1  
0.2  
0.3  
0.4  
0.5  
Time (s)  
0.6  
0.7  
0.8  
0.9  
-1  
-0.8  
-0.6  
-0.4  
-0.2  
0
0.2  
0.4  
0.6  
0.8  
Accuracy (%)  
number of  
1s < tIP 7200s  
observations  
>20000  
Figure 7. Time Interval Setting Accuracy  
Figure 6. IDD vs. Time  
8
Copyright © 2015–2018, Texas Instruments Incorporated  
TPL5010  
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ZHCSEK6A JANUARY 2015REVISED SEPTEMBER 2018  
8 Detailed Description  
8.1 Overview  
The TPL5010 is a system wake-up timer with a watchdog feature designed for low-power applications. The  
TPL5010 can be used in interrupt-driven applications and provides selectable timing from 100 ms to 7200 s.  
8.2 Functional Block Diagram  
VDD  
RSTn  
LOW FREQUENCY  
OSCILLATOR  
FREQUENCY  
DIVIDER  
LOGIC  
CONTROL  
WAKE  
DONE  
DELAY/  
M_RST  
DECODER  
&
MANUAL RESET  
DETECTOR  
GND  
8.3 Feature Description  
The DONE, WAKE and RSTn signals are used to implement the watchdog function. The TPL5010 is  
programmed to issue a periodic WAKE pulse to a µC which is in sleep or standby mode. After receiving the  
WAKE pulse, the µC must issue a DONE signal to the TPL5010 at least 20 ms before the rising edge of the next  
WAKE pulse. If the DONE signal is not asserted, the TPL5010 asserts the RSTn signal to reset the µC. A  
manual reset function is realized by momentarily pulling the DELAY/M_RST pin to VDD.  
ttIPt  
ttIPt  
WAKE  
DONE  
RSTn  
MISSED  
DONE  
ttRSTn+ tIPt  
DELAY/  
M_RST  
Figure 8. Watchdog  
8.3.1 WAKE  
The WAKE pulse is sent out from the TPL5010 when the programmed time interval starts (except at the  
beginning of the first cycle or if in the previous interval the DONE has not been received).  
This signal is normally low.  
8.3.2 DONE  
The DONE pin is driven by a µC to signal successful processing of the WAKE signal. The TPL5010 recognizes a  
valid DONE signal as a low to high transition. If two or more DONE signals are received within the time interval,  
only the first DONE signal is processed.  
The DONE signal resets the counter of the watchdog only. If the DONE signal is received when the WAKE is still  
high, the WAKE will go low as soon as the DONE is recognized.  
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Feature Description (continued)  
8.3.3 RSTn  
To implement the reset interface between the TPL5010 and the µC a pullup resistance is required. 100 KΩ is  
recommended to minimize current.  
During the POR and the reading of the REXT, the RSTn signal is LOW.  
RSTn is asserted (LOW) for either one of the following conditions:  
1. If the DELAY/M_RST pin is high for at least two consecutive cycles of the internal oscillator (approximately  
20 ms).  
2. At the beginning of a new time interval if DONE is not received at least 20 ms before the next WAKE rising  
edge (see Figure 8).  
8.4 Device Functional Modes  
8.4.1 Start-Up  
During start-up after POR, the TPL5010 executes a one-time measurement of the resistance attached to the  
DELAY/M_RST pin to determine the desired time interval for WAKE. This measurement interval is tR_EXT. During  
this measurement, a constant current is temporarily flowing into REXT  
.
ttR_EXT + tRSTn + tIPt  
ttIPt  
WAKE  
DONE  
RSTn  
DELAY/  
M_RST  
RESISTANCE  
POR  
READING  
Figure 9. Start-Up  
8.4.2 Normal Operating Mode  
During normal operating mode, the TPL5010 asserts periodic WAKE pulses in response to valid DONE pulses  
from the µC. If either a manual reset is applied (logic HIGH on DELAY/M_RST pin), or the µC does not issue a  
DONE pulse within the required time, the TPL5010 asserts the RSTn signal to the µC and restarts its internal  
counters. See Figure 8 and Figure 10 .  
8.5 Programming  
8.5.1 Configuring the WAKE Interval With the DELAY/M_RST Pin  
The time interval between two adjacent WAKE pulses (rising edges) is selectable through an external resistance  
(REXT) between the DELAY/M_RST pin and ground. The value of the resistance REXT is converted one time after  
POR. The allowable range of REXT is 500 Ω to 170 kΩ. At least a 1% precision resistance is recommended. See  
section Timer Interval Selection Using External Resistance on how to set the WAKE pulse interval using REXT  
.
The time between two adjacent RESET signals (falling edges), or between a RESET (falling edge) and a WAKE  
(rising edge), is given by the sum of the programmed time interval and the tRSTn (reset pulse width).  
10  
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Programming (continued)  
8.5.2 Manual Reset  
If VDD is connected to the DELAY/M_RST pin, the TPL5010 recognizes this as a manual reset condition. In this  
case, the time interval is not set. If the manual reset is asserted during the POR or during the reading procedure,  
the reading procedure is aborted and is restarted as soon as the manual reset switch is released. A pulse on the  
DELAY/M_RST pin is recognized as a valid manual reset only if it lasts at least 20 ms (observation time is 30  
ms).  
A valid manual reset resets all the counters inside the TPL5010. The counters restart only when the high digital  
voltage at DELAY/M_RST is removed and the next tRSTn is elapsed.  
ttIPt  
WAKE  
DONE  
ttRSTn+ tIPt  
RSTn  
ANY RESET  
ttM_RST  
t
ttDB  
t
ttM_RSTt  
DELAY/  
M_RST  
VALID M_RST  
NOT VALID M_RST  
Figure 10. Manual Reset  
8.5.2.1 DELAY/M_RST  
A resistance in the range between 500 Ω and 170 kΩ needs to be connected to select a valid time interval. At the  
POR and during the reading of the resistance the DELAY/M_RST is connected to an analog signal chain though  
a mux. After the reading of the resistance the analog circuit is switched off and the DELAY/RST is connected to  
a digital circuit.  
The manual reset detection is supported with a de-bounce feature which makes the TPL5010 insensitive to the  
glitches on the DELAY/M_RST pin. When a valid manual reset signal is asserted on the DELAY/M_RST pin, the  
RSTn signal is asserted LOW after a delay of tM_RST. It remains LOW after a valid manual reset is asserted + tDB  
+ tRSTn. Due to the asynchronous nature of the manual reset signal and its arbitrary duration, the LOW status of  
the RSTn signal maybe affected by an uncertainty of about ±5 ms.  
A valid manual reset puts all the digital output signals at their default values:  
WAKE = LOW  
RSTn = asserted LOW  
8.5.2.2 Circuitry  
The manual reset may be implemented using a switch (momentary mechanical action). The TPL5010 offers two  
possible approaches according to the power consumption constraints of the application.  
Copyright © 2015–2018, Texas Instruments Incorporated  
11  
TPL5010  
ZHCSEK6A JANUARY 2015REVISED SEPTEMBER 2018  
www.ti.com.cn  
Programming (continued)  
µC  
VOUT  
VIN  
Rp  
TPL5010  
RSTn  
VDD  
VDD  
GND  
RSTn  
GPIO  
GPIO  
Battery  
POWER MANAGEMENT  
WAKE  
DONE  
DELAY/  
M_RST  
REXT  
GND  
GND  
Figure 11. Manual Reset With SPST Switch  
For use cases that do not require the lowest power consumption, using a single-pole single-throw switch may  
offer a lower-cost solution. The DELAY/M_RST pin may be directly connected to VDD with REXT in the circuit.  
The current drawn from the supply voltage during the reset is given by VDD/REXT  
.
µC  
VOUT  
Rp  
TPL5010  
RSTn  
VIN  
VDD  
VDD  
GND  
RSTn  
GPIO  
GPIO  
Battery  
POWER MANAGEMENT  
GND  
WAKE  
DONE  
DELAY/  
M_RST  
REXT  
GND  
Figure 12. Manual Reset With SPDT Switch  
The reset function may also be asserted by switching DELAY/M_RST from REXT to VDD using a single-pole  
double-throw switch, which will provide a lower power solution for the manual reset, because no current flows.  
8.5.3 Timer Interval Selection Using External Resistance  
To set the time interval, the external resistance REXT is selected according to Equation 1:  
- b + b 2 - 4a  
2a  
(
c -100 T  
)
÷
REXT =100  
«
÷
where  
T is the desired time interval in seconds.  
REXT is the resistance value to use in Ω.  
a, b, and c are coefficients depending on the range of the time interval.  
(1)  
12  
Copyright © 2015–2018, Texas Instruments Incorporated  
 
TPL5010  
www.ti.com.cn  
ZHCSEK6A JANUARY 2015REVISED SEPTEMBER 2018  
Programming (continued)  
Table 1. Coefficients for Equation 1  
Time interval  
Range (s)  
SET  
a
b
c
1
2
3
4
5
1 < T 5  
0.2253  
–0.1284  
0.1972  
0.2617  
0.3177  
–20.7654  
46.9861  
570.5679  
–2651.8889  
692.1201  
5 < T 10  
10 < T 100  
100 < T 1000  
T > 1000  
–19.3450  
–56.2407  
–136.2571  
5957.7934  
34522.4680  
EXAMPLE  
Required time interval: 8 s  
The coefficient set to be selected is the number 2. The formula becomes Equation 2.  
2
46.9861- 46.9861 +4*0.1284  
(
-2561.8889-100*8  
)
÷
REXT =100  
«
÷
2*0.1284  
(2)  
The resistance value is 10.18 k.  
Table 2 and Table 3 contain example values of tIP and their corresponding value of REXT  
.
Table 2. First 9 Time Intervals  
Parallel of Two 1% Tolerance  
tIP (ms)  
Resistance (Ω)  
Closest Real Value (Ω)  
Resistors, (kΩ)  
100  
200  
300  
400  
500  
600  
700  
800  
900  
500  
500  
1.0 // 1.0  
-
1000  
1500  
2000  
2500  
3000  
3500  
4000  
4500  
1000  
1500  
2000  
2500  
3000  
3500  
4000  
4501  
2.43 // 3.92  
-
4.42 // 5.76  
5.36 // 6.81  
4.75 // 13.5  
6.19 // 11.3  
6.19 // 16.5  
Table 3. Most Common Time Intervals Between 1s to 2h  
Closest Real Value  
Parallel of Two 1% Tolerance Resistors,  
tIP  
Calculated Resistance (kΩ)  
(kΩ)  
(kΩ)  
1s  
2s  
5.20  
6.79  
5.202  
6.788  
7.15 // 19.1  
12.4 // 15.0  
12.7// 19.1  
14.7 // 19.1  
16.5 // 19.1  
18.2 // 18.7  
19.1 // 19.6  
11.5 // 8.87  
17.8 // 26.7  
15.0 // 44.2  
16.9 // 97.6  
32.4 // 34.8  
22.6 // 110.0  
28.7 // 66.5  
3s  
7.64  
7.628  
4s  
8.30  
8.306  
5s  
8.85  
8.852  
6s  
9.27  
9.223  
7s  
9.71  
9.673  
8s  
10.18  
10.68  
11.20  
14.41  
16.78  
18.75  
20.047  
10.180  
10.68  
9s  
10s  
20s  
30s  
40s  
50s  
11.199  
14.405  
16.778  
18.748  
20.047  
Copyright © 2015–2018, Texas Instruments Incorporated  
13  
 
 
 
 
TPL5010  
ZHCSEK6A JANUARY 2015REVISED SEPTEMBER 2018  
www.ti.com.cn  
Table 3. Most Common Time Intervals Between 1s to 2h (continued)  
Closest Real Value  
Parallel of Two 1% Tolerance Resistors,  
tIP  
Calculated Resistance (kΩ)  
(kΩ)  
(kΩ)  
1min  
2min  
3min  
4min  
5min  
6min  
7min  
8min  
9min  
10min  
20min  
30min  
40min  
50min  
1h  
22.02  
29.35  
34.73  
39.11  
42.90  
46.29  
49.38  
52.24  
54.92  
57.44  
77.57  
92.43  
104.67  
115.33  
124.91  
149.39  
170.00  
22.021  
29.349  
34.729  
39.097  
42.887  
46.301  
49.392  
52.224  
54.902  
57.437  
77.579  
92.233  
104.625  
115.331  
124.856  
149.398  
170.00  
40.2 // 48.7  
35.7 // 165.0  
63.4 // 76.8  
63.4 // 102.0  
54.9 // 196.0  
75.0 // 121.0  
97.6 // 100.0  
88.7 // 127.0  
86.6 // 150.0  
107.0 // 124.0  
140.0 // 174.0  
182.0 // 187.0  
130.0 // 536.00  
150.0 // 499.00  
221.0 // 287.00  
165.0 // 1580.0  
340.0 // 340.0  
1h30min  
2h  
8.5.4 Quantization Error  
The TPL5010 can generate 1650 discrete timer intervals in the range of 100 ms to 7200 s. The first 9 intervals  
are multiples of 100 ms. The remaining 1641 intervals cover the range between 1 s to 7200 s. Because they are  
discrete intervals, there is a quantization error associated with each value.  
The quantization error can be evaluated according to Equation 3:  
(
TDESIRED -TADC  
)
Err =100  
TDESIRED  
where  
1
é
ù
TADC = INT  
aR2 + bR + c  
(
)
D
D
ê
ú
100  
ë
û
REXT  
100  
RD  
=
(3)  
REXT is the resistance calculated with Equation 1 and a, b, c are the coefficients of the equation listed in Table 1.  
8.5.5 Error Due to Real External Resistance  
REXT is a theoretical value and may not be available in standard commercial resistor values. It is possible to  
closely approach the theoretical REXT using two or more standard values in parallel. However, standard values  
are characterized by a certain tolerance. This tolerance will affect the accuracy of the time interval.  
The accuracy can be evaluated using the following procedure:  
1. Evaluate the min and max values of REXT (REXT_MIN, REXT_MAX with Equation 1 using the selected commercial  
resistance values and their tolerances.  
2. Evaluate the time intervals (TADC_MIN[REXT_MIN], TADC_MAX[REXT_MAX]) with the TADC equation mentioned in  
Equation 3.  
3. Find the errors using Equation 3 with TADC_MIN, TADC_MAX  
.
The results of the formula indicate the accuracy of the time interval.  
14  
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ZHCSEK6A JANUARY 2015REVISED SEPTEMBER 2018  
The example below illustrates the procedure.  
Desired time interval, T_desired = 600 s,  
Required REXT from Equation 1, REXT= 57.44 kΩ.  
From Table 3 REXT can be built with a parallel combination of two commercial values with 1% tolerance: R1 =  
107 kΩ, R2 = 124 kΩ. The uncertainty of the equivalent parallel resistance can be found using Equation 4:  
2
2
u
u
R2  
R1 ’ ≈  
÷
uR =R//  
+
÷ ∆  
//  
R1  
R2  
«
◊ «  
where  
uRn (n=1,2) represent the uncertainty of a resistance (see Equation 5)  
(4)  
(5)  
SPACER  
Tolerance  
uR =Rn  
n
3
The uncertainty of the parallel resistance is 0.82%, which means the value of REXT may range between REXT_MIN  
= 56.96 kΩ and REXT_MAX = 57.90 kΩ.  
Using these value of REXT, the digitized timer intervals calculated by TADC equation mentioned in Equation 3 are  
respectively TADC_MIN = 586.85 s and TADC_MAX = 611.3 s, giving an error range of –1.88% / +2.19%. The  
asymmetry of the error range is due to the quadratic transfer function of the resistance digitizer.  
Copyright © 2015–2018, Texas Instruments Incorporated  
15  
 
 
TPL5010  
ZHCSEK6A JANUARY 2015REVISED SEPTEMBER 2018  
www.ti.com.cn  
9 Application and Implementation  
NOTE  
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test their design implementation to confirm system functionality.  
9.1 Application Information  
In battery-powered applications, one design constraint is the need for low current consumption. The TPL5010 is  
designed for applications where there is a need to monitor environmental conditions at a fixed time interval. Often  
in these applications a watchdog or other internal timer in a µC is used to implement a wake-up function. Using  
the TPL5010 to implement the watchdog function will consume only tens of nA, significantly improving the power  
consumption of the system.  
9.2 Typical Application  
The TPL5010 can be used in conjunction with environment sensors to build a low-power environment data-  
logger, such as an air quality data-logger. In this application, due to the monitored phenomena, the µC and the  
front end of the sensor spend most of the time in the idle state, waiting for the next logging interval, usually a few  
hundred of milliseconds. Figure 13 shows a data logging application based on a µC and a front end for a gas  
sensor based on the LMP91000.  
VOLTAGE  
REFERENCE  
VIN  
VOUT  
GND  
µC  
LMP91000  
Rp  
100k  
VOUT  
VIN  
Rp  
100k  
Rp  
100k  
VDD  
SDA  
VDD  
SCL  
SDA  
VREF  
CE  
TPL5010  
RSTn  
+
VDD  
GND  
RST  
Lithium  
ion battery  
CE  
POWER MANAGEMENT  
GND  
WAKE  
DONE  
GPIO  
GPIO  
SCL  
RE  
RE  
WE  
-
DELAY/  
M_RST  
ADC  
GND  
GPIO  
GPIO  
VOUT  
GND  
WE  
GAS  
SENSOR  
MENB  
GPIO  
GPIO  
Button  
Temp 29°C  
CO 0PPM  
Button  
Button  
TIME xx:xx  
Date xx/xx/xxxx  
DISPLAY  
KEYBOARD  
Figure 13. Data-Logger  
9.2.1 Design Requirements  
The design is driven by the low-current consumption constraint. The data are usually acquired on a rate that  
ranges between 1 s and 10 s. The highest necessity is the maximization of the battery life. The TPL5010 helps  
achieve that goal because it allows putting the µC in its lowest power mode. The TPL5010 will take care of the  
watchdog and the timing.  
16  
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TPL5010  
www.ti.com.cn  
ZHCSEK6A JANUARY 2015REVISED SEPTEMBER 2018  
Typical Application (continued)  
9.2.2 Detailed Design Procedure  
When the main constraint is the battery life, the selection of a low power voltage reference, the µC, and the  
display is mandatory. The first step in the design is the calculation of the power consumption of the devices in  
their different mode of operations. For instance, the LMP91000 burns most of the power when in gas  
measurement mode, then, according to the connected gas sensor, it has two idle states (standby and deep  
sleep). The same is true for the µC, such as one of the MSP430 family, which can be placed in one of its lower  
power modes, such as LMP3.5 or LMP4.5. In this case, the TPL5010 can be used to implement the watchdog  
and wake-up timing functions.  
After the power budget calculation, it is possible to select the appropriate time interval which satisfies the  
application constraints and maximize the life of the battery.  
9.2.3 Application Curve  
Without TPL5010  
With TPL5010  
Time  
Figure 14. Effect of TPL5010 on Current Consumption  
Copyright © 2015–2018, Texas Instruments Incorporated  
17  
TPL5010  
ZHCSEK6A JANUARY 2015REVISED SEPTEMBER 2018  
www.ti.com.cn  
10 Power Supply Recommendations  
The TPL5010 requires a voltage supply within 1.8 V and 5.5 V. A multilayer ceramic bypass X7R capacitor of 0.1  
μF between VDD and GND pin is recommended.  
11 Layout  
11.1 Layout Guidelines  
The DELAY/M_RST pin is sensitive to parasitic capacitance. TI suggests that the traces connecting the  
resistance on this pin to GROUND be kept as short as possible to minimize parasitic capacitance. This  
capacitance can affect the initial set up of the time interval. Signal integrity on the WAKE and RSTn pins is also  
improved by keeping the trace length between the TPL5010 and the µC short to reduce the parasitic  
capacitance.  
11.2 Layout Example  
Figure 15. Layout  
18  
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TPL5010  
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ZHCSEK6A JANUARY 2015REVISED SEPTEMBER 2018  
12 器件和文档支持  
12.1 接收文档更新通知  
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周接收产  
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。  
12.2 社区资源  
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商按照原样提供。这些内容并不构成 TI 技术规范,  
并且不一定反映 TI 的观点;请参阅 TI 《使用条款》。  
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在  
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。  
设计支持  
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。  
12.3 商标  
E2E is a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
12.4 静电放电警告  
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可  
能会损坏集成电路。  
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可  
能会导致器件与其发布的规格不相符。  
12.5 术语表  
SLYZ022 TI 术语表。  
这份术语表列出并解释术语、缩写和定义。  
13 机械、封装和可订购信息  
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且  
不会对此文档进行修订。如需获取此产品说明书的浏览器版本,请查阅左侧的导航栏。  
版权 © 2015–2018, Texas Instruments Incorporated  
19  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TPL5010DDCR  
TPL5010DDCT  
ACTIVE SOT-23-THIN  
ACTIVE SOT-23-THIN  
DDC  
DDC  
6
6
3000 RoHS & Green  
250 RoHS & Green  
NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
-40 to 105  
-40 to 105  
ZAKX  
ZAKX  
NIPDAU  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
3-Jun-2022  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPL5010DDCR  
TPL5010DDCT  
TPL5010DDCT  
SOT-23-  
THIN  
DDC  
DDC  
DDC  
6
6
6
3000  
250  
178.0  
178.0  
180.0  
8.4  
8.4  
8.4  
3.2  
3.2  
3.1  
3.2  
1.4  
1.4  
1.1  
4.0  
4.0  
4.0  
8.0  
8.0  
8.0  
Q3  
Q3  
Q3  
SOT-23-  
THIN  
3.2  
SOT-23-  
THIN  
250  
3.05  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
3-Jun-2022  
TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPL5010DDCR  
TPL5010DDCT  
TPL5010DDCT  
SOT-23-THIN  
SOT-23-THIN  
SOT-23-THIN  
DDC  
DDC  
DDC  
6
6
6
3000  
250  
208.0  
208.0  
183.0  
191.0  
191.0  
183.0  
35.0  
35.0  
20.0  
250  
Pack Materials-Page 2  
PACKAGE OUTLINE  
DDC0006A  
SOT-23 - 1.1 max height  
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR  
3.05  
2.55  
1.1  
0.7  
1.75  
1.45  
0.1 C  
B
A
PIN 1  
INDEX AREA  
1
6
4X 0.95  
1.9  
3.05  
2.75  
4
3
0.5  
0.3  
0.1  
6X  
TYP  
0.0  
0.2  
C A B  
C
0 -8 TYP  
0.25  
GAGE PLANE  
SEATING PLANE  
0.20  
0.12  
TYP  
0.6  
0.3  
TYP  
4214841/C 04/2022  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. Reference JEDEC MO-193.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DDC0006A  
SOT-23 - 1.1 max height  
SMALL OUTLINE TRANSISTOR  
SYMM  
6X (1.1)  
1
6
6X (0.6)  
SYMM  
4X (0.95)  
4
3
(R0.05) TYP  
(2.7)  
LAND PATTERN EXAMPLE  
EXPLOSED METAL SHOWN  
SCALE:15X  
METAL UNDER  
SOLDER MASK  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL  
EXPOSED METAL  
EXPOSED METAL  
0.07 MIN  
ARROUND  
0.07 MAX  
ARROUND  
NON SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
SOLDERMASK DETAILS  
4214841/C 04/2022  
NOTES: (continued)  
4. Publication IPC-7351 may have alternate designs.  
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DDC0006A  
SOT-23 - 1.1 max height  
SMALL OUTLINE TRANSISTOR  
SYMM  
6X (1.1)  
1
6
6X (0.6)  
SYMM  
4X(0.95)  
4
3
(R0.05) TYP  
(2.7)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 THICK STENCIL  
SCALE:15X  
4214841/C 04/2022  
NOTES: (continued)  
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
7. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
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Copyright © 2022,德州仪器 (TI) 公司  
配单直通车
TPL5010DDCR产品参数
型号:TPL5010DDCR
Brand Name:Texas Instruments
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
包装说明:TSSOP,
Reach Compliance Code:compliant
ECCN代码:EAR99
Factory Lead Time:6 weeks
风险等级:1.64
可调阈值:YES
模拟集成电路 - 其他类型:POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码:R-PDSO-G6
JESD-609代码:e4
长度:2.9 mm
湿度敏感等级:1
信道数量:1
功能数量:1
端子数量:6
最高工作温度:105 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260
座面最大高度:1.1 mm
最大供电电流 (Isup):0.00005 mA
最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.8 V
标称供电电压 (Vsup):2.5 V
表面贴装:YES
温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING
端子节距:0.95 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:1.6 mm
Base Number Matches:1
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