TPS1663现货热卖使用介绍供应商报价哪里找芯片批发报价-中国IC网-芯三七

TPS1663

ZHCSIV1F –SEPTEMBER 2018 –REVISED FEBRUARY 2023

具有可调节输出功率限制功能的TPS1663x 60V、6A 电子保险丝

1 特性

3 说明

• 工作电压为4.5V 至60V，

TPS1663x 是一款易于使用的正极 60V、6A 电子保险

丝，具有一个 31mΩ 的集成式 FET。可提供对负载、

电源和电子保险丝本身的保护以及可调特性，例如精确

的过流保护、快速短路保护、输出压摆率控制、过压保

护和欠压锁定。TPS16332 器件集成了可调节输出功率

限制 (PLIM) 功能，可简化并实现对诸如 IEC61010-1

和 UL1310 等标准的遵从。该器件还具有可调节过流

保护功能。可以使用 PGOOD 来启用和禁用下游直流/

直流转换器控制。

绝对最大值为67V

• 集成式60V、31mΩR_ON热插拔FET

• 可调电流限制为0.6A 至6A (±7%)

• 低静态电流，关断时为21µA

• 可调节输出功率限制（仅限TPS16632）(±6%)

• 精度为±2% 的可调节UVLO 和OVP 切断

– 39V 固定最大过压钳位（仅限TPS16632）

• 可调节输出压摆率控制，用于实现浪涌电流限制

– 通过在器件加电期间进行热调节，为大型及未知

电容负载充电

• 电源正常输出(PGOOD)

• 可选过流故障响应选项（自动重试和闭锁模式）

• 模拟电流监控器(IMON) 输出(±6%)

• 通过UL 2367 认证

借助关断引脚，可以从外部控制内部 FET 的启用和禁

用以及将器件置于低电流关断模式。为实现系统状态监

视和下游负载控制，该器件提供了故障和精确的电流监

视器输出。MODE 引脚可用于在两种限流故障响应

（闭锁自动重试）之间灵活地对器件进行配置。

这些器件采用 4mm × 4mm 24 引脚 VQFN 封装，额定

温度范围为–40°C 至+125°C。

– 文件编号E169910

– RILIM ≥3kΩ

封装信息

• 通过IEC 62368-1 认证

• 提供功能安全

封装⁽¹⁾

VQFN (24)

HTSSOP (20)

封装尺寸（标称值）

4.00mm × 4.00mm

6.50mm x 4.40mm

器件型号

TPS16630

– 有助于进行功能安全系统设计的文档

• 采用易于使用的24 引脚VQFN 封装

TPS16632

TPS16630

2 应用

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 工厂自动化和控制–PLC、DCS、HMI、I/O 模

块、传感器集线器

• 电机驱动器–CNC、编码器电源

• 电子断路器

• 电信无线电

• 工业打印机

4.5 V - 60 V

OUT

IN

C_OUT

P_IN

31 mΩ

Protected supply

To Load

R₁

R₂

PGOOD

FLT

UVLO

TPS16632

ON/OFF Control

SHDN

PLIM

IMON

ILIM

Load Monitor

R_IMON

R_PLIM

GND

dVdT

MODE

R_ILIM

C_dVdT

TPS16632 的输出功率限制性能

简化原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSET9

TPS1663

www.ti.com.cn

ZHCSIV1F –SEPTEMBER 2018 –REVISED FEBRUARY 2023

Table of Contents

9.3 Feature Description...................................................15

9.4 Device Functional Modes..........................................23

10 Application and Implementation................................24

10.1 Application Information........................................... 24

10.2 Typical Application.................................................. 24

10.3 System Examples................................................... 27

10.4 Power Supply Recommendations...........................27

10.5 Layout..................................................................... 28

11 Device and Documentation Support..........................32

11.1 Documentation Support.......................................... 32

11.2 接收文档更新通知................................................... 32

11.3 支持资源..................................................................32

11.4 Trademarks............................................................. 32

11.5 静电放电警告...........................................................32

11.6 术语表..................................................................... 32

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings........................................ 5

7.2 ESD Ratings............................................................... 5

7.3 Recommended Operating Conditions.........................5

7.4 Thermal Information....................................................5

7.5 Electrical Characteristics.............................................6

7.6 Timing Requirements..................................................7

7.7 Typical Characteristics................................................9

8 Parameter Measurement Information..........................12

9 Detailed Description......................................................13

9.1 Overview...................................................................13

9.2 Functional Block Diagram.........................................14

Information.................................................................... 32

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision E (March 2020) to Revision F (February 2023)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 向特性部分添加了“提供功能安全型”要点......................................................................................................1

Changes from Revision D (August 2019) to Revision E (March 2020)

Page

• 已将待定的 UL 2367 和UL 60950 认证更改为通过 UL 2367 认证.....................................................................1

• 向特性部分添加了“通过IEC 62368-1 认证”...................................................................................................1

Changes from Revision C (March 2019) to Revision D (August 2019)

Page

• 更改了特性中的绝对最大电压............................................................................................................................1

• 更改了特性中的可调节输出功率限制功能..........................................................................................................1

• Changed the Absolute Maximum Ratings IN, P_IN, OUT, UVLO, FLT, PGOOD maximum input voltage......... 5

• Added T_A= 25℃to the Absolute Maximum Ratings IN, P_IN (10ms transient) input voltage...........................5

• Changed the V_(OVPF)maximum in Electrical Characteristics .............................................................................6

• Changed V_{(SEL_PLIM)}, I_(PLIM), and I_(dVdT)minimum and maximum.......................................................................6

• Changed the P_(PLIM)minimum, typical, and maximum....................................................................................... 6

Changes from Revision B (December 2018) to Revision C (March 2019)

Page

• 将“预告信息”更改为“量产数据”..................................................................................................................1

Changes from Revision A (October 2018) to Revision B (December 2018)

Page

• Updated the TPS16632 RGE Package VQFN................................................................................................... 3

• Updated Functional Block Diagram ................................................................................................................. 14

• Updated Layout Example ................................................................................................................................ 30

Changes from Revision * (September 2018) to Revision A (October 2018)

Page

• 更改了封装信息.................................................................................................................................................. 1

English Data Sheet: SLVSET9

2

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ZHCSIV1F –SEPTEMBER 2018 –REVISED FEBRUARY 2023

5 Device Comparison Table

PART NUMBER

TPS16630

OVERVOLTAGE PROTECTION

ADJUSTABLE OUTPUT POWER LIMITING

Overvoltage cutoff, adjustable

No

TPS16632

Overvoltage clamp, fixed (39-V maximum)

Yes

6 Pin Configuration and Functions

IN

1

2

3

4

OUT

20

OUT

19

18

17

IN

N.C

18

17

OUT

1

2

3

4

5

6

IN

N.C

PGOOD

5

6

16

15

14

PowerPAD™

FLT

N.C

P_IN

16

15

PGOOD

N.C

PowerPad^TM

UVLO

7

8

IMON

OVP

GND

SHDN

MODE

13

12

14

13

FLT

9

IMON

UVLO

10

11

dVdT

ILIM

图6-2. TPS16630 PWP Package, 20-Pin HTSSOP

(Top View)

图6-1. TPS16630 RGE Package, 24-Pin VQFN (Top

View)

18

17

OUT

1

2

3

4

5

6

IN

N.C

P_IN

16

15

PGOOD

N.C

PowerPad^TM

14

13

FLT

IMON

UVLO

图6-3. TPS16632 RGE Package, 24-Pin VQFN (Top View)

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English Data Sheet: SLVSET9

TPS1663

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ZHCSIV1F –SEPTEMBER 2018 –REVISED FEBRUARY 2023

表6-1. Pin Functions

TYPE#

none#

TPS16630

TPS16632

DESCRIPTION

NAME

VQFN

HTSSOP

VQFN

1

2

1

2

3

6

1

2

IN

P

Power input. Connects to the DRAIN of the internal FET.

—

P_IN

5

P

I

Supply voltage of the device. Always connect P_IN to IN directly.

Input for setting the programmable undervoltage lockout threshold.

An undervoltage event turns off the internal FET and asserts FLT to

indicate the power-failure.

UVLO

6

7

8

6

Input for setting the adjustable overvoltage protection threshold (for

TPS16630 only). An overvoltage event turns off the internal FET and

asserts FLT to indicate the overvoltage fault.

OVP

I

—

Input for setting the adjustable output power limiting threshold

(TPS16632 Only). Connect a resistor across PLIM to GND to set the

output power limit. Connect PLIM to GND if PLIM feature is not used.

See Output Power Limiting, PLIM (TPS16632 Only) section.

PLIM

GND

dVdT

7

8

9

—

8

—

9

Connect GND to system ground.

—

A capacitor from this pin to GND sets output voltage slew rate.

Leaving this pin floating enables device power up in thermal

regulation resulting in fast output charge. See the Hot Pug-In and In-

Rush Current Control section.

9

10

I/O

A resistor from this pin to GND sets the overload limit. See Overload

and Short Circuit Protection section.

ILIM

10

11

12

10

11

I/O

I

Mode selection pin for Overload fault response. See the Device

Functional Modes section.

MODE

Shutdown pin. Pulling SHDN low makes the device to enter into low

power shutdown mode. Cycling SHDN pin voltage resets the device

that has latched off due to a fault condition.

SHDN

12

13

12

I

Analog current monitor output. This pin sources a scaled down ratio

of current through the internal FET. A resistor from this pin to GND

converts current to proportional voltage. If unused, leave it floating.

IMON

FLT

13

14

15

13

14

O

Fault event indicator. This pin is an open drain output. If unused,

leave floating or connect to GND.

Active High. A high indicates that the internal FET is enhanced.

PGOOD goes low when the internal FET is turned OFF during a fault

or when SHDN is pulled low. If PGOOD is unused, then connect to

GND or leave it floating.

PGOOD

OUT

16

O

P

17

18

19

20

4

17

18

Power output of the device.

—

3

—

3

4

5

4

15

19

20

21

22

23

24

17

—

15

19

20

21

22

23

24

N.C

No connect.

—

Connect PowerPAD to GND plane for heat sinking. Do not use

PowerPAD as the only electrical connection to GND.

PowerPAD^™

—

4

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English Data Sheet: SLVSET9

TPS1663

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ZHCSIV1F –SEPTEMBER 2018 –REVISED FEBRUARY 2023

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

67

UNIT

V

IN, P_IN, OUT, UVLO, FLT, PGOOD

75

IN, P_IN (10-ms transient), T_A= 25℃

Input Voltage

OVP, dVdT, IMON, MODE, SHDN,

ILIM

5.5

10

–0.3

I_FLT, I_dVdT, I_PGOOD

Sink current

mA

I_dVdT, I_ILIM, I_PLIM,I_MODE,I_SHDN

Source current

Internally limited

Operating Junction temperature

Transient junction temperature

Storage temperature

150

T_(TSD)

150

–40

–65

T_J

°C

T_stg

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

0

NOM

MAX

60

4

UNIT

IN, P_IN

OUT, UVLO, PGOOD, FLT

Input voltage

Resistance

V

OVP, dVdT, IMON, MODE

0

SHDN

ILIM

0

5

3

30

150

PLIM

60.4

1

kΩ

IMON

IN, P_IN, OUT

dVdT

0.1

10

–40

µF

nF

°C

External capacitance

T_J

Operating junction temperature

25

125

7.4 Thermal Information

TPS1663

THERMAL METRIC⁽¹⁾

RGE (VSON)

24 PINS

31.4

PWP (HTSSOP)

UNIT

20 PINS

32.2

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

23.2

23.4

10.2

10

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UNIT

ZHCSIV1F –SEPTEMBER 2018 –REVISED FEBRUARY 2023

7.4 Thermal Information (continued)

TPS1663

THERMAL METRIC⁽¹⁾

RGE (VSON)

24 PINS

0.3

PWP (HTSSOP)

20 PINS

0.3

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

°C/W

Ψ_JT

10.2

9.9

Ψ_JB

R_θJC(bot)

2.8

3.6

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

–40°C ≤T_A= T_J≤+125°C, 4.5 V < V_(IN)= V_{(P_IN)}< 60 V, V_{( SHDN)}= 2 V, R_(ILIM)= 30 kΩ, IMON = PGOOD = FLT = OPEN,

C_(OUT)= 1 μF, C_(dVdT)= OPEN. (All voltages referenced to GND, (unless otherwise noted))

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SUPPLY VOLTAGE

V_(IN),V_{(P_IN)}

IQ_(ON)

Operating input voltage

Supply current

4.5

60

1.7

60

V

Enabled: V_{( SHDN)}= 2 V

1.38

21

mA

µA

IQ_(OFF)

V_{( SHDN)}= 0 V

TPS16632 only, V_(IN)> 40 V, I_(OUT)= 1

mA

V_(OVC)

Over voltage clamp

35.7

36.6

39

V

UNDERVOLTAGE LOCKOUT (UVLO) INPUT

V_(UVLOR)

V_(UVLOF)

I_(UVLO)

UVLO threshold voltage, rising

UVLO threshold voltage, falling

UVLO Input leakage current

1.176

1.09

1.2

1.122

8

1.224

1.15

150

V

nA

0 V ≤V_(UVLO)≤60 V

–150

OVERVOLTAGE PROTECTION (OVP) INPUT

V_(OVPR)

V_(OVPF)

I_(OVP)

over-voltage threshold voltage, rising

1.176

1.09

1.2

1.122

0

1.224

1.15

150

V

over-voltage threshold voltage, falling

OVP Input leakage current

nA

0 V ≤V_(OVP)≤4 V

–150

CURRENT LIMIT PROGRAMMING (ILIM)

0.54

1.84

0.6

2

0.66

2.16

A

R_(ILIM)= 30 kΩ, V_(IN)–V_(OUT)= 1 V

R_(ILIM)= 9 kΩ, V_(IN)–V_(OUT)= 1 V

R_(ILIM)= 4.02 kΩ, V_(IN)–V_(OUT)= 1 V

R_(ILIM)= 3 kΩ, V_(IN)–V_(OUT)= 1 V

I_(OL)

Over Load current limit

4.185

5.58

4.5

4.815

6.42

6

I_(FASTRIP)

I_(SCP)

Fast-trip comparator threshold

Short Circuit Protect current

2xI_(OL)

45

OUTPUT POWER LIMITING CONTROL (PLIM) INPUT –TPS16632 ONLY

V_{(SEL_PLIM)}

I_(PLIM)

Power Limit Feature select threshold

PLIM sourcing current

180

4.4

210

5.02

100

151

240

5.6

mV

µA

W

V_(PLIM)= 0 V

94

106

R_(PLIM)= 100 kΩ

R_(PLIM)= 150 kΩ

P_(PLIM)

Max Output power

(1)

141.9

160.1

W

PASS FET OUTPUT (OUT)

R_ON

IN to OUT total ON resistance

26

33

30.44

34.5

45

0.6 A ≤I_(OUT)≤6 A,T_J= 25°C

0.6 A ≤I_(OUT)≤6 A,T_J= 85°C

mΩ

IN to OUT total ON resistance

0.6 A ≤I_(OUT)≤6 A, –40°C ≤T_J≤

+125°C

R_ON

19

30.44

2

53

mΩ

OUTPUT RAMP CONTROL (dVdT)

I_(dVdT)dVdT charging current

V_(dVdT)= 0 V

1.775

2.225

µA

English Data Sheet: SLVSET9

6

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7.5 Electrical Characteristics (continued)

–40°C ≤T_A= T_J≤+125°C, 4.5 V < V_(IN)= V_{(P_IN)}< 60 V, V_{( SHDN)}= 2 V, R_(ILIM)= 30 kΩ, IMON = PGOOD = FLT = OPEN,

C_(OUT)= 1 μF, C_(dVdT)= OPEN. (All voltages referenced to GND, (unless otherwise noted))

PARAMETER

TEST CONDITIONS

MIN

23.5

3.8

TYP

MAX UNIT

GAIN_(dVdT)

V_(dVdTmax)

R_(dVdT)

dVdT to OUT gain

V_(OUT)/V_(dVdT)

25

26

4.75

26.6

V/V

V

dVdT maximum capacitor voltage

dVdT discharging resistance

4.17

16.6

10

Ω

CURRENT MONITOR OUTPUT (IMON)

GAIN_(IMON)Gain factor I_(IMON):I_(OUT)

LOW IQ SHUTDOWN ( SHDN) INPUT

25.66

26.22

27.9

30.14 µA/A

29.58 µA/A

0.6 A ≤I_(OUT)< 2 A

2 A ≤I_(OUT)≤6 A

V_{( SHDN)}

V_(SHUTF)

Open circuit voltage

I_{( SHDN)}= 0.1 µA

2.48

0.8

2.7

3.3

2

V

SHDN threshold voltage for low IQ

shutdown, falling

V_(SHUTR)

I_{( SHDN)}

SHDN threshold rising

Leakage current

V

V_{( SHDN)}= 0 V

µA

–10

FAULT FLAG ( FLT): ACTIVE LOW

R_{( FLT)}FLT Pull-down resistance

I_{( FLT)}FLT Input leakage current

POWER GOOD (PGOOD)

R_(PGOOD)PGOOD Pull-down resistance

I_(PGOOD)PGOOD Input leakage current

THERMAL PROTECTION

T_{(J_REG)}Thermal regulation set point

36

70

6

130

150

Ω

nA

0 V ≤V_{( FLT)}≤60 V

–150

36

70

6

130

150

Ω

nA

0 V ≤V_(PGOOD)≤60 V

–150

136

145

165

11

154

°C

Thermal shutdown (TSD) threshold,

rising

T_(TSD)

T_(TSDhyst)

TSD hysteresis

Mode selection

MODE

MODE = Open

Latch

MODE_SEL

Auto –

Retry

MODE = Short to GND

(1) Parameter specified by design and characterization, not tested in production

7.6 Timing Requirements

–40°C ≤T_A= T_J≤+125°C, 4.5 V < V_(IN)= V_{(P_IN)}< 60 V, V_{( SHDN)}= 2 V, R_(ILIM)= 30 kΩ, IMON = PGOOD = FLT = OPEN,

C_(OUT)= 1 μF, C_(dVdT)= OPEN. (All voltages referenced to GND, (unless otherwise noted))

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX UNIT

UVLO INPUT (UVLO)

UVLO↑(100 mV above V_(UVLOR)) to

V_(OUT)= 100 mV, C_(dVdT)≥10 nF,

[C_(dVdT)in nF]

742 +

49.5 x

C_(dVdT)

UVLO_t_on(dly)

UVLO switch turnon delay

µs

UVLO↓(20 mV below V_(UVLOF)) to FLT

↓

UVLO_t_off(dly)

t_{UVLO_FLT(dly)}

UVLO switch turnoff delay

9

11

16

µs

UVLO to Fault de-assertion delay

500

617

700

UVLO↑ to FLT ↑delay

OVER VOLTAGE PROTECTION INPUT (OVP)

OVP_t_off(dly)OVP switch turnOFF delay

OVP↑(20 mV above V_(OVPR)) to FLT

↓

8.5

11

14

µs

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ZHCSIV1F –SEPTEMBER 2018 –REVISED FEBRUARY 2023

7.6 Timing Requirements (continued)

–40°C ≤T_A= T_J≤+125°C, 4.5 V < V_(IN)= V_{(P_IN)}< 60 V, V_{( SHDN)}= 2 V, R_(ILIM)= 30 kΩ, IMON = PGOOD = FLT = OPEN,

C_(OUT)= 1 μF, C_(dVdT)= OPEN. (All voltages referenced to GND, (unless otherwise noted))

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX UNIT

150 +

49.5 x

C_(dVdT)

OVP↓(100 mV below V_(OVPF)) to FET

ON , C_(dVdT)≥10 nF, [C_(dVdT)in nF]

OVP_t_on(dly)

OVP switch disable delay

µs

Maximum duration in over voltage

clamp operation

t_OVC(dly)

TPS16632 only

162

617

ms

µs

FLT assertion delay in over voltage

clamp operation

OVC_t_FLT(dly)

SHUTDOWN CONTROL INPUT ( SHDN)

t_SD(dly)

SHUTDOWN entry delay

0.8

1

1.5

µs

SHDN↓(below V_(SHUTF)) to FET OFF

CURRENT LIMIT

Hot-short response time

Soft short response

I_(OUT)> I_(SCP)

1

µs

t_{FASTTRIP(dly)}

I_(FASTTRIP)< I_(OUT)< I_(SCP)

2.2

3.2

4.5

Maximum duration in current & (power

limiting: TPS16632 Only)

t_{CL_PLIM(dly)}

129

162

1.3

202

ms

FLT delay in current & (power limiting:

TPS16632 Only)

t_{CL_PLIM_FLT(dly)}

1.09

350

1.6

OUTPUT RAMP CONTROL (dVdT)

t_(FASTCHARGE)Output ramp time in fast charging

t_(dVdT)Output ramp time

C_(dVdT)= Open, 10% to 90%

V_(OUT), C_(OUT)= 1 µF; V_(IN)= 24V

495

700

µs

C_(dVdT)= 22 nF, 10% to 90%

V_(OUT),V_(IN)= 24 V

8.35

ms

POWER GOOD (PGOOD)

t_PGOODRPGOOD delay (deglitch) time

t_PGOODFPGOOD delay (deglitch) time

THERMAL PROTECTION

Rising edge

Falling edge

8

11.5

10

13

ms

t_{(TSD_retry)}

Retry delay in TSD

Thermal Regulation Timeout

MODE = GND

500

1.1

648

800

1.5

ms

s

t_{(Treg_timeout)}

1.25

English Data Sheet: SLVSET9

8

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7.7 Typical Characteristics

–40°C ≤T_A= T_J≤+125°C, V_(IN)= V_{(P_IN)}= 24 V, V_{( SHDN)}= 2 V, R_(ILIM)= 30 kΩ, IMON = PGOOD = FLT = OPEN, C_(OUT)

= 1 μF, C_(dVdT)= OPEN (unless stated otherwise)

75

60

45

30

15

0

40

38

36

34

32

30

I_LOAD= 0.6 A

I_LOAD= 6 A

-60

-30

0

30

60

90

120

150

-50

0

50

Temperature (èC)

100

150

Temperature (èC)

D002

D006

图7-1. On-Resistance vs Temperature Across Load Current

TPS16632

图7-2. Overvoltage Clamp Threshold vs Temperature

48

1600

T_A= 125èC

T_A= 85èC

T_A= 25èC

T_A= -40èC

45

42

39

36

33

30

27

24

21

18

15

12

9

1400

1200

1000

800

600

T_A= -40 èC

T_A= 25 èC

T_A= 85 èC

T_A= 125 èC

400

200

0

6

0

5

10 15 20 25 30 35 40 45 50 55 60

Supply Voltage (V)

0

5

10 15 20 25 30 35 40 45 50 55 60 65

Supply Voltage (V)

D023

D026

图7-3. Input Supply Current vs Supply Voltage in Shutdown

图7-4. Input Supply Current vs Supply Voltage During Normal

Operation

10

1.25

R_(ILIM)= 9 kW

R_(ILIM)= 4.02 kW

R_(ILIM)= 3 kW

R_(ILIM)= 30 kW

R_(ILIM)= 18 kW

7.5

5

1

0.75

0.5

2.5

0

-50

0

50

Temperature (èC)

100

150

-50

0

50

Temperature (èC)

100

150

D020

D025

图7-5. Overload Current Limit vs Temperature

图7-6. Overload Current Limit vs Temperature

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7.7 Typical Characteristics (continued)

–40°C ≤T_A= T_J≤+125°C, V_(IN)= V_{(P_IN)}= 24 V, V_{( SHDN)}= 2 V, R_(ILIM)= 30 kΩ, IMON = PGOOD = FLT = OPEN, C_(OUT)

= 1 μF, C_(dVdT)= OPEN (unless stated otherwise)

7

6

5

4

3

2

1

150

125

100

75

8

7

6

5

CURRENT LIMIT

POWER LIMIT

50

25

0

60

0

10

20

30

Supply Voltage (V)

40

50

60

80

100

120

140

160

D052

PLIM (W)

D042

TPS16632

R_(PLIM)= 100 kΩ

R_(ILIM)= 3 kΩ

图7-7. Output Power Limiting Accuracy vs PLIM

图7-8. Power Limit, Current Limit vs Supply Voltage

160

140

120

100

80

T_A= 125èC

T_A= 85èC

T_A= 25èC

T_A= -40èC

140

120

100

80

60

40

20

0

0.6 1.2 1.8 2.4

3

Output Current (A)

3.6 4.2 4.8 5.4

6

6.6

0

0.1

0.2

0.3

Output Current (A)

0.4

0.5

0.6

D021

D033

图7-9. Current Monitor Output vs Output Current

190

图7-10. IMON Gain Accuracy at Low Output Current Levels

13

t_PGOODR

t_PGOODF

180

170

160

150

140

12

11

10

9

-50

0

50

Temperature (èC)

100

150

-50

0

50

Temperature (èC)

100

150

D029

D031

图7-11. Maximum Duration in Current and Power Limiting vs

图7-12. PGOOD Rising and Falling Delay vs Temperature

Temperature

10

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7.7 Typical Characteristics (continued)

–40°C ≤T_A= T_J≤+125°C, V_(IN)= V_{(P_IN)}= 24 V, V_{( SHDN)}= 2 V, R_(ILIM)= 30 kΩ, IMON = PGOOD = FLT = OPEN, C_(OUT)

= 1 μF, C_(dVdT)= OPEN (unless stated otherwise)

3000

2000

T_A= -40èC

1000

T_A= 0èC

500

T_A= 25èC

T_A= 85èC

200

T_A= 125èC

100

50

20

10

5

2

1

0.5

0.2

0.1

3

4

5 6 7 8 10

20 30 4050 70 100

Power Dissipation (W)

200 300400

D040

Taken on VQFN device on EVM Board

图7-13. Thermal Shutdown Time vs Power Dissipation

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8 Parameter Measurement Information

V_(OUT)

V_UVLO

V_(UVLOF)-0.02 V

0.1 V

V_UVLO

FLT

V_(UVLOR)+0.1V

10%

time

0

time

0

UVLO_t_ON(dly)

UVLO_t_off(dly)

V_(OVPR)+0.02V

V_(OVP)

V_(OUT)

0.1 V

FLT

V_OVP

V_(OVPF)-0.02 V

10%

0

time

OVP_t_OFF(dly)

OVP_t_ON(dly)

P_(PLIM)

P_(OUT)

I_(FASTRIP)

V_(OUT)

I_(OL)

I_(OUT)

0

t_{CL_PLIM(dly)}

time

t_{CL_PLIM(dly)}

0

time

t_FASTRIP(dly)

图8-1. Timing Waveforms

English Data Sheet: SLVSET9

12

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9 Detailed Description

9.1 Overview

The TPS1663x is a family of 60-V industrial eFuses. The device provides robust protection for all systems and

applications powered from 4.5 V to 60 V. For hot-pluggable boards, the device provides hot-swap power

management with in-rush current control and programmable output voltage slew rate features using the dVdT

pin. Load, source, and device protections are provided with many programmable features including overcurrent,

overvoltage and undervoltage. The 60-V maximum DC operating and 62-V absolute maximum voltage rating

enables system protection from 60-V DC input supply faults from industrial SELV power supplies. The precision

overcurrent limit (±7% at 6 A) helps to minimize over design of the input power supply, while the fast response

short circuit protection 1 µs (typical) immediately isolates the faulty load from the input supply when a short

circuit is detected.

The TPS16632 device integrate adjustable output power limiting (PLIM) functionality that simplifies the system

design requiring compliance in accordance to standards like IEC61010-1 and UL1310.

The device provides precise monitoring of voltage bus for brown-out and overvoltage conditions and asserts fault

signal for the downstream system. The device's overall threshold accuracy of 2% ensures tight supervision of

bus, eliminating the need for a separate supply voltage supervisor chip.

Additional features of the TPS1663x include:

• ±6% current monitor output (IMON) for health monitoring of the system

• A choice of latch off or automatic restart mode response during current limit, power limit, and thermal fault

using MODE pin

• PGOOD indicator output

• Overtemperature protection to safely shutdown in the event of an overcurrent event

• De-glitched fault reporting for supply brown-out and overvoltage faults

• Enable and Disable control from an MCU using SHDN pin

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9.2 Functional Block Diagram

OUT

IN

P_IN

31 mΩ

Charge

Pump

Current

Sense

P_IN

+

PORb

X27.9 µ

4.3 V

4.2 V

IMON

CP

UVLO

5 V

Gate Control Logic

UVLOb

1.2 V

Current Limit Amp

1.12 V

SWEN

I_(OUT)= I_(OL)

Fast-Trip Comp

(Threshold= 45A)

162 msec

timer

Timeout

ILIM

TSD

Thermal

Shutdown

OLR

Open/ Short

detect

OVP

+

OVP

SHDNb

1.2V

1.12V

4.17V

Ramp Control

2µA

SWEN

FLT

25x

* Only for Latch Mode

dVdT

70 Ω

SET

UVLOb

PORb

S

Q

16Ω

TSD

CLR

R

Q

SHDNb

GND

PORb

Fault Latch

Gate Enhanced

(HS_FET)

PGOOD

11.5 ms

10 ms

1.2 Meg ꢀ

SET

S

R

Q

MODE

3V

2.7V

Overload fault response

(Auto-Retry/Latch-off)

select detection

65 Ω

OLR

10 µsec

0.8V

CLR

UVLOb

SHDNb

+

SHDNb

TPS16630

SHDN

English Data Sheet: SLVSET9

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9.3 Feature Description

9.3.1 Hot Plug-In and In-Rush Current Control

The devices are designed to control the in-rush current upon insertion of a card into a live backplane or other hot

power source. This design limits the voltage sag on the backplane’s supply voltage and prevents unintended

resets of the system power. The controlled start-up also helps to eliminate conductive and radiative

interferences. An external capacitor connected from the dVdT pin to GND defines the slew rate of the output

voltage at power-on. The fastest output slew rate of 24 V/500 µs can be achieved by leaving dVdT pin floating.

The inrush current can be calculated using 方程式1.

dV

dT

V(IN)

tdVdT

I = Cì

where

í I(INRUSH) = C(OUT) ì

(1)

(2)

t_dVdT= 20.8 × 10³× V_(IN)× C_(dVdT)

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图9-1 illustrates in-rush current control performance of the device during Hot Plug-In.

VIN

VOUT

PGOOD

IIN

C_dVdT= 100 nF

C_OUT= 1000 µF

R_ILIM= 4.02 kΩ

图9-1. Hot Plug In and In-Rush Current Control at 24-V Input

9.3.1.1 Thermal Regulation Loop

The average power dissipation within the eFuse during power up with a capacitive load can be calculated using

方程式3.

PD(INRUSH) = 0.5ì V(IN) ìI(INRUSH)

(3)

System designs requiring to charge large output capacitors rapidly can result in an operating point that exceeds

the power dissipation versus time boundary limits of the device defined by 图 7-13 characteristic curve. This

event can result in increase in junction temperature beyond the device's maximum allowed junction temperature.

To keep the junction temperature within the operating range, the thermal regulation control loop regulates the

junction temperature at T_{(J_REG)}, 145°C (typical) by controlling the inrush current profile and thereby limiting the

power dissipation within the device automatically. An internal 1.25 sec (typical), t_{(Treg_timeout)}timer starts from the

instance the thermal regulation operation kicks in. If the output does not power up within this time then the

internal FET is turned OFF. Subsequent operation of the device depends on the MODE configuration (auto-retry

or latch OFF) setting as per the 表 9-1. The maximum time-out of 1.25 sec (typical) in thermal regulation loop

operation ensures that the device and the system board does not heat up during steady fault conditions such as

wake up with output short-circuit. This scheme ensures reliable power-up operation.

Thermal regulation control loop is internally enabled during power up by V_(IN), UVLO cycling and turn ON using

SHDN control. 图 9-2 illustrates performance of the device operating in thermal regulation loop during power up

by V_(IN)with a large output capacitor. The thermal regulation loop gets disabled internally after the power up

sequence when the internal FET's gate gets fully enhanced or when the t_{(Treg_timeout)}of 1.25 sec (typical) time is

elapsed.

English Data Sheet: SLVSET9

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VIN

VOUT

PGOOD

IIN

C_dVdT= Open

C_OUT= 15 mF

R_ILIM= 4.02 kΩ

图9-2. Thermal Regulation Loop Response During Power Up With Large Capacitive Load

9.3.2 Undervoltage Lockout (UVLO)

The TPS1663x devices feature an accurate ± 2% adjustable undervoltage lockout functionality. When the

voltage at UVLO pin falls below V_(UVLOF)during input undervoltage fault, the internal FET quickly turns off and

FLT is asserted. The UVLO comparator has a hysteresis of 78 mV (typical). To set the input UVLO threshold,

connect a resistor divider network from IN supply to UVLO terminal to GND as shown in 图 9-3. If the

Undervoltage Lockout function is not needed, the UVLO terminal must be connected to the IN terminal. UVLO

terminal must not be left floating.

V_(IN)

IN

P_IN

R₁

UVLO

+

UVLOb

1.2 V

R₂

1.12 V

OVP

+

OVP

1.2 V

1.12 V

R₃

GND

图9-3. UVLO and OVP Thresholds Set by R₁, R₂and R₃

9.3.3 Overvoltage Protection (OVP)

The TPS1663x incorporate circuitry to protect the system during overvoltage conditions. The TPS16630 features

an accurate ± 2% adjustable overvoltage cut off functionality. A voltage more than V_(OVPR)on OVP pin turns off

the internal FET and protects the downstream load. To program the OVP threshold externally, connect a resistor

divider from IN supply to OVP terminal to GND as shown in 图 9-3. The TPS16632 features an internally fixed

39-V maximum overvoltage clamp V_(OVC)functionality. The TPS16632 clamps the output voltage to V_(OVC), when

the input voltage exceeds 40 V. During the output voltage clamp operation, the power dissipation in the internal

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MOSFET is PD = (V_(IN) – V_(OVC)) × I_(OUT). Excess power dissipation for a prolonged period can increase the

device temperature. To avoid this, the internal FET is operated in overvoltage clamp for a maximum duration of

t_OVC(dly), 162 msec (typical). After this duration, the internal FET is turned OFF and the subsequent operation of

the device depends on the MODE configuration (auto-retry or latch off) setting as per the 表9-1.

图 9-4 illustrates the overvoltage cut-off functionality and 图 9-5 illustrates the overvoltage clamp functionality.

FLT is asserted after a delay of 617 µs (typical) after entering in overvoltage clamp mode and remains asserted

until the overvoltage fault is removed.

VIN

VOUT

FLTb

IIN

TPS16630

OVP Setting at 33 V

TPS16632

C_OUT= 10 µF, FLT

connected to V_OUT

R_LOAD= 30 Ω

图9-4. Overvoltage Cut-Off Response at 33-V Level

图9-5. Overvoltage Clamp Response

9.3.4 Overload and Short Circuit Protection

The device monitors the load current by sensing the voltage across the internal sense resistor. The FET current

is monitored during start-up and normal operation.

9.3.4.1 Overload Protection

The TPS1663x devices feature accurate overload current limiting and fast short circuit protection feature. If the

load current exceeds the programmed current limit I_OL, the device regulates the current through it at I_OL

eventually reducing the output voltage. The power dissipation across the device during this operation is (V_IN–

V_OUT) × I_OLand this can heat up the device and eventually enter into thermal shutdown. The maximum duration

for the overcurrent through the FET is t_{CL_PLIM(dly)}, 162 msec (typical). If the thermal shutdown occurs before this

time the internal FET turns OFF and the device operates either in auto-retry or latch off mode based on MODE

pin configuration in 表9-1. Set the current limit using 方程式4.

18

I_OL

=

R₍_ILIM

)

(4)

where

• I_(OL)is the overload current limit in Ampere

• R_(ILIM)is the current limit resistor in kΩ

During the overload current limiting if the overload condition exists for more than t_{CL_PLIM_FLT(dly)}, 1.3 msec

(typical), the FLT asserts to warn of impending turnoff of the internal FETs due to the subsequent thermal

shutdown event or due to t_{CL_PLIM(dly)}timer expiry. The FLT signal remains asserted until the fault condition is

removed and the device resumes normal operation. 图 9-6 and 图 9-7 illustrate overload current limiting

performance.

English Data Sheet: SLVSET9

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VOUT

IIN

IMON

FLTb

IMON

FLTb

V_IN= 50 V

MODE = GND

V_IN= 50 V

MODE = GND

R_ILIM= 18 kΩ

图9-6. Overload Performance During Load Step

from 140 Ωto 40 Ω

图9-7. Coming Out of Overload With Load Step

from 40 Ωto 140 Ω

The TPS1663x devices features ILIM pin short and open fault detection and protection. The internal FET is

turned OFF when ILIM pin is detected short or open to GND and it remains OFF till the ILIM pin fault is removed.

9.3.4.2 Short Circuit Protection

During a transient output short circuit event, the current through the device increases rapidly. As the current-limit

amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip

comparator. The fast-trip comparator architecture is designed for fast turn OFF t_{FASTTRIP(dly)}= 1 µs (typical) with

I_(SCP)= 45 A of the internal FET during an output short circuit event. The fast-trip threshold is internally set to

I_(FASTTRIP). The fast-trip circuit holds the internal FET off for only a few microseconds, after which the device

turns back on slowly, allowing the current-limit loop to regulate the output current to I_(OL). Then the device

functions similar to the overload condition. 图9-8 illustrates output hot-short performance of the device.

VOUT

IIN

IMON

FLTb

V_IN= 50 V

R_ILIM= 18 kΩ

图9-8. Output Hot-Short Response

The fast-trip comparator architecture has a supply line noise immunity resulting in a robust performance in noisy

environments. This supply line noise immunity is achieved by controlling the turn OFF time of the internal FET

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based on the overcurrent level, I_(FASTTRIP), through the device. The higher the overcurrent, the faster the turn

OFF time, t_{FASTTRIP(dly)}. At Overload current level in the range of I_FASTTRIP< I_OUT< I_SCP, the fast-trip comparator

response is 3.2 µs (typical).

9.3.4.2.1 Start-Up With Short-Circuit On Output

When the device is started with short-circuit on the output, the current begins to limit at I_(OL). Due to high power

dissipation of VIN x I_(OL)within the device the junction temperature increases. Subsequently, the thermal

regulation control loop limits the load current to regulate the junction temperature at T_{(J_REG)}, 145°C (typical) for

a duration of t_{(Treg_timeout)}, 1.25 sec (typical). Subsequent operation of the device depends on the MODE

configuration (auto-retry or latch off) setting as per the 表 9-1. FLT gets asserted after t_{(Treg_timeout)}and remains

asserted till the output short-circuit is removed. 图9-9 illustrates the behavior of the device in this condition.

VIN

FLTb

IIN

V_IN= 24 V

R_ILIM= 3 kΩ

图9-9. Start-Up With Short on Output

9.3.5 Output Power Limiting, PLIM (TPS16632 Only)

In TPS16630, with a fixed overcurrent limit threshold the maximum output power limit increases linearly with

supply input. Electrical Industrial process control equipment such as PLC CPU must comply with standards like

IEC61010-1 and UL1310 for fire safety which require limited energy and power circuits. Limiting the output

power becomes a challenge in such high power applications where the operating supply voltage range is wide.

The TPS16632 integrate adjustable output power limiting functionality that simplifies the system design requiring

compliance in accordance to this standard.

Connect a resistor from PLIM to GND as shown in 图 9-10 to set the output power limiting value. If output power

limiting is not required, then connect PLIM to GND directly. This connection disables the PLIM functionality.

During an over-power load event, the TPS16632 limits the output power at the programmed value set by PLIM

resistor. This limit indirectly results in the device operation in current limiting mode with steady state output

voltage and current set by the load characteristics and P_LIM= V_OUT× I_OUT. 图 7-8 shows the output power limit

and current limit characteristics of TPS16632 with 100-W power limit setting. The maximum duration for the

device in power limiting mode is 162 msec (typical), t_{CL_PLIM(dly)}. After this time, the device operates either in

auto-retry or latch off mode based on MODE pin configuration in 表9-1.

P_(PLIM)= 1 × R_(PLIM)

(5)

Here, P_(PLIM)is output power limit in watts, and R_(PLIM)is the power limit setting resistor in kΩ.

English Data Sheet: SLVSET9

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During the output power limiting operation, FLT asserts after a delay of t_{CL_PLIM_FLT(dly)}. The FLT signal remains

asserted until the over power load condition is removed and the device resumes normal operation.

图 9-11 illustrates output power limiting performance of TPS16632 with 100-W setting for class-2 power supply

designs .

4.5 V - 60 V

OUT

IN

C_OUT

P_IN

31 mΩ

Protected supply

To Load

R₁

R₂

PGOOD

FLT

UVLO

TPS16632

ON/OFF Control

SHDN

PLIM

IMON

ILIM

Load Monitor

R_IMON

R_PLIM

GND

dVdT

MODE

R_ILIM

C_dVdT

图9-10. TPS16632 Typical Application Schematic

R_PLIM= 100 kΩ

R_ILIM= 3 kΩ

图9-11. 100 W class 2, Output Power Limiting Response of TPS16632

9.3.6 Current Monitoring Output (IMON)

The TPS1663x devices feature an accurate analog current monitoring output. A current source at IMON terminal

is internally configured to be proportional to the current flowing from IN to OUT. This current can be converted

into a voltage using a resistor R_(IMON)from IMON terminal to GND terminal. The IMON voltage can be used as a

means of monitoring current flow through the system. The maximum voltage (V_(IMONmax) for monitoring the

current is limited to 4 V. This limitation puts a limitation on maximum value of R_(IMON)resistor and is determined

by 方程式6.

V

(

IMON

)

= I

[

(

OUT

)

ìGAIN

(

IMON

)

ìR

(

IMON

)

]

(6)

Where,

• GAIN_(IMON)is the gain factor I_(IMON):I_(OUT)= 27.9μA/A (typical)

• I_(OUT)is the load current

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Refer to 图7-9 for IMON output versus load current plot. 图9-12 illustrates IMON performance.

VIN

VOUT

IMON

IIN

图9-12. IMON Response During a Load Step

The IMON pin must not have a bypass capacitor to avoid delay in the current monitoring information.

9.3.7 FAULT Response (FLT)

The FLT open-drain output asserts (active low) under the faults events such as undervoltage, overvoltage,

overload, power limiting, ILIM pin short, and thermal shutdown conditions. The device is designed to eliminate

false reporting by using an internal de-glitch circuit for fault conditions without the need for an external circuitry.

FLT can be left open or connected to GND when not used.

9.3.8 Power Good Output (PGOOD)

The devices feature an open drain Power Good (PGOOD) indicator output. PGOOD can be used for enable-

disable control of the downstream loads like DC/DC converters. PGOOD goes high when the internal FET’s

gate is enhanced. PGOOD goes low when the internal FET turns OFF during a fault event or when SHDN is

pulled low. There is a deglitch of 11.5 msec (typical), t_PGOODR, at the rising edge and 10 msec (typical), t_PGOODF

on falling edge. PGOOD is a rated for 60 V and can be pulled to IN or OUT through a resistor.

,

9.3.9 IN, P_IN, OUT and GND Pins

Connect a minimum of a 0.1-µF capacitor across IN and GND. Connect P_IN and IN together. Do not leave any

of the IN and OUT pins un-connected.

9.3.10 Thermal Shutdown

The device has a built-in overtemperature shutdown circuitry designed to protect the internal FET if the junction

temperature exceeds T_(TSD), 165°C (typical). After the thermal shutdown event, depending upon the mode of

fault response configured as shown in 表 9-1, the device either latches off or commences an auto-retry cycle of

648 msec (typical), t_{(TSD_retry)}after T_J< (_(TSD)– 11°C). During the thermal shutdown, the fault pin FLT pulls low

to indicate a fault condition.

9.3.11 Low Current Shutdown Control (SHDN)

The internal and the external FET and hence the load current can be switched off by pulling the SHDN pin below

0.8-V threshold with a micro-controller GPIO pin or can be controlled remotely with an opto-isolator device. The

device quiescent current reduces to 21 μA (typical) in shutdown state. To assert SHDN low, the pull down must

have sinking capability of at least 10 µA. To enable the device, SHDN must be pulled up to at least 2 V. Once the

device is enabled, the internal FET turns on with dVdT mode.图 9-13 and 图 9-14 illustrate the performance of

SHDN control.

English Data Sheet: SLVSET9

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SHDN

VOUT

SHDN

VOUT

PGOOD

IIN

V_IN= 24 V

C_(dVdT)= 22 nF

V_IN= 24 V

C_(dVdT)= 22 nF

R_LOAD= 24 Ω

图9-13. Turnon Control With SHDN

图9-14. Turnoff Control With SHDN

9.4 Device Functional Modes

The TPS1663x devices respond differently to overload with MODE pin configurations. 表9-1 lists the operational

differences.

表9-1. Device Operational Differences Under Different MODE Configurations

MODE Pin Configuration

Power Limiting, Over Current fault and Thermal Shutdown Operation

Active Current limiting for a maximum duration of t_{CL_PLIM(dly)}. There after Latches OFF.

Latch reset by toggling SHDN or UVLO low to high or power cycling IN.

Open

Active current limiting for a maximum duration of t_{CL_PLIM(dly)}. There after auto-retries after a

Shorted to GND

delay of t_{(TSD_retry)}

.

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10 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

10.1 Application Information

The TPS1663x is a 60-V eFuse, typically used for hot-swap and power rail protection applications. The device

operates from 4.5 V to 60 V with programmable current limit, overvoltage, and undervoltage protections. The

device aids in controlling in-rush current and provides output power limiting for systems such as PLCs, Telecom

radios, and industrial printers. The device also provides robust protection for multiple faults on the system rail.

The Detailed Design Procedure section can be used to select component values for the device. Additionally, a

spreadsheet design tool, TPS1663 Design Calculator, is available in the web product folder.

10.2 Typical Application

VIN: 20 V œ 50 V

VOUT

C_OUT

IN

OUT

P_IN

31mΩ

100 µF

R₁

887 k

PGOOD

FLT

UVLO

OVP

TPS16630

R₂

43 k

ON/OFF Control

SHDN

IMON

ILIM

R₃

20.5 k

R_IMON

30 k

dVdT

22 nF

R_ILIM

18 k

MODE

GND

图10-1. 20 V –50 V, 1-A eFuse Protection Circuit for Telecom Radios

10.2.1 Design Requirements

表10-1 shows the design requirements for TPS16630.

表10-1. Design Requirements

DESIGN PARAMETER

EXAMPLE VALUE

20 V–50 V

18 V

V_(IN)

Input voltage range

V_(UV)

V_(OV)

I_(LIM)

Undervoltage lockout set point

Overvoltage cutoff set point

Overload current limit

Output capacitor

55 V

1 A

C_OUT

I_(INRUSH)

100 µF

Inrush current limit

300 mA

10.2.2 Detailed Design Procedure

10.2.2.1 Programming the Current-Limit Threshold R_(ILIM)Selection

The R_(ILIM)resistor at the ILIM pin sets the overload current limit. The overload current limit can be set using 方

程式7.

18

R₍_ILIM

=

= 18kW

)

I_OL

(7)

English Data Sheet: SLVSET9

24

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where

• I_LIM= 1 A

Choose the closest standard 1% resistor value: R_(ILIM)= 18 kΩ

10.2.2.2 Undervoltage Lockout and Overvoltage Set Point

The undervoltage lockout (UVLO) and overvoltage trip point are adjusted using an external voltage divider

network of R₁, R₂and R₃connected between IN, UVLO, OVP and GND pins of the device. The values required

for setting the undervoltage and overvoltage are calculated by solving 方程式8 and 方程式9.

R³

V^(OVPR)=

ì V^(OV)

R1+ R2 + R3

(8)

R²+ R3

R¹+ R²+ R³

V(UVLOR) =

ì V(UV)

(9)

For minimizing the input current drawn from the power supply [I_(R123)= V_(IN)/ (R₁+ R₂+ R₃)], TI recommends to

use higher value resistance for R₁, R₂and R₃.

However, the leakage current due to external active components connected at resistor string can add error to

these calculations. So, the resistor string current, I(R₁₂₃), must be chosen to be 20 times greater than the

leakage current of UVLO and OVP pins.

From the device electrical specifications, V_(OVPR)= 1.2 V and V_(UVLOR)= 1.2 V. From the design requirements,

V_(OV)is 55 V and V_(UV)is 18 V. To solve the equation, first choose the value of R₃= 20.5 kΩ and use 方程式 8 to

solve for (R₁+ R₂) = 930 kΩ. Use 方程式 9 and value of (R₁+ R₂) to solve for R₂= 43 kΩ and finally R₁= 887

kΩ.

Choose the closest standard 1% resistor values: R₁= 887 kΩ, R₂= 43 kΩ, and R₃= 20.5 kΩ.

10.2.2.3 Setting Output Voltage Ramp Time (t_dVdT

)

Use 方程式 1 and 方程式 2 to calculate required C_(dVdT)for achieving an inrush current of 300 mA. C_(dVdT)= 22

nF. 图10-2 and 图10-3 illustrate the inrush current limiting performance during 50-V hot-plug in condition.

10.2.2.3.1 Support Component Selections R_PGOODand C_(IN)

The R_PGOODserves as pull-up for the open-drain output. The current sink by this pin must not exceed 10 mA

(see the Absolute Maximum Ratings table). TI recommends typical resistance value in the range of 10 kΩto 100

kΩ for R_PGOOD. 图 10-5 and 图 10-7 illustrate the power up and power down performance of the system

respectively. The C_INis a local bypass capacitor to suppress noise at the input. TI recommends a minimum of

0.1 µF for C_(IN)

.

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10.2.3 Application Curves

VIN

VOUT

PGOOD

IIN

图10-2. Hot-Plug In at 50-V Supply With No Load 图10-3. Hot-Plug In at 50-V Supply With 60-ΩLoad

VOUT

IIN

IMON

FLTb

IMON

FLTb

图10-4. Overload Performance During Load Step

From 140 Ωto 40 Ω

图10-5. Coming Out of Overload With Load Step

From 40 Ωto 140 Ω

SHDNb

VOUT

IIN

IMON

FLTb

PGOOD

IIN

图10-6. Output Hot-short Performance With 50-V

图10-7. Turn ON Using SHDN Control

Input Supply

26

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SHDNb

VOUT

PGOOD

IIN

图10-8. Turn OFF Using SHDN Control

10.3 System Examples

10.3.1 Simple 24-V Power Supply Path Protection

With the TPS1663x, a simple 24-V power supply path protection can be realized using a minimum of three

external components, as shown in the schematic diagram in 图 10-9. The external components required are a

R_(ILIM)resistor to program the current limit and C_(IN)and C_(OUT)capacitors.

VOUT

C_OUT

VIN

C_IN

IN

OUT

P_IN

31 mΩ

PGOOD

FLT

UVLO

PLIM

TPS16632

ON/OFF Control

SHDN

IMON

dVdT

ILIM

MODE

R_ILIM

GND

图10-9. TPS16630 Configured for a Simple Power Supply Path Protection

Protection features with this configuration include:

• 39-V (maximum) overvoltage clamp output

• Inrush current control with 24-V/500-µs output voltage slew rate

• Accurate current limiting with auto-retry

10.4 Power Supply Recommendations

The TPS1663x eFuse is designed for the supply voltage range of 4.5 V ≤ V_IN≤ 60 V. If the input supply is

located more than a few inches from the device, TI recommends an input ceramic bypass capacitor higher than

0.1 μF. Power supply must be rated higher than the current limit set to avoid voltage droops during overcurrent

and short circuit conditions.

10.4.1 Transient Protection

In case of short circuit and overload current limit, when the device interrupts current flow, input inductance

generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the

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output. The peak amplitude of voltage spikes (transients) depends on the value of inductance in series to the

input or output of the device. These transients can exceed the Absolute Maximum Ratings of the device if steps

are not taken to address the issue.

Typical methods for addressing transients include:

• Minimizing lead length and inductance into and out of the device

• Using large PCB GND plane

• Using a Schottky diode across the output and GND to absorb negative spikes

• Using low value ceramic capacitor (C_(IN)to approximately 0.1 μF) to absorb the energy and dampen the

transients.

The approximate value of input capacitance can be estimated with 方程式10.

L _IN

( )

V_{spike Absolute}= V _IN+ I _Load

( ) )

´

(

)

(

C _IN

( )

(10)

where

• V_(IN)is the nominal supply voltage

• I_(LOAD)is the load current

• L_(IN)equals the effective inductance seen looking into the source

• C_(IN)is the capacitance present at the input

Some applications can require additional Transient Voltage Suppressor (TVS) to prevent transients from

exceeding the Absolute Maximum Ratings of the device. These transients can occur during positive and

negative surge tests on the supply lines. In such applications, TI recommends to place at least 1 µF of input

capacitor.

The circuit implementation with optional protection components (a ceramic capacitor, TVS and Schottky diode) is

shown in 图10-10

Input

Output

C_OUT

IN

OUT

P_IN

*

31 mΩ

*

R₁

R₂

PGOOD

FLT

UVLO

OVP

TPS16633x

SHDN

IMON

ILIM

R₃

dVdT

C_dVdT

MODE

R_ILIM

GND

^*Optional components needed for suppression of transients

图10-10. Circuit Implementation With Optional Protection Components for TPS1663x

10.5 Layout

10.5.1 Layout Guidelines

• For all the applications, TI recommends a 0.1 µF or higher value ceramic decoupling capacitor between IN

terminal and GND.

• High current carrying power path connections must be as short as possible and must be sized to carry at

least twice the full-load current. See 图10-11 and 图10-12 for a typical PCB layout example.

English Data Sheet: SLVSET9

28

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• Locate all the TPS1663x family support components R_(ILIM), R_(PLIM), C_(dVdT), R_(IMON), UVLO, OVP resistors

close to their connection pin. Connect the other end of the component to the GND with shortest trace length.

• The trace routing for the R_(ILIM), R_(PLIM)component to the device must be as short as possible to reduce

parasitic effects on the current limit and power limit accuracy. These traces must not have any coupling to

switching signals on the board.

• Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the

device they are intended to protect, and routed with short traces to reduce inductance. For example, TI

recommends a protection Schottky diode to address negative transients due to switching of inductive loads,

and it must be physically close to the OUT and GND pins.

• Thermal Considerations: when properly mounted, the PowerPAD package provides significantly greater

cooling ability. To operate at rated power, the PowerPAD must be soldered directly to the board GND plane

directly under the device. Other planes, such as the bottom side of the circuit board, can be used to increase

heat sinking in higher current applications.

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ZHCSIV1F –SEPTEMBER 2018 –REVISED FEBRUARY 2023

10.5.2 Layout Example

Top Layer

Bottom layer GND plane

Top Layer GND Plane

Via to Bottom Layer

BOTTOM Layer GND Plane

High

Frequency

Bypass cap

D2

D1

VOUT PLANE

VIN PLANE

OUT

IN

N.C

PGOOD

N.C

P_IN

N.C

FLT

UVLO

IMON

TOP Layer

GND Plane

BOTTOM Layer GND Plane

图10-11. PCB Layout Example With QFN Package With a 2-Layer PCB

English Data Sheet: SLVSET9

30

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Top Layer

Bottom layer GND plane

Top Layer GND Plane

Via to Bottom Layer

BOTTOM Layer GND Plane

High

Frequency

Bypass cap

D2

D1

VIN PLANE

VOUT PLANE

IN

OUT

IN

N.C

P_IN

UVLO

PGOOD

FLT

IMON

OVP

GND

SHDN

MODE

dVdT

ILIM

TOP Layer

GND Plane

BOTTOM Layer GND Plane

图10-12. Typical PCB Layout Example With HTSSOP Package With a 2-Layer PCB

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ZHCSIV1F –SEPTEMBER 2018 –REVISED FEBRUARY 2023

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

• TPS1663 Design Calculator

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.4 Trademarks

PowerPAD^™and TI E2E^™are trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

11.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

English Data Sheet: SLVSET9

32

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PACKAGE OUTLINE

PWP0020T

PowerPAD^TMTSSOP - 1.2 mm max height

S

C

A

L

E

2

.

3

0

SMALL OUTLINE PACKAGE

C

6.6

6.2

TYP

0.1 C

A

PIN 1 INDEX

AREA

18X 0.65

SEATING

20

PLANE

1

2X

6.6

6.4

5.85

NOTE 3

10

11

0.30

20X

4.5

4.3

0.19

B

0.1

C A B

SEE DETAIL A

(0.15) TYP

2X 1.15 MAX

NOTE 5

11

10

2X 0.3 MAX

NOTE 5

0.25

1.2 MAX

GAGE PLANE

21

2.96

2.21

0.15

0.05

0.75

0.50

THERMAL

PAD

0 -8

A

15

DETAIL A

TYPICAL

1

20

2.96

2.16

4224598/A 10/2018

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0020T

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(3.4)

NOTE 9

(2.96)

METAL COVERED

BY SOLDER MASK

20X (1.5)

SYMM

1

20

20X (0.45)

(R0.05) TYP

(1.3)

TYP

(6.5)

NOTE 9

21

SYMM

(2.96)

SOLDER MASK

DEFINED PAD

18X (0.65)

10

11

(1.3) TYP

SEE DETAILS

(

0.2) TYP

VIA

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

15.000

SOLDER MASK DETAILS

4224598/A 10/2018

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged

or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0020T

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(2.96)

BASED ON

0.125 THICK

STENCIL

METAL COVERED

BY SOLDER MASK

20X (1.5)

1

20

20X (0.45)

(R0.05) TYP

SYMM

21

(2.96)

BASED ON

0.125 THICK

STENCIL

18X (0.65)

11

10

SYMM

(5.8)

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

3.31 X 3.31

2.96 X 2.96 (SHOWN)

2.70 X 2.70

0.125

0.15

0.175

2.50 X 2.50

4224598/A 10/2018

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

GENERIC PACKAGE VIEW

RGE 24

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4204104/H

PACKAGE OUTLINE

VQFN - 1 mm max height

RGE0024H

PLASTIC QUAD FLATPACK- NO LEAD

A

4.1

3.9

B

4.1

3.9

PIN 1 INDEX AREA

1 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ

(0.2) TYP

2X 2.5

12

7

20X 0.5

6

13

25

2X

SYMM

2.5

1

18

0.30

PIN 1 ID

(OPTIONAL)

24X

0.18

24

19

0.1

0.05

C A B

C

SYMM

0.48

0.28

24X

4219016 / A 08/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RGE0024H

PLASTIC QUAD FLATPACK- NO LEAD

(3.825)

2.7)

(

24

19

24X (0.58)

24X (0.24)

1

18

20X (0.5)

25

SYMM

(3.825)

2X

(1.1)

ꢆꢄꢂꢁꢇꢀ9,$

TYP

6

13

(R0.05)

7

12

2X(1.1)

SYMM

LAND PATTERN EXAMPLE

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219016 / A 08/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments

literature number SLUA271 (www.ti.com/lit/slua271).

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RGE0024H

PLASTIC QUAD FLATPACK- NO LEAD

(3.825)

4X ( 1.188)

24

19

24X (0.58)

24X (0.24)

1

18

20X (0.5)

SYMM

(3.825)

(0.694)

TYP

6

13

25

(R0.05) TYP

METAL

TYP

7

12

(0.694)

TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

78% PRINTED COVERAGE BY AREA

SCALE: 20X

4219016 / A 08/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations..

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重要声明和免责声明

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型号:	TPS16630PWPR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
包装说明：	HTSSOP,
Reach Compliance Code：	compliant
Factory Lead Time：	8 weeks
风险等级：	5.63
可调阈值：	YES
模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e4
长度：	6.5 mm
湿度敏感等级：	2
信道数量：	1
功能数量：	1
端子数量：	20
最高工作温度：	125 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	HTSSOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
座面最大高度：	1.2 mm
最大供电电压 (Vsup)：	60 V
最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	24 V
表面贴装：	YES
温度等级：	AUTOMOTIVE
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
宽度：	4.4 mm
Base Number Matches：	1

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