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产品型号TPS2013ADR的概述

TPS2013ADR芯片概述 TPS2013ADR是一款由德州仪器（Texas Instruments）公司推出的用于电源管理的集成电路，专门设计用于提供多重电源轨的电源分配功能。此芯片以其高效能和集成特性而受到电子工程师的广泛欢迎，特别是在便携式设备和各种消费电子应用中。TPS2013ADR 的设计涉及在各种供电条件下保持电源的稳定性，确保系统的可靠性和安全性。 TPS2013ADR的详细参数 TPS2013ADR具有一系列出色的电气参数，包括： - 输入电压范围：该芯片支持较宽的输入电压范围，通常从 2.7V 到 5.5V。 - 电源电压：芯片的工作电压为 5V。 - 输出电流能力：每个通道可提供最大 1.5A 的输出电流，足以满足大多数中小型负载的需求。 - 通道数量：该芯片拥有两个电源输出通道，可独立控制和管理。 - 开关频率：有效的开关频率为 300 kHz，确保快速的响应特...

产品型号TPS2013ADR的Datasheet PDF文件预览

TPS2010A, TPS2011A

TPS2012A, TPS2013A

www.ti.com

SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

POWER-DISTRIBUTION SWITCHES

FEATURES

•

33-mΩ (5-V Input) High-Side MOSFET Switch

•

Short-Circuit and Thermal Protection

Operating Range . . . 2.7 V to 5.5 V

Logic-Level Enable Input

Typical Rise Time. . . 6.1 ms

Undervoltage Lockout

Maximum Standby Supply Current. . . 10 μA

No Drain-Source Back-Gate Diode

Available in 8-pin SOIC and 14-Pin TSSOP

Packages

•

Ambient Temperature Range, –40°C to 85°C

2-kV Human-Body-Model, 200-V

Machine-Model ESD Protection

DESCRIPTION

The TPS201xA family of power distribution switches is intended for applications where heavy capacitive loads

and short circuits are likely to be encountered. These devices are 50-mΩ N-channel MOSFET high-side power

switches. The switch is controlled by a logic enable compatible with 5-V logic and 3-V logic. Gate drive is

provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize

current surges during switching. The charge pump requires no external components and allows operation from

supplies as low as 2.7 V.

When the output load exceeds the current-limit threshold or a short is present, the TPS201xA limits the output

current to a safe level by switching into a constant-current mode. When continuous heavy overloads and short

circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal

protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once

the device has cooled sufficiently. Internal circuitry ensures the switch remains off until valid input voltage is

present.

TPS2014 600 mA

TPS201xA 0.2 A - 2 A

TPS2015 1 A

TPS202x

TPS203x

0.2 A - 2 A

TPS2041B 500 mA

TPS2051B 500 mA

TPS2045A 250 mA

TPS2049 100 mA

TPS2055A 250 mA

TPS2061 1 A

TPS2065 1 A

TPS2068 1.5 A

TPS2069 1.5 A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS2010A, TPS2011A

TPS2012A, TPS2013A

www.ti.com

SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

The TPS201xA devices differ only in short-circuit current threshold. The TPS2010A limits at 0.3-A load, the

TPS2011 at 0.9-A load, the TPS2012A at 1.5-A load, and the TPS2013A at 2.2-A load (see Available Options).

The TPS201xA is available in an 8-pin small-outline integrated-circuit (SOIC) package and in a 14-pin thin-shrink

small-outline package (TSSOP) and operates over a junction temperature range of -40°C to 125°C.)

AVAILABLE OPTIONS

RECOMMENDED

MAXIMUM CONTINUOUS

LOAD CURRENT

(A)

PACKAGED DEVICES⁽¹⁾

TYPICAL SHORT-CIRCUIT

CURRENT LIMIT AT 25°C

(A)

SMALL OUTLINE

TSSOP

T_A

ENABLE

(D)⁽²⁾

(PWP)⁽³⁾

0.2

0.6

0.3

0.9

1.5

2.2

TPS2010AD

TPS2011AD

TPS2012AD

TPS2013AD

TPS2010APWPR

TPS2011APWPR

TPS2012APWPR

TPS2013APWPR

–40°C to 85°C

Active low

1.5

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2010DR)

(3) The PWP package is only available left-end taped-and-reeled.

TPS201xA FUNCTIONAL BLOCK DIAGRAM

TERMINAL FUNCTIONS

TERMINAL

NO.

I/O

DESCRIPTION

NAME

PWP

Enable input. Logic low turns on power switch.

GND

Ground

2, 3

5–8

2–6

8–14

Input voltage

Power-switch output

OUT

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SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

DETAILED DESCRIPTION

POWER SWITCH

The power switch is an N-channel MOSFET with a maximum on-state resistance of 50 mΩ (V_I(IN)= 5V).

Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when

disabled.

CHARGE PUMP

An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate

of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires

very little supply current.

DRIVER

The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated

electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall

times of the output voltage. The rise and fall times are typically in the 2-ms to 9-ms range.

ENABLE (EN)

The logic enable disables the power switch, the bias for the charge pump, driver, and other circuitry to reduce the

supply current to less than 10 μA when a logic high is present on EN . A logic zero input on EN restores bias to

the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS

logic levels.

CURRENT SENSE

A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than

conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry

sends a control signal to the driver. The driver, in turn, reduces the gate voltage and drives the power FET into

its saturation region, which switches the output into a constant current mode and holds the current constant while

varying the voltage on the load.

THERMAL SENSE

An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to approximately

140°C. Hysteresis is built into the thermal sense circuit. After the device has cooled approximately 20°C, the

switch turns back on. The switch continues to cycle off and on until the fault is removed.

UNDERVOLTAGE LOCKOUT

A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control

signal turns off the power switch.

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TPS2010A, TPS2011A

TPS2012A, TPS2013A

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SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

VALUE

–0.3 to 6

UNIT

V_I(IN)

Input voltage range⁽²⁾

Output voltage range⁽²⁾

V_O(OUT)

V_I(EN)

–0.3 to V_I(IN)+ 0.3

–0.3 to 6

Input voltage range

I_O(OUT)

Continuous output current

Internally Limited

Continuous total power dissipation

Operating virtual junction temperature range

Storage temperature range

See Dissipation Rating Table

T_J

–40 to 125

°C

T_stg

–65 to 150

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds

260

Human body model

Electrostatic discharge protection

Machine model

ESD

200

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND.

DISSIPATION RATINGS

_A≤ 25°C

DERATING FACTOR

ABOVE T_A= 25°C

T_A= 70°C

POWER RATING

T_A= 85°C

POWER RATING

PACKAGE

POWER RATING

725 mW

5.8 mW/°C

5.6 mW/°C

464 mW

448 mW

377 mW

364 mW

PWP

700 mW

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

2.7

MAX

5.5

0.2

0.6

UNIT

V_I(IN)

Input voltage

V_IH

TPS2010A

TPS2011A

I_O

Continuous output current

TPS2012A

TPS2013A

1.5

125

T_J

Operating virtual junction temperature

–40

°C

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SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

ELECTRICAL CHARACTERISTICS

over recommended operating junction temperature range, V_I(IN)= 5.5 V, I_O= rated current, EN = 0 V (unless otherwise noted)

PARAMETER

POWER SWITCH

TEST CONDITIONS⁽¹⁾

MIN

TYP

MAX UNIT

V_I(IN)= 5 V,

T_J= 25°C,

T_J= 85°C,

T_J= 125°C,

T_J= 25°C,

T_J= 85°C,

T_J= 125°C,

T_J= 25°C,

T_J= 85°C,

T_J= 125°C,

T_J= 25°C,

T_J= 85°C,

T_J= 125°C,

T_J= 25°C,

I_O= 1.5 A

I_O= 0.18 A

C_L= 1 μF,

6.1

8.6

3.4

V_I(IN)= 5 V,

TPS2013A

TPS2010A

mΩ

V_I(IN)= 3.3 V,

V_I(IN)= 5 V,

Static drain-source on-state

resistance

r_DS(on)

V_I(IN)= 5 V,

mΩ

V_I(IN)= 3.3 V,

V_I(IN)= 5.5 V,

V_I(IN)= 2.7 V,

V_I(IN)= 5.5 V,

V_I(IN)= 2.7 V,

R_L= 10 Ω

t_r

t_f

Rise time, output

ENABLE INPUT (EN)

V_IH

High-level input voltage

2.7 V ≤ V_I(IN)≤ 5.5 V

4.5 V ≤ V_I(IN)≤ 5.5 V

2.7 V ≤ V_I(IN)≤ 4.5 V

EN = 0 V or EN = V_I(IN)

C_L= 100 μF,

0.8

V_IL

Low-level input voltage

0.5

I_I

Input current

Turnon time

Turnoff time

–0.5

0.5

μA

t_on

t_off

R_L= 10 Ω

C_L= 100 μF,

CURRENT LIMIT

TPS2010A

TPS2011A

TPS2012A

TPS2013A

0.22

0.66

1.1

0.3

0.9

1.5

2.2

0.4

1.1

1.8

2.7

T_J= 25°C, V_I= 5.5 V,

OUT connected to GND,

Device enable into short circuit

I_OS

Short-circuit output current

1.65

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account

separately.

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TPS2010A, TPS2011A

TPS2012A, TPS2013A

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SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

ELECTRICAL CHARACTERISTICS (Continued)

over recommended operating junction temperature range, V_I(IN)= 5.5 V, I_O= rated current, EN = 0 V (unless otherwise noted)

PARAMETER

SUPPLY CURRENT

TEST CONDITIONS⁽¹⁾

MIN TYP MAX UNIT

T_J= 25°C

0.3

Supply current, low-level output

Supply current, high-level output

No Load on OUT

EN = V_I(IN)

EN = 0 V

μA

–40°C ≤ T_J≤ 125°C

T_J= 25°C

μA

–40°C ≤ T_J≤ 125°C

75 100

Leakage current

OUT connected to ground EN = V_I(IN)

UNDERVOLTAGE LOCKOUT

Low-level input voltage

Hysteresis

2.5

T_J= 25°C

100

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account

separately.

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TPS2010A, TPS2011A

TPS2012A, TPS2013A

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SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

PARAMETER MEASUREMENT INFORMATION

Figure 1. Test Circuit and Voltage Waveforms

Table 1. Timing Diagrams

FIGURE

Turnon Delay and Rise Time

Turnoff Delay and Fall Time

Turnon Delay and Rise TIME with 1-μF Load

Turnoff Delay and Rise TIME with 1-μF Load

Device Enabled into Short

TPS2010A, TPS2011A, TPS2012A, and TPS2013A, Ramped Load on Enabled Device

TPS2013A, Inrush Current

7, 8, 9, 10

7.9-Ω Load Connected to an Enabled TPS2010A Device

3.7-Ω Load Connected to an Enabled TPS2010A Device

3.7-Ω Load Connected to an Enabled TPS2011A Device

2.6-Ω Load Connected to an Enabled TPS2011A Device

2.6-Ω Load Connected to an Enabled TPS2012A Device

1.2-Ω Load Connected to an Enabled TPS2012A Device

1.2-Ω Load Connected to an Enabled TPS2013A Device

0.9-Ω Load Connected to an Enabled TPS2013A Device

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TPS2012A, TPS2013A

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SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

Figure 2. Turnon Delay and Rise Time

Figure 3. Turnoff Delay and Fall Time

Figure 4. Turnon Delay and Rise Time With 1-μF Load

Figure 5. Turnoff Delay and Fall Time With 1-μF Load

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SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

Figure 6. Device Enabled Into Short

Figure 7. TPS2010A, Ramped Load on Enabled Device

Figure 8. TPS2011A, Ramped Load on Enabled Device

Figure 9. TPS2012A, Ramped Load on Enabled Device

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SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

Figure 10. TPS2013A, Ramped Load on Enabled Device

Figure 11. TPS2013A, Inrush Current

Figure 12. 7.9-Ω Load Connected to an Enabled

Figure 13. 3.7-Ω Load Connected to an Enabled

TPS2010A Device

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SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

Figure 14. 3.7-Ω Load Connected to an Enabled

Figure 15. 2.6-Ω Load Connected to an Enabled

TPS2011A Device

Figure 16. 2.6-Ω Load Connected to an Enabled

Figure 17. 1.2-Ω Load Connected to an Enabled

TPS2012A Device

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SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

Figure 18. 1.2-Ω Load Connected to an Enabled TPS2013A Device

Figure 19. 0.9-Ω Load Connected to an Enabled TPS2013A Device

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SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

t_d(on)

t_d(off)

t_r

Turnon delay time

vs Output voltage

Turnoff delay time

vs Input voltage

Rise time

vs Load current

t_f

Fall time

vs Load current

Supply current (enabled)

Supply current (disabled)

Supply current (enabled)

Supply current (disabled)

Short-circuit current limit

vs Junction temperature

vs Input voltage

I_OS

vs Input voltage

vs Junction temperature

vs Input voltage

r_DS(on)

Static drain-source on-state resistance

vs Junction temperature

vs Input voltage

vs Junction temperature

Input voltage vs Temperature

Undervoltage lockout

TURNON DELAY TIME

OUTPUT VOLTAGE

TURNOFF DELAY TIME

INPUT VOLTAGE

Figure 20.

Figure 21.

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SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

RISE TIME

LOAD CURRENT

FALL TIME

LOAD CURRENT

Figure 22.

Figure 23.

SUPPLY CURRENT (ENABLED)

JUNCTION TEMPERATURE

SUPPLY CURRENT (DISABLED)

JUNCTION TEMPERATURE

Figure 24.

Figure 25.

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SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

SUPPLY CURRENT (ENABLED)

SUPPLY CURRENT (DISABLED)

INPUT VOLTAGE

Figure 26.

Figure 27.

SHORT-CIRCUIT CURRENT LIMIT

INPUT VOLTAGE

JUNCTION TEMPERATURE

Figure 28.

Figure 29.

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SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

INPUT VOLTAGE

JUNCTION TEMPERATURE

Figure 30.

Figure 31.

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

INPUT VOLTAGE

JUNCTION TEMPERATURE

Figure 32.

Figure 33.

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SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

UNDERVOLTAGE LOCKOUT

Figure 34.

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SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

APPLICATION INFORMATION

Figure 35. Typical Application

POWER-SUPPLY CONSIDERATIONS

A 0.01-μF to 0.1-μF ceramic bypass capacitor between IN and GND, close to the device, is recommended.

Placing a high-value electrolytic capacitor on the output and input pins is recommended when the output load is

heavy. This precaution reduces power supply transients that may cause ringing on the input. Additionally,

bypassing the output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to

short-circuit transients.

OVERCURRENT

A sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the

series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant

output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present

long enough to activate thermal limiting.

Three possible overload conditions can occur. In the first condition, the output has been shorted before the

device is enabled or before V_I(IN)has been applied (see Figure 6). The TPS201xA senses the short and

immediately switches into a constant-current output.

In the second condition, the excessive load occurs while the device is enabled. At the instant the excessive load

occurs, very high currents may flow for a short time before the current-limit circuit can react (see

Figure 12–Figure 19). After the current-limit circuit has tripped (reached the overcurrent trip threshold) the device

switches into constant-current mode.

In the third condition, the load has been gradually increased beyond the recommended operating current. The

current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is

exceeded (see Figures Figure 77–Figure 10). The TPS201xA is capable of delivering current up to the

current-limit threshold without damaging the device. Once the threshold has been reached, the device switches

into its constant-current mode.

POWER DISSIPATION AND JUNCTION TEMPERATURE

The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass

large currents. The thermal resistance of these packages are high compared to those of power packages; it is

good design practice to check power dissipation and junction temperature. The first step is to find r_DS(on)at the

input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of

interest and read r_DS(on)from SLVS1892074Figure 30–Figure 33 . Next, calculate the power dissipation using:

+ r

DS(on)

(1)

(2)

Finally, calculate the junction temperature:

T + P R ) T

qJA

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SLVS189C–DECEMBER 1998–REVISED SEPTEMBER 2007

Where:

T_A= Ambient Temperature °C

_θJA= Thermal resistance SOIC = 172°C/W

Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,

repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally

sufficient to get an acceptable answer.

THERMAL PROTECTION

Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for

extended periods of time. The faults force the TPS201xA into constant current mode, which causes the voltage

across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal to

the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The protection

circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal sense

circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues

to cycle in this manner until the load fault or input power is removed.

UNDERVOLTAGE LOCKOUT (UVLO)

An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input

voltage falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of

hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The

UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if the

switch is enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce EMI

and voltage overshoots.

GENERIC HOT-PLUG APPLICATIONS (see Figure 36)

In many applications it may be necessary to remove modules or p-c boards while the main unit is still operating.

These are considered hot-plug applications. Such implementations require the control of current surges seen by

the main power supply and the card being inserted. The most effective way to control these surges is to limit and

slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply

normally turns on. Because of the controlled rise times and fall times of the TPS201xA series, these devices can

be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of

the TPS201xA also ensures the switch will be off after the card has been removed, and the switch will be off

during the next insertion. The UVLO feature guarantees a soft start with a controlled rise time for every insertion

of the card or module.

Figure 36. Typical Hot-Plug Implementation

By placing the TPS201xA between the V_CCinput and the rest of the circuitry, the input power will reach this

device first after insertion. The typical rise time of the switch is approximately 9 ms, providing a slow voltage

ramp at the output of the device. This implementation controls system surge currents and provides a

hot-plugging mechanism for any device.

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PACKAGE OPTION ADDENDUM

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30-Jul-2011

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

TPS2010AD

TPS2010ADG4

TPS2010ADR

TPS2010ADRG4

TPS2011AD

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-1-260C-UNLIM

SOIC

2500

Green (RoHS

& no Sb/Br)

SOIC

Green (RoHS

& no Sb/Br)

SOIC

Green (RoHS

& no Sb/Br)

TPS2011ADG4

TPS2011ADR

TPS2011ADRG4

TPS2011APWP

TPS2011APWPG4

TPS2012AD

SOIC

Green (RoHS

& no Sb/Br)

SOIC

2500

Green (RoHS

& no Sb/Br)

SOIC

Green (RoHS

& no Sb/Br)

HTSSOP

SOIC

PWP

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TPS2012ADG4

TPS2012ADR

TPS2012ADRG4

TPS2013AD

SOIC

Green (RoHS

& no Sb/Br)

SOIC

2500

Green (RoHS

& no Sb/Br)

SOIC

Green (RoHS

& no Sb/Br)

SOIC

Green (RoHS

& no Sb/Br)

TPS2013ADG4

TPS2013ADR

SOIC

Green (RoHS

& no Sb/Br)

SOIC

2500

Green (RoHS

& no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

30-Jul-2011

Status ⁽¹⁾

ACTIVE

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

TPS2013ADRG4

TPS2013APWP

SOIC

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

HTSSOP

PWP

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

TPS2013APWPG4

TPS2013APWPR

TPS2013APWPRG4

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS2010ADR

TPS2011ADR

TPS2012ADR

TPS2013ADR

TPS2013APWPR

SOIC

2500

2000

330.0

12.4

6.4

6.9

5.2

5.6

2.1

1.6

8.0

12.0

HTSSOP PWP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS2010ADR

TPS2011ADR

TPS2012ADR

TPS2013ADR

TPS2013APWPR

SOIC

2500

2000

340.5

367.0

338.1

367.0

20.6

35.0

SOIC

HTSSOP

PWP

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which

have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such

components to meet such requirements.

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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TPS2013ADR产品参数

型号:	TPS2013ADR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	SOIC
包装说明：	SOIC-8
针数：	8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	0.81
Is Samacsys：	N
可调阈值：	NO
模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e4
长度：	4.9 mm
湿度敏感等级：	1
信道数量：	1
功能数量：	1
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1.58 mm
最大供电电流 (Isup)：	0.1 mA
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.91 mm
Base Number Matches：	1

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