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产品型号TPS2114的Datasheet PDF文件预览

TPS2114  
TPS2115  
(
3
,
1
0
m
m
x
4
,
5
0
m
m
)
www.ti.com  
SLVS447ADECEMBER 2002REVISED MARCH 2004  
AUTOSWITCHING POWER MULTIPLEXER  
FEATURES  
Available in a TSSOP-8 Package  
Two-Input, One-Output Power Multiplexer  
With Low rDS(on) Switches:  
APPLICATIONS  
PCs  
PDAs  
– 84 mTyp (TPS2115)  
– 120 mTyp (TPS2114)  
Digital Cameras  
Modems  
Cell phones  
Digital Radios  
MP3 Players  
Reverse and Cross-Conduction Blocking  
Wide Operating Voltage Range: 2.8 V to 5.5 V  
Low Standby Current: 0.5 µA Typical  
Low Operating Current: 55 µA Typical  
Adjustable Current Limit  
PW PACKAGE  
(TOP VIEW)  
Controlled Output Voltage Transition Times,  
Limits Inrush Current and Minimizes Output  
Voltage Hold-Up Capacitance  
1
2
3
4
8
7
6
5
STAT  
D0  
IN1  
OUT  
IN2  
CMOS and TTL Compatible Control Inputs  
Manual and Auto-Switching Operating Modes  
Thermal Shutdown  
D1  
ILIM  
GND  
DESCRIPTION  
The TPS211x family of power multiplexers enables seamless transition between two power supplies, such as a  
battery and a wall adapter, each operating at 2.8-5.5 V and delivering up to 1 A. The TPS211x family includes  
extensive protection circuitry, including user-programmable current limiting, thermal protection, inrush current  
control, seamless supply transition, cross-conduction blocking, and reverse-conduction blocking. These features  
greatly simplify designing power multiplexer applications.  
TYPICAL APPLICATION  
Switch Status  
IN1: 2.8 - 5.5 V  
TPS2115PW  
R1  
0.1 µF  
1
2
3
4
8
7
6
5
IN1  
OUT  
IN2  
STAT  
D0  
D1  
R
L
C
L
ILIM  
GND  
R
ILIM  
IN2: 2.8 - 5.5 V  
0.1 µF  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2002–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
TPS2114  
TPS2115  
www.ti.com  
SLVS447ADECEMBER 2002REVISED MARCH 2004  
These devices have limited built-in ESD protection. The leads should be shorted together or the device  
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.  
AVAILABLE OPTIONS  
FEATURE  
TPS2110  
0.31-0.75A  
Yes  
TPS2111  
0.63-1.25A  
Yes  
TPS2112  
0.31-0.75A  
No  
TPS2113  
0.63-1.25A  
No  
TPS2114  
0.31-0.75A  
Yes  
TPS2115  
0.63-1.25A  
Yes  
Current limit adjustment range  
Manual  
Switching modes  
Automatic  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Switch status output  
Package  
No  
No  
Yes  
Yes  
Yes  
Yes  
TSSOP-8  
TSSOP-8  
TSSOP-8  
TSSOP-8  
TSSOP-8  
TSSOP-8  
ORDERING INFORMATION  
TA  
PACKAGE  
ORDERING NUMBER(1)  
MARKINGS  
2114  
TPS2114PW  
TPS2115PW  
-40°C to 85°C  
TSSOP-8 (PW)  
2115  
(1) The PW package is available taped and reeled. Add an R suffix to the device type (e.g., TPS2114PWR) to indicate tape and reel.  
PACKAGE DISSIPATION RATINGS  
DERATING FACTOR  
ABOVE TA = 25°C  
T
A 25°C  
TA = 70°C  
POWER RATING  
TA = 85°C  
POWER RATING  
PACKAGE  
POWER RATING  
TSSOP-8 (PW)  
3.87 mW/°C  
386.84 mW  
212.76 mW  
154.73 mW  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range unless otherwise noted(1)  
TPS2114, TPS2115  
-0.3 V to 6 V  
-0.3 V to 6 V  
5 mA  
VI  
Input voltage range  
Output voltage range(2)  
Output sink current  
IN1, IN2, D0, D1, ILIM(2)  
OUT, STAT  
STAT  
VO  
IO  
TPS2114  
0.9 A  
IO  
Continuous output current  
TPS2115  
1.5 A  
Continuous total power dissipation  
See Dissipation Rating Table  
-40°C to 125°C  
-65°C to 150°C  
260°C  
TJ  
Operating virtual junction temperature range  
Storage temperature range  
Tstg  
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltages are with respect to GND.  
2
TPS2114  
TPS2115  
www.ti.com  
SLVS447ADECEMBER 2002REVISED MARCH 2004  
RECOMMENDED OPERATING CONDITIONS  
MIN  
1.5  
2.8  
1.5  
2.8  
0
MAX  
5.5  
UNIT  
V
I(IN2) 2.8 V  
VI  
Input voltage at IN1  
V
VI(IN2) < 2.8 V  
5.5  
V
I(IN1) 2.8 V  
5.5  
VI  
Input voltage at IN2  
V
V
VI(IN1) < 2.8 V  
5.5  
VI  
Input voltage at D0, D1  
5.5  
TPS2114  
TPS2115  
0.31  
0.63  
-40  
0.75  
1.25  
125  
IO(OUT)  
TJ  
Current limit adjustment range  
Operating virtual junction temperature  
A
°C  
ELECTROSTATIC DISCHARGE (ESD) PROTECTION  
MIN  
MAX  
2
UNIT  
kV  
Human body model  
CDM  
500  
V
ELECTRICAL CHARACTERISTICS  
over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, R(ILIM) = 400 (unless otherwise noted)  
TPS2114  
MIN TYP  
TPS2115  
PARAMETER  
POWER SWITCH  
TEST CONDITIONS  
UNIT  
MAX  
MIN TYP MAX  
VI(IN1) = VI(IN2) = 5.0 V  
120  
120  
120  
140  
140  
140  
220  
220  
220  
84 110  
84 110  
84 110  
150  
TJ = 25°C,  
IL= 500 mA  
VI(IN1) = VI(IN2) = 3.3 V  
VI(IN1) = VI(IN2) = 2.8 V  
VI(IN1) = VI(IN2) = 5.0 V  
VI(IN1) = VI(IN2) = 3.3 V  
VI(IN1) = VI(IN2) = 2.8 V  
mΩ  
mΩ  
Drain-source on-state  
resistance (INx-OUT)  
(1)  
rDS(on)  
TJ = 125°C,  
IL= 500 mA  
150  
150  
(1) The TPS211x can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this specific  
case, the lower supply voltge has no effect on the IN1 and IN2 switch on-resistances.  
3
TPS2114  
TPS2115  
www.ti.com  
SLVS447ADECEMBER 2002REVISED MARCH 2004  
ELECTRICAL CHARACTERISTICS  
over operating free-air temperature range (unless otherwise noted)  
TPS2115  
PARAMETER  
LOGIC INPUTS (D0 AND D1)  
TEST CONDITIONS  
UNIT  
MIN TYP MAX  
VIH  
VIL  
High-level input voltage  
Low-level input voltage  
2
V
V
0.7  
1
D0 or D1 = High, sink current  
D0 or D1 = Low, source current  
Input current at D0 or D1  
µA  
µA  
0.5  
1.4  
5
SUPPLY AND LEAKAGE CURRENTS  
D1 = High, D0 = Low (IN1 active), VI(IN1) = 5.5 V,  
VI(IN2) = 3.3 V, IO(OUT) = 0 A  
55  
1
90  
12  
75  
1
D1 = High, D0 = Low (IN1 active), VI(IN1) = 3.3 V,  
VI(IN2) = 5.5 V, IO(OUT) = 0 A  
Supply current from IN1 (operating)  
D0 = D1 = Low (IN2 active), VI(IN1) = 5.5 V,  
VI(IN2) = 3.3 V, IO(OUT) = 0 A  
D0 = D1 = Low (IN2 active), VI(IN1) = 3.3 V,  
VI(IN2) = 5.5 V, IO(OUT) = 0 A  
D1 = High, D0 = Low (IN1 active), VI(IN1) = 5.5 V,  
VI(IN2) = 3.3 V, IO(OUT) = 0 A  
1
D1 = High, D0 = Low (IN1 active), VI(IN1) = 3.3 V,  
VI(IN2) = 5.5 V, IO(OUT) = 0 A  
75  
12  
90  
2
Supply current from IN2 (operating)  
µA  
D0 = D1 = Low (IN2 active), VI(IN1) = 5.5 V,  
VI(IN2)= 3.3 V, IO(OUT) = 0 A  
1
55  
D0 = D1 = Low (IN2 active), VI(IN1) = 3.3 V,  
VI(IN2) = 5.5 V, IO(OUT) = 0 A  
D0 = D1 = High (inactive), VI(IN1) = 5.5 V,  
VI(IN2) = 3.3 V, IO(OUT) = 0 A  
0.5  
Quiescent current from IN1 (STANDBY)  
Quiescent current from IN2 (STANDBY)  
µA  
µA  
D0 = D1 = High (inactive), VI(IN1) = 3.3 V,  
VI(IN2) = 5.5 V, IO(OUT) = 0 A  
1
D0 = D1 = High (inactive), VI(IN1) = 5.5 V,  
VI(IN2) = 3.3 V, IO(OUT) = 0 A  
1
D0 = D1 = High (inactive), VI(IN1) = 3.3 V,  
VI(IN2) = 5.5 V, IO(OUT) = 0 A  
0.5  
0.1  
0.1  
0.3  
2
Forward leakage current from IN1  
(measured from OUT to GND)  
D0 = D1 = High (inactive), VI(IN1) = 5.5 V, IN2 open,  
VO(OUT) = 0 V (shorted), TJ = 25°C  
5
µA  
µA  
µA  
Forward leakage current from IN2  
(measured from OUT to GND)  
D0 = D1= High (inactive), VI(IN2) = 5.5 V, IN1 open,  
VO(OUT)= 0 V (shorted), TJ = 25°C  
5
Reverse leakage current to INx  
(measured from INx to GND)  
D0 = D1 = High (inactive), VI(INx) = 0 V,  
VO(OUT) = 5.5 V, TJ = 25°C  
5
CURRENT LIMIT CIRCUIT  
R(ILIM) = 400 Ω  
R(ILIM) = 700 Ω  
R(ILIM) = 400 Ω  
R(ILIM) = 700 Ω  
0.51 0.63  
0.30 0.36  
0.95 1.25  
0.47 0.71  
0.80  
0.50  
1.56  
0.99  
TPS2114  
Current limit  
A
accuracy  
TPS2115  
Time for short-circuit output current to settle within  
10% of its steady state value.  
td  
Current limit settling time(1)  
Input current at ILIM  
1
ms  
µA  
VI(ILIM) = 0 V, IO(OUT) = 0 A  
-15  
0
(1) Not tested in production.  
4
TPS2114  
TPS2115  
www.ti.com  
SLVS447ADECEMBER 2002REVISED MARCH 2004  
ELECTRICAL CHARACTERISTICS (continued)  
over operating free-air temperature range (unless otherwise noted)  
TPS2115  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN TYP MAX  
UNDERVOLTAGE LOCKOUT  
Falling edge  
1.15 1.25  
IN1 and IN2 UVLO  
Rising edge  
IN1 and IN2 UVLO hysteresis(2)  
V
1.30  
57  
1.35  
30  
65 mV  
Falling edge  
Internal VDD UVLO (the higher of IN1 and IN2)  
Rising edge  
24 2.53  
2.58  
V
2.8  
Internal VDD UVLO hysteresis(2)  
UVLO deglitch for IN1, IN2(2)  
30  
50  
75 mV  
µs  
Falling edge  
110  
REVERSE CONDUCTION BLOCKING  
D0 = D1 = high, VI(INx) = 3.3 V. Connect OUT to a 5  
V supply through a series 1-kresistor. Let  
D0 = low. Slowly decrease the supply voltage until  
OUT connects to IN1.  
Minimum output-to-input voltage  
VO(I_block)  
80 100  
120 mV  
difference to block switching  
THERMAL SHUTDOWN  
Thermal shutdown threshold(2)  
Recovery from thermal shutdown(2)  
Hysteresis(2)  
TPS211x is in current limit.  
TPS211x is in current limit.  
135  
125  
°C  
10  
IN2-IN1 COMPARATORS  
Hysteresis of IN2-IN1 comparator  
Deglitch of IN2-IN1 comparator, (both)(2)  
STAT OUTPUT  
0.1  
0.2  
V
90 150  
220  
µs  
Leakage current  
VO(STAT) = 5.5 V  
0.01  
0.13  
150  
1
µA  
V
Saturation voltage  
II(STAT) = 2 mA, IN1 switch is on  
0.4  
Deglitch time (falling edge only)  
µs  
(2) Not tested in production.  
5
TPS2114  
TPS2115  
www.ti.com  
SLVS447ADECEMBER 2002REVISED MARCH 2004  
SWITCHING CHARACTERISTICS  
over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, R(ILIM) = 400 (unless otherwise noted)  
TPS2114  
MIN TYP  
TPS2115  
PARAMETER  
POWER SWITCH  
TEST CONDITIONS  
UNIT  
MAX MIN TYP MAX  
TJ = 25°C, CL = 1 µF,  
IL = 500 mA,  
See Figure 1(a)  
Output rise time from an  
enable(1)  
tr  
tf  
VI(IN1) = VI(IN2) = 5 V  
0.5  
1.0  
0.5  
40  
1.5  
0.7  
60  
1
1.8  
1
3
2
ms  
ms  
TJ = 25°C, CL = 1 µF,  
IL = 500 mA,  
See Figure 1(a)  
Output fall time from a  
disable(1)  
VI(IN1) = VI(IN2) = 5 V  
0.35  
0.5  
IN1 to IN2 transition,  
VI(IN1) = 3.3 V,  
VI(IN2) = 5 V  
TJ = 125°C,  
CL = 10 µF,  
40  
60  
IL= 500 mA [Measure  
transition time as  
10-90% rise time or  
from 3.4 V to 4.8 V  
on VO(OUT)],  
tt  
Transition time(1)  
µs  
IN2 to IN1 transition,  
VI(IN1) = 5 V,  
VI(IN2) = 3.3 V  
40  
60  
40  
60  
See Figure 1(b)  
TJ = 25°C,  
VI(IN1)= VI(IN2) = 5 V,  
Measured from enable  
to 10% of VO(OUT)  
Turnon propagation delay  
from enable(1)  
CL = 10 µF,  
IL= 500 mA,  
SeeFigure 1(a)  
tPLH1  
0.5  
3
1
5
ms  
ms  
TJ = 25°C,  
VI(IN1) = VI(IN2) = 5 V,  
Measured from disable  
to 90% of VO(OUT)  
Turnoff propagation delay  
from a disable(1)  
CL = 10 µF,  
IL= 500 mA,  
See Figure 1(a)  
tPHL1  
Logic 1 to Logic 0 tran-  
sition on D1,  
VI(IN1) = 1.5 V,  
VI(IN2) = 5 V,  
VI(D0)= 0 V,  
TJ = 25°C,  
Switch-over rising  
CL = 10 µF,  
IL= 500 mA,  
See Figure 1(c)  
tPLH2  
0.17  
1
0.17  
1
ms  
ms  
propagation delay(1)  
Measured from D1 to  
10% of VO(OUT)  
Logic 0 to Logic 1 tran-  
sition on D1,  
VI(IN1) = 1.5 V,  
VI(IN2) = 5V,  
VI(D0)= 0 V, Measured  
from D1 to 90% of  
VO(OUT)  
TJ = 25°C,  
Switch-over falling  
CL = 10 µF,  
IL= 500 mA,  
See Figure 1(c)  
tPHL2  
2
3
10  
2
5
10  
propagation delay(1)  
(1) Not tested in production.  
TRUTH TABLE  
D1  
0
D0  
0
VI(IN2) > VI(IN1)  
STAT  
Hi-Z  
0
OUT(1)  
IN2  
X
No  
Yes  
X
0
1
IN1  
0
1
Hi-Z  
0
IN2  
1
0
IN1  
1
1
X
0
Hi-Z  
(1) The under-voltage lockout circuit causes the output OUT to go Hi-Z  
if the selected power supply does not exceed the IN1/IN2 UVLO, or  
if neither of the supplies exceeds the internal VDD UVLO.  
6
TPS2114  
TPS2115  
www.ti.com  
SLVS447ADECEMBER 2002REVISED MARCH 2004  
Terminal Functions  
TERMINAL  
I/O DESCRIPTION  
NAME  
NO.  
2
D0  
I
I
I
I
TTL and CMOS compatible input pins. Each pin has a 1-µA pullup resistor. The truth table shown above illustrates  
the functionality of D0 and D1.  
D1  
3
GND  
IN1  
5
Ground  
8
Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO threshold and  
at least one supply exceeds the internal VDD UVLO.  
IN2  
6
4
I
I
Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is above the UVLO threshold  
and at least one supply exceeds the internal VDD UVLO.  
ILIM  
A resistor R(ILIM) from ILIM to GND sets the current limit IL to 250/R(ILIM) and 500/R(ILIM) for the TPS2114 and  
TPS2115, respectively.  
OUT  
7
1
O
O
Power switch output  
STAT  
STAT is an open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1 switch is ON or if OUT is  
Hi-Z (i.e., EN is equal to logic 0).  
FUNCTIONAL BLOCK DIAGRAM  
Internal V  
DD  
1 µA  
1 µA  
V = 0 V  
f
V = 0 V  
f
I
O(OUT)  
Q1  
8
6
7
4
IN1  
IN2  
OUT  
ILIM  
Q2  
Charge  
Pump  
k* I  
O(OUT)  
TPS2114: k = 0.2%  
TPS2115: k = 0.1%  
V
DD  
_
+
ULVO  
0.5 V  
IN2  
ULVO  
Cross-Conduction  
Detector  
+
IN1  
ULVO  
+
0.6 V  
+
_
_
EN2  
EN1  
Q1 is ON  
Q2 is ON  
UVLO (V  
100 mV  
+
)
DD  
V
> V  
I(INx)  
O(OUT)  
+
_
UVLO (IN2)  
UVLO (IN1)  
D0  
EN1  
2
3
D0  
D1  
Thermal  
Sense  
Control  
Logic  
D1  
IN2  
+
_
5
GND  
IN1  
1
STAT  
Q2 is ON  
7
TPS2114  
TPS2115  
www.ti.com  
SLVS447ADECEMBER 2002REVISED MARCH 2004  
PARAMETER MEASUREMENT INFORMATION  
90%  
10%  
90%  
10%  
V
O(OUT)  
0 V  
t
r
t
f
t
t
PHL1  
PLH1  
DO-D1  
Switch Off  
Switch Off  
Switch Enabled  
(a)  
5 V  
4.8 V  
V
O(OUT)  
3.4 V  
3.3 V  
t
t
DO-D1  
Switch #1 Enabled  
Switch #2 Enabled  
(b)  
5 V  
1.85 V  
4.65 V  
V
O(OUT)  
1.5 V  
t
t
PHL2  
PLH2  
DO-D1  
Switch #1 Enabled  
Switch #2 Enabled  
(c)  
Switch #1 Enabled  
Figure 1. Propagation Delays and Transition Timing Waveforms  
8
TPS2114  
TPS2115  
www.ti.com  
SLVS447ADECEMBER 2002REVISED MARCH 2004  
TYPICAL CHARACTERISTICS  
OUTPUT SWITCHOVER RESPONSE  
V
I(DO)  
5 V  
2V/Div  
TPS2115PW  
0.1 µF  
1
2
8
7
NC  
IN1  
STAT  
D0  
V
I(D1)  
f = 28 Hz  
78% Duty Cycle  
OUT  
IN2  
2V/Div  
3
4
6
5
D1  
50 Ω  
1
µF  
ILIM  
GND  
400 Ω  
3.3 V  
V
O(OUT)  
0.1 µF  
2V/Div  
Output Switchover Response Test Circuit  
t - Time - 1 ms/div  
Figure 2.  
OUTPUT TURNON RESPONSE  
V
I(DO)  
5 V  
2V/Div  
TPS2115PW  
0.1 µF  
1
2
8
7
IN1  
STAT  
D0  
NC  
f = 28 Hz  
78% Duty Cycle  
V
I(D1)  
OUT  
IN2  
3
4
6
5
2V/Div  
D1  
50 Ω  
1
ILIM  
GND  
µF  
400 Ω  
3.3 V  
V
O(OUT)  
2V/Div  
0.1 µF  
Output Turnon Response Test Circuit  
t − Time − 2 ms/div  
Figure 3.  
9
TPS2114  
TPS2115  
www.ti.com  
SLVS447ADECEMBER 2002REVISED MARCH 2004  
TYPICAL CHARACTERISTICS (continued)  
OUTPUT SWITCHOVER VOLTAGE DROOP  
0 µF  
V
I(DO)  
5 V  
2V/Div  
TPS2115PW  
0.1 µF  
1
2
8
7
IN1  
STAT  
D0  
NC  
V
f = 580 Hz  
90% Duty Cycle  
I(D1)  
OUT  
IN2  
3
4
6
5
2V/Div  
D1  
50 Ω  
C
L
ILIM  
GND  
C
L
= 1 µF  
400 Ω  
V
O(OUT)  
2V/Div  
0.1 µF  
C
L
= 0 µF  
Output Switchover Voltage Droop Test Circuit  
t - Time - 40 µs/div  
Figure 4.  
10  
TPS2114  
TPS2115  
www.ti.com  
SLVS447ADECEMBER 2002REVISED MARCH 2004  
TYPICAL CHARACTERISTICS (continued)  
OUTPUT SWITCHOVER VOLTAGE DROOP  
vs  
LOAD CAPACITANCE  
5
V
I
= 5 V  
4.5  
4
3.5  
3
R = 10  
L
2.5  
2
1.5  
1
0.5  
0
R
L
= 50 Ω  
0.1  
1
10  
100  
C
L
- Load Capacitance - µF  
V
I
TPS2115PW  
0.1 µF  
8
7
6
5
1
2
3
4
IN1  
OUT  
IN2  
NC  
D0  
f = 28 Hz  
50% Duty Cycle  
D1  
VSNS  
ILIM  
GND  
400 Ω  
50 Ω  
10 Ω  
0.1 µF  
0.1 µF  
1 µF  
10 µF  
47 µF  
100 µF  
Output Switchover Voltage Droop Test Circuit  
Figure 5.  
11  
TPS2114  
TPS2115  
www.ti.com  
SLVS447ADECEMBER 2002REVISED MARCH 2004  
TYPICAL CHARACTERISTICS (continued)  
INRUSH CURRENT  
vs  
LOAD CAPACITANCE  
300  
250  
200  
150  
100  
50  
V = 5 V  
I
V = 3.3 V  
I
0
0
20  
40  
60  
80  
100  
C
L
- Load Capacitance - µF  
V
I
TPS2115PW  
0.1 µF  
8
7
6
5
To Oscilloscope  
1
2
3
4
NC  
NC  
IN1  
OUT  
IN2  
STAT  
D0  
f = 28 Hz  
90% Duty Cycle  
D1  
50 Ω  
ILIM  
GND  
400 Ω  
0.1 µF  
0.1 µF  
1 µF  
10 µF  
47 µF  
100 µF  
Output Capacitor Inrush Current Test Circuit  
Figure 6.  
12  
TPS2114  
TPS2115  
www.ti.com  
SLVS447ADECEMBER 2002REVISED MARCH 2004  
TYPICAL CHARACTERISTICS (continued)  
SWITCH ON-RESISTANCE  
vs  
JUNCTION TEMPERATURE  
SWITCH ON-RESISTANCE  
vs  
SUPPLY VOLTAGE  
120  
115  
110  
105  
100  
95  
180  
160  
TPS2114  
TPS2114  
140  
120  
TPS2115  
100  
90  
80  
60  
TPS2115  
85  
80  
2
3
4
5
6
−50  
0
50  
100  
150  
T − Junction Temperature − °C  
J
V
I(INx)  
− Supply Voltage − V  
Figure 7.  
Figure 8.  
IN1 SUPPLY CURRENT  
vs  
SUPPLY VOLTAGE  
IN1 SUPPLY CURRENT  
vs  
SUPPLY VOLTAGE  
0.96  
60  
IN1 Switch is ON  
Device Disabled  
V
I(IN2)  
= 0 V,  
58  
56  
54  
52  
V
I(IN2)  
= 0 V  
0.94  
0.92  
I
= 0 A  
O(OUT)  
I
= 0 A  
O(OUT)  
0.90  
0.88  
0.86  
50  
48  
46  
44  
0.84  
0.82  
42  
40  
2
3
4
5
6
2
3
4
5
6
V
I(IN1)  
− Supply Voltage − V  
V − IN1 Supply Voltage − V  
I(IN1)  
Figure 9.  
Figure 10.  
13  
TPS2114  
TPS2115  
www.ti.com  
SLVS447ADECEMBER 2002REVISED MARCH 2004  
TYPICAL CHARACTERISTICS (continued)  
SUPPLY CURRENT  
vs  
JUNCTION TEMPERATURE  
SUPPLY CURRENT  
vs  
JUNCTION TEMPERATURE  
1.2  
80  
70  
60  
50  
IN1 Switch is ON  
Device Disabled  
V
I(IN1)  
V
I(IN2)  
= 5.5 V,  
= 3.3 V  
V
I(IN1)  
= 5.5 V  
1
V
I(IN2)  
= 3.3 V  
I
= 0 A  
O(OUT)  
I
= 0 A  
O(OUT)  
I
I(IN1)  
I
= 5.5 V  
I(IN1)  
0.8  
40  
30  
20  
0.6  
0.4  
0.2  
0
10  
0
I
I(IN2)  
I
3.3 V  
I(IN2) =  
−50  
0
50  
100  
150  
−50  
0
50  
100  
150  
T − Junction Temperature − °C  
J
T − Junction Temperature − °C  
J
Figure 11.  
Figure 12.  
14  
TPS2114  
TPS2115  
www.ti.com  
SLVS447ADECEMBER 2002REVISED MARCH 2004  
APPLICATION INFORMATION  
The circuit in Figure 13 allows one or two battery packs to power a system. Two battery packs allow a longer run  
time. The TPS2114/5 cycles between the battery packs until both packs are drained.  
Switch Status  
IN1: 2.8 - 5.5 V  
TPS2115PW  
R1  
0.1 µF  
1
2
3
4
8
7
6
5
IN1  
OUT  
IN2  
STAT  
D0  
NC  
D1  
R
L
C
L
ILIM  
GND  
R
ILIM  
IN2: 2.8 - 5.5 V  
C2  
0.1 µF  
Figure 13. Running a System From Two Battery Packs  
In Figure 14, the multiplexer selects between two power supplies based upon the D1 logic signal. OUT connects  
to IN1 if D1 is logic 1, otherwise OUT connects to IN2. The logic thresholds for the D1 terminal are compatible  
with both TTL and CMOS logic.  
Switch Status  
IN1: 2.8 - 5.5 V  
TPS2115PW  
R1  
0.1 µF  
1
2
3
4
8
7
6
5
IN1  
OUT  
IN2  
STAT  
D0  
D1  
R
L
C
L
ILIM  
GND  
R
ILIM  
IN2: 2.8 - 5.5 V  
0.1 µF  
Figure 14. Manually Switching Power Sources  
15  
 
TPS2114  
TPS2115  
www.ti.com  
SLVS447ADECEMBER 2002REVISED MARCH 2004  
DETAILED DESCRIPTION  
AUTO-SWITCHING MODE  
D0 equal to logic 1 and D1 equal to logic 0 selects the auto-switching mode. In this mode, OUT connects to the  
higher of IN1 and IN2.  
MANUAL SWITCHING MODE  
D0 equal to logic 0 selects the manual-switching mode. In this mode, OUT connects to IN1 if D1 is equal to logic  
1, otherwise OUT connects to IN2.  
N-CHANNEL MOSFETs  
Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic  
selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so  
output-to-input current cannot flow when the FET is off. An integrated comparator prevents turnon of a FET  
switch if the output voltage is greater than the input voltage.  
CROSS-CONDUCTION BLOCKING  
The switching circuitry ensures that both power switches never conduct at the same time. A comparator monitors  
the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source voltage of  
the other FET is below the turnon threshold voltage.  
REVERSE-CONDUCTION BLOCKING  
When the TPS211x switches from a higher-voltage supply to a lower-voltage supply, current can potentially flow  
back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the TPS211x  
does not connect a supply to the output until the output voltage has fallen to within 100 mV of the supply voltage.  
Once a supply has been connected to the output, it remains connected regardless of output voltage.  
CHARGE PUMP  
The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to the  
current limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages.  
A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET.  
CURRENT LIMITING  
A resistor R(ILIM) from ILIM to GND sets the current limit to 250/ R(ILIM) and 500/R(ILIM) for the TPS2114 and  
TPS2115, respectively. Setting resistor R(ILIM) equal to zero is not recommended as that disables current limiting.  
OUTPUT VOLTAGE SLEW-RATE CONTROL  
The TPS2114/5 slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state  
(see Truth Table). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can  
adversely effect the voltage bus and cause a system to hang up or reset. It can also cause reliability issues—like  
pit the connector power contacts, when hot plugging a load like a PCI card. The TPS2114/5 slews the output  
voltage at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the output  
voltage droop and reduces the output voltage hold-up capacitance requirement.  
16  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
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配单直通车
TPS2114APW产品参数
型号:TPS2114APW
Brand Name:Texas Instruments
是否无铅:不含铅
是否Rohs认证:符合
生命周期:Active
IHS 制造商:TEXAS INSTRUMENTS INC
零件包装代码:SOIC
包装说明:TSSOP-8
针数:8
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
Factory Lead Time:1 week
风险等级:1.09
Samacsys Confidence:3
Samacsys Status:Released
Samacsys PartID:241389
Samacsys Pin Count:8
Samacsys Part Category:Integrated Circuit
Samacsys Package Category:Small Outline Packages
Samacsys Footprint Name:PW0008A
Samacsys Released Date:2016-01-10 13:42:00
Is Samacsys:N
其他特性:CAN SWITCH A VOLTAGE AS LOW AS 1.5V AS LONG AS THERE IS A MIN OF 2.8V AT ONE OF THE I/P POWER PINS
可调阈值:YES
模拟集成电路 - 其他类型:POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码:R-PDSO-G8
JESD-609代码:e4
长度:4.4 mm
湿度敏感等级:1
信道数量:2
功能数量:1
端子数量:8
最高工作温度:85 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP
封装等效代码:TSSOP8,.25
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260
电源:1.8/5 V
认证状态:Not Qualified
座面最大高度:1.2 mm
子类别:Power Management Circuits
最大供电电流 (Isup):0.09 mA
最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.5 V
标称供电电压 (Vsup):2.8 V
表面贴装:YES
温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING
端子节距:0.65 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mm
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