TPS23756PWPR全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

TPS23754

TPS23754-1

TPS23756

www.ti.com ....................................................................................................................................................... SLVS885B–OCTOBER 2008–REVISED MAY 2009

High Power/High Efficiency PoE Interface and DC/DC Controller

1

FEATURES

The TPS23754/6 supports a number of input voltage

2

•

Powers up to 30 W (input) PDs

ORing options including highest voltage, external

adapter preference, and PoE preference. These

features allow the designer to determine which power

source will carry the load under all conditions.

•

DC/DC Control Optimized for Isolated

Converters

•

Supports High-efficiency Topologies

Complete PoE Interface

The PoE interface features the new extended

hardware classification necessary for compatibility

with high-power midspan power sourcing equipment

(PSE) per IEEE 802.3at (draft). The detection

signature pin can also be used to force power from

the PoE source off. Classification can be

programmed to any of the defined types with a single

resistor.

Enhanced Classification per IEEE 802.3at

(Draft) with Status Flag

•

Adapter ORing Support

Programmable Frequency with

Synchronization

•

Robust 100 V, 0.5 Ω Hotswap MOSFET

–40°C to 125°C Junction Temperature Range

Industry Standard PowerPAD™ TSSOP-20

The dc/dc controller features two complementary gate

drivers with programmable dead time. This simplifies

design of active-clamp forward converters or

optimized gate drive for highly-efficient flyback

topologies. The second gate driver may be disabled if

desired for single MOSFET topologies. The controller

also features internal softstart, bootstrap startup

source, current-mode compensation, 78% maximum

duty cycle. A programmable and synchronizable

oscillator allows design optimization for efficiency and

eases use of the controller to upgrade existing power

supply designs. Accurate programmable blanking,

APPLICATIONS

•

IEEE 802.3at (Draft) Compliant Devices

Video and VoIP Telephones

RFID Readers

Multiband Access Points

Security Cameras

DESCRIPTION

with

a

default period, simplifies the usual

current-sense filter design trade-offs.

The TPS23754/6 is a combined Power over Ethernet

(PoE) powered device (PD) interface and

current-mode dc/dc controller optimized specifically

for isolated converters. The PoE interface supports

the IEEE 802.3at (draft) standard.

The TPS23754 has a 15 V converter startup while the

TPS23756 has

a 9 V converter startup. The

TPS23754-1 replaces the PPD pin with a no-connect

for increased pin spacing.

C_IO

T1

V_OUT

C_IN

L_OUT

M4

R_T2P-OUT

T2P

D_VC1

DEN

CLS

R_T2P

V_C

C_OUT

V_T2P-OUT

L_VC

M3

N/C OR PPD

PAD

D_VC2

Type 2 PSE

Indicator

M1

V_B

GATE

CS

V_SS

C_C

V_B

R_CTL

APD

CTL

FRS

R_OB

C_IZ

M2

C_CTL

D_A

GAT2

C_CL

R_APD1

D_CL

TLV431

R_DT

Optional

Interface

Figure 1. High Efficiency Converter Using TPS23754

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS23754

TPS23754-1

TPS23756

SLVS885B–OCTOBER 2008–REVISED MAY 2009....................................................................................................................................................... www.ti.com

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields.

These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to

MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than

maximum-rated voltages to these high-impedance circuits. During storage or handling the device leads should be shorted together

or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate

voltage level, preferably either the proper supply or ground. Specific guidelines for handling devices of this type are contained in

the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas

Instruments.

PRODUCT INFORMATION⁽¹⁾

DUTY

CYCLE

POE UVLO CONVERTER UVLO

STATUS

FEATURE

PACKAGE

MARKING

ON / HYST.

TPS23754PWP

TPS23754PWP-1

TPS23756PWP

Active

0–78%

35/4.5

15 / 6.5

PPD

TSSOP-20

PowerPAD™

TPS23754

Active

35/4.5

15 / 6.5

9 / 3.5

–

TSSOP-20

PowerPAD™

23754-1

PPD

TSSOP-20

TPS23756

PowerPAD™

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS^{(1) (2)}

Voltage with respect to V_SSunless otherwise noted.

VALUE

–0.3 to 100

-0.3 to 6.5

–0.3 to 6.5

–0.3 to V_B

–2 to 2

UNIT

V

Input voltage range, ARTN⁽²⁾, COM⁽²⁾, DEN, PPD, RTN⁽³⁾, V_DD, V_DD1

Input voltage range CLS⁽⁴⁾

V

Input voltage range [APD, BLNK⁽⁴⁾, CTL, DT⁽⁴⁾, FRS⁽⁴⁾, VB⁽⁴⁾] to [ARTN, COM]

Input voltage range CS to [ARTN,COM]

Input voltage range [ARTN, COM] to RTN

Voltage range V_C, T2P, to [ARTN, COM]

Voltage range GATE⁽⁴⁾, GAT2⁽⁴⁾to [ARTN, COM]

Sinking current RTN

V

–0.3 to 19

–0.3 to V_C+0.3

Internally limited

25

V

mA

mArms

kV

V

Sourcing current V_B

Average Sourcing or sinking current, GATE, GAT2

ESD rating, HBM

2

ESD rating, CDM

500

ESD – system level (contact/air) at RJ-45⁽⁵⁾

8 / 15

kV

°C

Operating junction temperature range, T_J

–40 to Internally limited

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) ARTN and COM must be tied to RTN.

(3) I_RTN= 0 for V_RTN> 80V.

(4) Do not apply voltage to these pins

(5) ESD per EN61000-4-2. A power supply containing the TPS23754 was subjected to the highest test levels in the standard. See the ESD

section.

2

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TPS23754

TPS23754-1

TPS23756

www.ti.com ....................................................................................................................................................... SLVS885B–OCTOBER 2008–REVISED MAY 2009

RECOMMENDED OPERATING CONDITIONS⁽¹⁾

Voltage with respect to V_SS(unless otherwise noted)

MIN

0

NOM

MAX UNIT

Input voltage range ARTN, COM, PPD, RTN, V_DD, V_DD1

Input voltage range T2P, V_Cto [ARTN, COM]

Input voltage range APD, CTL, DT to [ARTN, COM]

Input voltage range CS to [ARTN, COM]

Continuous RTN current (T_J≤ 125°C)⁽²⁾

Sourcing current, V_B

57

18

V_B

2

V

0

V

0

V

825

5

mA

µF

kΩ

ns

°C

0

0.08

0

2.5

V_Bcapacitance

R_BLNK

350

125

Synchronization pulse width input (when used)

Operating junction temperature range, T_J

25

–40

(1) ARTN and COM tied to RTN.

(2) This is the minimum current-limit value. Viable systems will be designed for maximum currents below this value with reasonable margin.

IEEE 802.3at (draft) permits 600mA continuous loading

DISSIPATION RATINGS

Ψ_JT

°C/W⁽¹⁾

θ_JP

°C/W

θ_JA

°C/W⁽²⁾

θ_JA

°C/W⁽³⁾

MAXIMUM POWER RATING

(W)⁽⁴⁾

PACKAGE

PWP (TSSOP-20)

0.607

1.4

32.6

73.8

1.2

(1) Thermal resistance junction to case top.

(2) See TI document SLMA002C (or latest version) for recommended layout. This is a best case, natural convection number.

(3) JEDEC method with high-k board (2 signal – 2 plane layers) and power pad not soldered (worst case).

(4) Based on TI recommended layout and 85°C.

ELECTRICAL CHARACTERISTICS

Unless otherwise noted: CS=COM=APD=CTL=RTN=ARTN, GATE & GAT2 float, R_FRS=68.1 kΩ, R_BLNK=249 kΩ, DT=V_B,

PPD=V_SS, T2P open, C_VB=C_VC=0.1 µF, R_DEN=24.9 kΩ, R_CLSopen, 0 V ≤ (V_DD, V_DD1) ≤ 57 V, 0 V ≤ V_C≤ 18 V, –40°C ≤ T_J≤

125°C. Typical specifications are at 25°C.

CONTROLLER SECTION ONLY

[V_SS= RTN and V_DD=V_DD1] or [V_SS=RTN=V_DD], all voltages referred to [ARTN, COM].

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

V_C

V_Crising ‘754

V_Crising ‘756

Hysteresis ‘754

Hysteresis ‘756

14.3

8.7

6.2

3.3

15 15.7

V_CUV

9

6.5

3.5

9.3

6.8

3.7

1.2

UVLO

V

(1)

V_CUVH

Operating current

V_C= 12 V, CTL = V_B, R_DT= 68.1 kΩ

‘756, V_DD1= 10.2 V, V_C(0) = 0 V

‘756, V_DD1= 35 V, V_C(0) = 0 V

‘754, V_DD1= 19.2 V, V_C(0) = 0 V

‘754, V_DD1= 35 V, V_C(0) = 0 V

‘754, V_DD1= 19.2 V, V_C= 13.9 V

‘756, V_DD1= 10.2 V, V_C= 8.6 V

‘754, ‘756, V_DD1= 48 V, V_C= 0 V

0.7 0.92

mA

ms

50

27

85 175

45 92

Bootstrap startup time,

C_VC= 22 µF

t_ST

49

81 166

75 158

44

1.7

3.4

5.5

Startup current source - I_VC

Voltage

0.44 1.06 1.80

2.7 4.8 6.8

mA

V

V_B

6.5 V ≤ V_C≤ 18 V, 0 ≤ I_VB≤ 5 mA

4.8 5.10 5.25

(1) The hysteresis tolerance tracks the rising threshold for a given device.

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TPS23754

TPS23754-1

TPS23756

SLVS885B–OCTOBER 2008–REVISED MAY 2009....................................................................................................................................................... www.ti.com

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

FRS

CTL = V_B, measure GATE

Switching frequency

kHz

R_FRS= 68.1 kΩ

227 253 278

D_MAX

V_SYNC

CTL

Duty cycle

CTL= V_B, measure GATE

Input threshold

76

2

78

80

%

V

Synchronization

2.2

2.4

V_ZDC

0% duty cycle threshold

Softstart period

V

_CTL↓ until GATE stops

1.3

1.9

1.5

3.9

1.7

6.2

V

Interval from switching start to V_CSMAX

ms

kΩ

Input resistance

70 100 145

BLNK

DT

BLNK = RTN

35

38

55

78

70

Blanking delay

(In addition to t₁)

ns

R_BLNK= 49.9 kΩ

CTL = V_B, C_GATE= 1 nF,

C_GAT2= 1 nF, measure GATE, GAT2

t_DT1

t_DT2

t_DT1

t_DT2

CS

R_DT= 24.9 kΩ, GAT2 ↑ to GATE ↑

R_DT= 24.9 kΩ, GATE ↓ to GAT2 ↓

R_DT= 75 kΩ, GAT2 ↑ to GATE ↑

R_DT= 75 kΩ, GATE ↓ to GAT2 ↓

40

50 62.5

Dead time

See Figure 2 for t_DTxdefinition

120 150 188

V_CSMAX

t₁

Maximum threshold voltage

Turnoff delay

V_CTL= V_B, V_CSrising until GATE duty cycle drops

V_CS= 0.65 V

0.5 0.55

24 40

0.6

70

V

ns

Internal slope compensation

voltage

V_SLOPE

I_{SL_EX}

Peak voltage at maximum duty cycle, referenced to CS

120 155 185

mV

Peak slope compensation

current

V_CTL= V_B, I_CSat maximum duty cycle

DC component of I_CS

30

1

42

54

µA

Bias current (sourcing)

2.5

4.3

GATE

GAT2

Source current

Sink current

V_CTL= V_B, V_C= 12 V, GATE high, pulsed measurement

V_CTL= V_B, V_C= 12 V, GATE low, pulsed measurement

0.37

0.7

0.6 0.95

1.0 1.4

A

V_CTL= V_B, V_C= 12 V, GAT2 high, R_DT= 24.9 kΩ, pulsed

measurement

Source current

Sink current

0.37

0.7

0.6 0.95

1.0 1.4

A

V_CTL= V_B, V_C= 12 V, GAT2 low, R_DT= 24.9 kΩ, pulsed

measurement

APD / PPD

V_APDEN

V_APDH

V_APDrising

1.43

1.5 1.57

APD threshold voltage

PPD threshold voltage

V

(2)

Hysteresis

0.29 0.31 0.33

1.45 1.55 1.65

0.29 0.31 0.33

V_PPDEN

V_PPDH

V_PPD- V_VSSrising, UVLO disable

(2)

Hysteresis

V_PPD2

V_PPD- V_VSSrising, Class enable

7.4

0.5

8.3

0.6

9.2

0.7

(2)

V_PPD2H

Hysteresis

APD leakage current

(source or sink)

V_C= 12 V, V_APD= V_B

V_PPD-VSS= 1.5 V

1

µA

I_PPD

PPD sink current

2.5

5

7.5

THERMAL SHUTDOWN

Turnoff temperature

Hysteresis⁽³⁾

(2) The hysteresis tolerance tracks the rising threshold for a given device.

T_Jrising

135 145 155

20

°C

(3) These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product

warranty.

4

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TPS23754

TPS23754-1

TPS23756

www.ti.com ....................................................................................................................................................... SLVS885B–OCTOBER 2008–REVISED MAY 2009

ELECTRICAL CHARACTERISTICS – PoE AND CONTROL

[V_DD=V_DD1] or [V_DD1=RTN], V_C= RTN, COM=RTN=ARTN, all voltages referred to V_SSunless otherwise noted

PARAMETER

DETECTION (DEN)

TEST CONDITIONS

(VDD = VDD1 = RTN = V_SUPPLYpositive)

Measure I_SUPPLY

MIN TYP MAX UNIT

Detection current

V_DD= 1.6 V

62 64.3 66.5

µA

V_DD= 10 V

399 406 414

V_DD= 10 V, float DEN, measure I_SUPPLY

Note: Not during Mark state

,

Detection bias current

5.6

10

µA

V_{PD_DIS}

Hotswap disable threshold

DEN leakage current

3

4

5

V

V_DEN= V_DD= 57 V, float V_DD1and RTN, measure I_DEN

(V_DD= V_DD1= RTN = V_SUPPLYpositive)

13 V ≤ V_DD≤ 21 V, Measure I_SUPPLY

R_CLS= 1270 Ω

0.1

µA

CLASSIFICATION (CLS)

1.8

2.1

2.4

R_CLS= 243 Ω

9.9 10.4 10.9

17.6 18.5 19.4

26.5 27.7 29.3

Classification current,

applies to both cycles

I_CLS

mA

R_CLS= 137 Ω

R_CLS= 90.9 Ω

R_CLS= 63.4 Ω

38.0 39.7

7.5 9.7

42

12

Classification mark resistance

5.6 V ≤ V_DD≤ 9.4 V

kΩ

V_{CL_ON}

V_{CL_H}

Regulator turns on, V_DDrising

Hysteresis⁽¹⁾

11.2 11.9 12.6

1.55 1.65 1.75

Classification regulator lower

threshold

V

V_{CU_OFF}

V_{CU_H}

V_MSR

Regulator turns off, V_DDrising

Hysteresis⁽¹⁾

21

22

23

1.0

5

Classification regulator upper

threshold

V

0.5 0.75

Mark state reset

Leakage current

V_DDfalling

3

4

V

V_DD= 57 V, V_CLS= 0 V, DEN = V_SS, measure I_CLS

(V_DD1= RTN)

1

µA

PASS DEVICE (RTN)

On resistance

Current limit

0.25 0.43 0.75

850 970 1100

100 140 180

11 12.3 13.6

Ω

mA

V

V_RTN= 1.5 V, V_DD= 48 V, pulsed measurement

V_RTN= 2 V, V_DD: 0 V → 48 V, pulsed measurement

V_DDrising

Inrush limit

Foldback voltage threshold

UVLO

V_{UVLO_R}

V_{UVLO_H}

T2P

V_DDrising

Hysteresis⁽¹⁾

33.9

35 36.1

UVLO threshold

V

4.4 4.55 4.76

Perform classification algorithm, V_T2P-RTN= 1 V,

CTL = ARTN

ON characteristic

2

mA

Leakage current

Delay

V_T2P= 18 V, CTL = V_B

10

µA

t_T2P

From start of switching to T2P active

5

9

15

ms

THERMAL SHUTDOWN

Turnoff temperature

Hysteresis⁽²⁾

(1) The hysteresis tolerance tracks the rising threshold for a given device.

T_Jrising

135 145 155

20

°C

(2) These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product

warranty.

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TPS23754

TPS23754-1

TPS23756

SLVS885B–OCTOBER 2008–REVISED MAY 2009....................................................................................................................................................... www.ti.com

hi

50%

lo

hi

50%

time

lo

t_DT1

t_DT2

Figure 2. GATE and GAT2 Timing and Phasing

DEVICE INFORMATION

FUNCTIONAL BLOCK DIAGRAM

V_C

V_B

V_DD1

f

Reg

Ref

Oscillator

FRS

CTL

CONV.

OFF

Control

Global Cvtr.

Enable

4ms

Softstart

50kW

enb

Q

-

GATE

+

D

1

+

CK

DT

COM

0.75V

CLRB

40mA

(pk)

ARTN

3.75kW

GAT2

f

CS

Switch

Matrix

t2

ss

Converter

Thermal

Monitor

+

-

CTL

ARTN

0.55V

T2P

CLS

ARTN

BLNK

ARTN

2.5V

uvlo, fpd

Class

Logic &

Regulator

V_DD

11V &

9V

pa, sa, den

T2

State

Eng.

uvlo

t2

22V &

21.25V

V_SS

DEN

12.5V

& 1V

5V

& 4V

CONV.

OFF

400ms

35V &

30.5V

Q

R

uvlo

1

S

ILIM

7.8V

H

+

-

L

PPD

0

1.55V

&1.25V

EN

pa

Common

Circuits and

PoE Thermal

Monitor

fpd

Hotswap

MOSFET

RTN

APD

V_SS

50mW

sa

den

1.5V

&1.2V

ARTN

4V

6

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TPS23756

www.ti.com ....................................................................................................................................................... SLVS885B–OCTOBER 2008–REVISED MAY 2009

(TOP VIEW)

TPS23754/6

TPS23754-1

20

CTL

V_B

1

2

3

4

5

6

7

8

9

T2P

FRS

BLNK

APD

DT

CTL

V_B

1

2

3

4

5

6

7

8

9

T2P

FRS

BLNK

APD

DT

19

18

17

16

15

14

13

12

11

19

18

17

16

15

14

13

12

11

CS

COM

GATE

V_C

COM

GATE

V_C

CLS

PPD

DEN

V_DD

CLS

N/C

GAT2

ARTN

RTN

V_SS

GAT2

ARTN

RTN

V_SS

DEN

V_DD

V_DD1

10

V_DD1

10

PAD = V_SS

N/C = Leave Pin Unused

PIN FUNCTIONS

NO.

NAME

TYPE

DESCRIPTION

'754/6 ‘754-1

CTL

1

I

The control loop input to the PWM (pulse width modulator), typically driven by output regulation

feedback (e.g. optocoupler). Use V_Bas a pullup for CTL.

V_B

2

O

5.1 V bias rail for dc/dc control circuits and the feedback optocoupler. Typically bypass with a 0.1 µF

to ARTN.

CS

3

4

5

6

3

4

5

6

I/O

DC/DC converter switching MOSFET current sense input. See R_CSin Figure 1.

Gate driver return, connect to ARTN and RTN.

COM

GATE

V_C

O

Gate drive output for the main dc/dc converter switching MOSFET.

I/O

DC/DC converter bias voltage. Connect a 0.47 µF (minimum) ceramic capacitor to ARTN at the pin,

and a larger capacitor to power startup.

GAT2

ARTN

RTN

V_SS

7

8

7

8

O

Gate drive output for a second dc/dc converter switching MOSFET (see Figure 1).

ARTN is the dc/dc converter analog return. Tie to RTN and COM on the circuit board.

RTN is the output of the PoE hotswap MOSFET.

9

10

11

12

10

11

12

Connect to the negative power rail derived from the PoE source.

V_DD1

V_DD

I

Source of dc/dc converter startup current. Connect to V_DDfor many applications.

Connect to the positive PoE input power rail. V_DDpowers the PoE interface circuits. Bypass with a

0.1 µF capacitor and protect with a TVS.

DEN

13

I/O

Connect a 24.9 kΩ resistor from DEN to V_DDto provide the PoE detection signature. Pulling this pin

to V_SSduring powered operation causes the internal hotswap MOSFET to turn off.

NC

–

14

–

Float this no-connect pin.

PPD

14

I

Raising V_PPD-VSSabove 1.55 V enables the hotswap MOSFET and activates T2P. Connecting PPD

to V_DDenables classification when APD is active. Tie PPD to V_SSor float when not used.

CLS

DT

15

16

17

15

16

17

Connect a resistor from CLS to V_SSto program classification current. 2.5 V is applied to the program

resistor during classification to set class current.

Connect a resistor from DT to ARTN to set the GATE to GAT2 dead time. Tie DT to V_Bto disable

GAT2 operation.

APD

Raising V_APD-V_ARTNabove 1.5 V disables the internal hotswap switch, turns class off, and forces T2P

active. This forces power to come from a external V_DD1-RTNadapter. Tie APD to ARTN when not

used.

BLNK

FRS

T2P

18

19

20

–

18

19

20

–

I

Connect to ARTN to utilize the internally set current-sense blanking period, or connect a resistor from

BLNK to ARTN to program a more accurate period.

Connect a resistor from FRS to ARTN to program the converter switching frequency. FRS may be

used to synchronize the converter to an external timing source.

O

Active low output that indicates a PSE has performed the IEEE 802.3at type 2 hardware

classification, PPD is active, or APD is active.

Pad

Connect to V_SS.

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TPS23754-1

TPS23756

SLVS885B–OCTOBER 2008–REVISED MAY 2009....................................................................................................................................................... www.ti.com

PIN DESCRIPTION

Refer to Figure 1 for component reference designators (R_CSfor example), and the Electrical Characteristics table

for values denoted by reference (V_CSMAXfor example). Electrical Characteristic values take precedence over any

numerical values used in the following sections.

APD

APD forces power to come from an external adapter connected from V_DD1to RTN by opening the hotswap

switch, disabling the CLS output (see PPD pin description), and enabling the T2P output. A resistor divider is

recommended on APD when it is connected to an external adapter. The divider provides ESD protection,

leakage discharge for the adapter ORing diode, and input voltage qualification. Voltage qualification assures the

adapter output voltage is high enough that it can support the PD before the PoE current is cut off.

Select the APD divider resistors per Equation 1 where V_ADPTR-ONis the desired adapter voltage that enables the

APD function as adapter voltage rises.

R

= R

´

V

(

- V

V

APDEN

)

APD1

APD2

ADPTR_ON

APDEN

R

+ R

APD1

APD2

V

=

´

V

(

- V

)

ADPTR_OFF

APDEN APDH

R

APD2

(1)

Place the APD pull-down resistor adjacent to the APD pin.

APD should be tied to ARTN when not used.

BLNK

Blanking provides an interval between GATE going high and the current-control comparators on CS actively

monitoring the input. This delay allows the normal turn-on current transient (spike) to subside before the

comparators are active, preventing undesired short duty cycles and premature current limiting.

Connect BLNK to ARTN to obtain the internally set blanking period. Connect a resistor from BLNK to ARTN for a

more accurate, programmable blanking period. The relationship between the desired blanking period and the

programming resistor is defined by Equation 2.

R_BLNKkW = t ns

( ) _BLNK( )

(2)

Place the resistor adjacent to the BLNK pin when it is used.

CLS

A resistor from CLS to V_SSprograms the classification current per the IEEE standard. The PD power ranges and

corresponding resistor values are listed in Table 1. The power assigned should correspond to the maximum

average power drawn by the PD during operation.

High-power PSEs may perform two classification cycles if Class 4 is presented on the first cycle. The TPS23754

presents the same (resistor programmed) class each cycle per the standard.

Table 1. Class Resistor Selection

POWER AT PD

RESISTOR

CLASS

NOTES

MINIMUM

(W)

MAXIMUM

(W)

(Ω)

0

1

2

3

4

0.44

3.84

6.49

12.95

3.84

1270

243

Minimum may be reduced by pulsed loading. Serves as a catch-all default class.

6.49

137

12.95

25.5

90.9

63.4

Not allowed for IEEE 802.3-2005. Use to indicate a Type 2 PD (high power) per

IEEE 802.3at.

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CS

The CS (current sense) input for the dc/dc converter should be connected to the high side of the switching

MOSFET’s current sense resistor (R_CS). The current-limit threshold, V_CSMAX, defines the voltage on CS above

which the GATE ON time will be terminated regardless of the voltage on CTL.

The TPS23754 provides internal slope compensation (150 mV, V_SLOPE), an output current for additional slope

compensation, a peak current limiter, and an off-time pull-down to this pin.

Routing between the current-sense resistor and the CS pin should be short to minimize cross-talk from noisy

traces such as the gate drive signal.

CTL

CTL (control) is the voltage-control loop input to the PWM (pulse width modulator). Pulling V_CTLbelow V_ZDC

causes GATE to stop switching. Increasing V_CTLabove V_ZDC(zero duty cycle voltage) raises the switching

MOSFET programmed peak current. The maximum (peak) current is requested at approximately V_ZDC+ (2 ×

V_CSMAX). The ac gain from CTL to the PWM comparator is 0.5. The internal divider from CTL to ARTN is

approximately 100 kΩ.

Use V_Bas a pull up source for CTL.

DEN

DEN (detection and enable) is a multifunction pin for PoE detection and inhibiting operation from PoE power.

Connect a 24.9 kΩ resistor from DEN to V_DDto provide the PoE detection signature. DEN goes to a

high-impedance state when V_VDD-VSSis outside of the detection range. Pulling DEN to V_SSduring powered

operation causes the internal hotswap MOSFET and class regulator to turn off, while the reduced detection

resistance prevents the PD from properly re-detecting.

DT

Dead-time programming sets the delay between GATE and GAT2 to prevent overlap of MOSFET ON times as

shown in Figure 2. GAT2 turns the second MOSFET off when it transitions high. Both MOSFETs should be off

between GAT2 going high to GATE going high, and GATE going low to GAT2 going low. The maximum GATE

ON time is reduced by the programmed dead-time period. The dead time period is specified with 1 nF of

capacitance on GATE and GAT2. Different loading on these pins will change the effective dead time.

A resistor connected from DT to ARTN sets the delay between GATE and GAT2 per Equation 3.

t

ns

_DT( )

R

kW

_DT( )

=

2

(3)

Connect DT to V_Bto set the dead time to 0 and turn GAT2 off.

FRS

Connect a resistor from FRS (frequency and synchronization) to ARTN to program the converter switching

frequency. Select the resistor per the following relationship.

17250

R_FRS(kW) =

f_SW(kHz)

(4)

The converter may be synchronized to a frequency above its maximum free-running frequency by applying short

ac-coupled pulses into the FRS pin per Figure 30.

The FRS pin is high impedance. Keep the connections short and apart from potential noise sources. Special care

should be taken to avoid crosstalk when synchronizing circuits are used.

GATE

Gate drive output for the dc/dc converter’s main switching MOSFET. GATE’s phase turns the main switch on

when it transitions high, and off when it transitions low. GATE is held low when the converter is disabled.

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GAT2

GAT2 is the second gate drive output for the dc/dc converter. GAT2’s phase turns the second switch off when it

transitions high, and on when it transitions low. This drives active-clamp PMOS devices per Figure 1, and driven

flyback synchronous rectifiers per Figure 28. See the DT Pin Description for GATE to GAT2 timing. Connecting

DT to V_Bdisables GAT2 in a high-impedance condition. GAT2 is low when the converter is disabled.

PPD

PPD is a multifunction pin that has two voltage thresholds, PPD1 and PPD2.

PPD1 permits power to come from an external low voltage adapter, e.g., 24 V, connected from V_DDto V_SSby

over-riding the normal hotswap UVLO. Voltage on PPD above 1.55 V (V_PPDEN) enables the hotswap MOSFET,

inhibits class current, and enables T2P. A resistor divider per Figure 35 provides ESD protection, leakage

discharge for the adapter ORing diode, reverse adapter protection, and input voltage qualification. Voltage

qualification assures the adapter output voltage is high enough that it can support the PD before it begins to draw

current.

æ

ç

è

ö

÷

ø

V_{ADPTR_ON}- V_PPDEN

R_PPD1

=

V_PPDEN

- I_PPD

R_PPD2

é

ù

ö

æ

V

(

- V_PPDH

)

PPDEN

V_{ADPTR_OFF}

=

V

(

- V_PPDH+êR

´ ç

- I_PPD÷ú

)

PPDEN

PPD1

ç

è

÷

ú

R_PPD2

ê

ë

ø

û

(5)

PPD2 enables normal class regulator operation when V_PPDis above 8.3 V to permit type 2 classification when

APD is used in conjunction with diode D_VDD(see Figure 34). Tie PPD to V_DDwhen PPD2 operation is desired.

The PPD pin has a 5 µA internal pull-down current.

Locate the PPD pull-down resistor adjacent to the pin when used.

PPD may be tied to V_SSor left open when not used.

RTN, ARTN, COM

RTN is internally connected to the drain of the PoE hotswap MOSFET, while ARTN is the quiet analog reference

for the dc/dc controller return. COM serves as the return path for the gate drivers and should be tied to ARTN on

the circuit board. The ARTN / COM / RTN net should be treated as a local reference plane (ground plane) for the

dc/dc control and converter primary. RTN and (ARTN/COM) may be separated by several volts for special

applications.

T2P

T2P is an active low output that indicates [ (V_APD> 1.5 V) OR (1.55 V ≤ V_PPD≤ 8.3 V) OR (type 2 hardware

classification observed) ]. T2P is valid after both a delay of t_T2Pfrom the start of converter switching, and [V_CTL

≤

(V_B– 1 V)]. Once T2P is valid, V_CTLwill not effect it. T2P will become invalid if the converter goes back into

softstart, over-temperature, or is held off by the PD during C_INrecharge (inrush). T2P is referenced to ARTN and

is intended to drive the diode side of an optocoupler. T2P should be left open or tied to ARTN if not used.

V_B

V_Bis an internal 5.1V regulated dc/dc controller supply rail that is typically bypassed by a 0.1 µF capacitor to

ARTN. V_Bshould be used to bias the feedback optocoupler.

V_C

V_Cis the bias supply for the dc/dc controller. The MOSFET gate drivers run directly from V_C. V_Bis regulated

down from V_C, and is the bias voltage for the rest of the converter control. A startup current source from V_DD1to

V_Cis controlled by a comparator with hysteresis to implement the converter bootstrap startup. V_Cmust be

connected to a bias source, such as a converter auxiliary output, during normal operation.

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A minimum 0.47 µF capacitor, located adjacent to the V_Cpin, should be connected from V_Cto COM to bypass

the gate driver. A larger total capacitance is required for startup to provide control power between the time the

converter starts switching and the availability of the converter auxiliary output voltage.

V_DD

V_DDis the positive input power rail that is derived from the PoE source (PSE). V_DDshould be bypassed to V_SS

with a 0.1 µF capacitor as required by the IEEE standard. A transient suppressor diode (TVS), a special type of

Zener diode, such as SMAJ58A should be connected from V_DDto V_SSto protect against over-voltage transients.

V_DD1

V_DD1is the dc/dc converter startup supply. Connect to V_DDfor many applications. V_DD1may be isolated by a

diode from V_DDto support PoE priority operation.

V_SS

V_SSis the PoE input-power return side. It is the reference for the PoE interface circuits, and has a current-limited

hotswap switch that connects it to RTN. V_SSis clamped to a diode drop above RTN by the hotswap switch.

A local V_SSreference plane should be used to connect the input bypass capacitor, TVS, R_CLS, and the

PowerPad. This plane becomes the main heatsink for the TPS23754.

V_SSis internally connected to the PowerPAD.

PowerPAD

The Powerpad is internally connected to V_SS. It should be tied to a large V_SScopper area on the PCB to provide

a low resistance thermal path to the circuit board. It is recommended that a clearance of 0.025” be maintained

between V_SS, RTN, and various control signals to high-voltage signals such as V_DDand V_DD1

.

TYPICAL CHARACTERISTICS

DETECTION BIAS CURRENT

PoE CURRENT LIMIT

vs

VOLTAGE

TEMPERATURE

970

960

950

940

930

920

910

8

7

6

5

4

3

2

1

0

Pulsed Current Measurement

25°C

125°C

−40°C

0

2

4

6

8

10

−40 −20

0

20

40

60

80 100 120

(V

VDD

− V ) − PoE Voltage − V

VSS

T − Junction Temperature − °C

J

G001

G002

Figure 3.

Figure 4.

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TYPICAL CHARACTERISTICS (continued)

'754 CONVERTER START TIME

'756 CONVERTER START TIME

vs

TEMPERATURE

160

140

120

100

80

160

140

120

100

80

V

= 10.2 V

C

VC

= 22 µF

VDD1

C

= 22 mF

VC

V

VDD1

= 19.2 V

V

VDD1

= 35 V

60

40

20

V

= 35 V

VDD1

20

−40 −20

0

20

40

60

80 100 120

−40 −20

0

20

40

60

80 100 120

T

- Junction Temperature - ^oC

T − Junction Temperature − °C

J

G003

Figure 5.

Figure 6.

'754 CONVERTER STARTUP CURRENT

'756 CONVERTER STARTUP CURRENT

vs

V_VDD1

6

5

6

5

V

= 13.9V

V

= 8.6V

VC

= -40^oC

= 25^oC

T

= -40^oC

= 25^oC

T

J

T

J

4

3

2

4

3

2

= 125^oC

T

= 125^oC

T

J

1

0

1

0

5

10 15 20 25 30 35 40 45 50 55 60

− V

5

10 15 20 25 30 35 40 45 50 55 60

− V

V

VDD1-RTN

Figure 7.

Figure 8.

12

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TYPICAL CHARACTERISTICS (continued)

CONTROLLER BIAS CURRENT

'754 CONTROLLER BIAS CURRENT

vs

TEMPERATURE

VOLTAGE

3000

2500

2000

1500

1000

500

3500

3000

2500

2000

1500

1000

500

GATE and GAT2 Open

= 12 V

GATE and GAT2 Open

V

VC

T = 25°C

J

937 kHz

484 kHz

937 kHz

245 kHz

484 kHz

100 kHz

245 kHz

100 kHz

V = 0 V

CTL

50 kHz

40

V

= 0 V

CTL

0

−40 −20

0

20

60

80 100 120

9

10 11

12 13

14 15

16 17 18

T - Junction Temperature - °C

J

V

C

− Controller Bias Voltage − V

G005

G006

Figure 9.

Figure 10.

'756 CONTROLLER BIAS CURRENT

SWITCHING FREQUENCY

vs

VOLTAGE

TEMPERATURE

1200

1100

1000

900

600

500

400

300

200

100

0

4000

3500

3000

2500

2000

1500

1000

500

GATE, GAT2 open

= 25^oC

T

R

= 34.6 kΩ (484 kHz)

FRS

J

960 kHz

R

FRS

= 17.35 kΩ (937 kHz)

= 69.8 kΩ (245 kHz)

480 kHz

R

FRS

R

FRS

= 347 kΩ (50 kHz)

800

100 kHz

R

FRS

= 173 kΩ (100 kHz)

50 kHz

250 kHz

700

600

−40 −20

0

20

40

60

80 100 120

V

= 0 V

14

CTL

0

T

J

- Junction Temperature - °C

G007

6

8

10

12

16

18

V

− Controller Bias Voltage − V

C

Figure 11.

Figure 12.

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TYPICAL CHARACTERISTICS (continued)

SWITCHING FREQUENCY

vs

PROGRAM CONDUCTANCE

MAXIMUM DUTY CYCLE

vs

TEMPERATURE

79

78

77

76

75

74

73

72

71

70

1200

1000

800

600

400

200

0

R

= 347 kW (50 kHz)

FRS

Ideal

R

= 69.8 kW (245 kHz)

FRS

R

= 34.6 kW (484 kHz)

FRS

Typical

= 26.7 kW (623 kHz)

FRS

R

= 21.5 kW (766 kHz)

= 17.3 kW (937 kHz)

FRS

R

FRS

−40 −20

0

20

40

60

80 100 120

0

10

20

30

40

50

60

6

−1

T - Junction Temperature - °C

J

Programmed Resistance (10 / R

) − Ω

FRS

G009

G008

Figure 13.

Figure 14.

CURRENT SLOPE COMPENSATION VOLTAGE

CURRENT SLOPE COMPENSATION CURRENT

vs

TEMPERATURE

50

45

40

35

30

155

154

153

152

151

150

149

−40 −20

0

20

40

60

80 100 120

−40 −20

0

20

40

60

80 100 120

T − Junction Temperature − °C

J

T − Junction Temperature − °C

J

G011

G010

Figure 15.

Figure 16.

14

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TYPICAL CHARACTERISTICS (continued)

BLANKING PERIOD

vs

TEMPERATURE

BLANKING PERIOD

vs

Blanking Resistance (R_BLNK)

265

450

18

115

105

95

400

350

300

250

14

10

6

260

255

250

245

240

235

230

R

= 100 kΩ

BLNK

85

2

R

= 249 kΩ

BLNK

200

150

100

50

−2

75

−6

65

R

BLNK

= RTN

R

BLNK

= 49.9 kΩ

−10

−14

−18

55

45

0

−40 −20

0

20

40

60

80 100 120

0

50

100 150 200 250 300 350 400

T

J

- Junction Temperature - °C

R

BLNK

− kΩ

G012

G013

Figure 17.

Figure 18.

DEAD TIME

vs

DEAD TIME RESISTANCE (R_DT

T2P DELAY TIME

vs

TEMPERATURE

)

900

11

10

9

800

700

600

Ideal

500

400

300

200

100

8

Typical

7

6

0

50

100 150 200 250 300 350 400

-40 -20

0

20

40

60

80

100 120

Temperature - °C

Dead Time Resistance - kW

Figure 19.

Figure 20.

DETAILED DESCRIPTION

PoE OVERVIEW

The following text is intended as an aid in understanding the operation of the TPS23754 but not as a substitute

for the actual IEEE 802.3-2005 or IEEE 802.3at standard. The pending IEEE 802.3at standard is an update to

IEEE 802.3-2005 clause 33 (PoE), adding high-power options and enhanced classification. Generally speaking, a

device compliant to IEEE 802.3-2005 will be referred to as a type 1 device, and devices with high power and

enhanced classification will be referred to as type 2 devices. Standards change and should always be referenced

when making design decisions.

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The IEEE 802.3-2005 (802.3at) standard defines a method of safely powering a PD (powered device) over a

cable by power sourcing equipment (PSE), and then removing power if a PD is disconnected. The process

proceeds through an idle state and three operational states of detection, classification, and operation. The PSE

leaves the cable unpowered (idle state) while it periodically looks to see if something has been plugged in; this is

referred to as detection. The low power levels used during detection are unlikely to damage devices not designed

for PoE. If a valid PD signature is present, the PSE my inquire how much power the PD requires; this is referred

to as classification. The PSE may then power the PD if it has adequate capacity.

Type 2 PSEs are required to do type 1 hardware classification plus a (new) data-layer classification, or an

enhanced type 2 hardware classification. Type 1 PSEs are not required to do hardware or data link layer (DLL)

classification. A type 2 PD must do type 2 hardware classification as well as DLL classification. The PD may

return the default 12.95W (often referred to as 13W) current-encoded class, or one of four other choices. DLL

classification occurs after power-on and the ethernet data link has been established.

Once started, the PD must present the maintain power signature (MPS) to assure the PSE that it is still present.

The PSE monitors its output for a valid MPS, and turns the port off if it loses the MPS. Loss of the MPS returns

the PSE to the idle state. Figure 21 shows the operational states as a function of PD input voltage. The upper

half is for IEEE 802.3-2005, and the lower half shows specific differences for IEEE 802.3at. The dashed lines in

the lower half indicate these are the same (e.g., Detect and Class) for both.

Shut-

down

Classify

Normal Operation

Detect

42.5

6.9

0

2.7

10.1 14.5

Mark

20.5

30

57

PI Voltage (V)

37

42

Normal Operation

Figure 21. Operational States for PD

The PD input, typically an RJ-45 eight-lead connector, is referred to as the power interface (PI). PD input

requirements differ from PSE output requirements to account for voltage drops and operating margin. The

standard allots the maximum loss to the cable regardless of the actual installation to simplify implementation.

IEEE 802.3-2005 was designed to run over infrastructure including ISO/IEC 11801 class C (CAT3 per

TIA/EIA-568) that may have had AWG 26 conductors. IEEE 802.3at cabling power loss allotments and voltage

drops have been adjusted for 12.5 Ω power loops per ISO/IEC11801 class D (CAT5 or higher per TIA/EIA-568,

typically AWG #24 conductors). Table 2 shows key operational limits broken out for the two revisions of the

standard.

Table 2. Comparison of Operational Limits

POWER LOOP

RESISTANCE

PSE

OUTPUT POWER

(min)

PSE STATIC

OUTPUT VOLTAGE

(min)

PD INPUT

POWER

(max)

STATIC PD INPUT VOLTAGE

STANDARD

POWER ≤

POWER >

12.95 W

(max)

12.95 W

'2005

20 Ω

15.4 W

36 W

44 V

50 V

12.95 W

25.5 W

37 V–57 V

N/A

802.3at

12.5 Ω

42.5 V–57 V

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The PSE can apply voltage either between the RX and TX pairs (pins 1 - 2 and 3 - 6 for 10baseT or 100baseT),

or between the two spare pairs (4 - 5 and 7 - 8). Power application to the same pin combinations in 1000baseT

systems is recognized in 802.3at. 1000baseT systems can handle data on all pairs, eliminating the spare pair

terminology. The PSE may only apply voltage to one set of pairs at a time. The PD uses input diode bridges to

accept power from any of the possible PSE configurations. The voltage drops associated with the input bridges

create a difference between the standard limits at the PI and the TPS23754 specifications.

A compliant type 2 PD has power management requirements not present with a type 1 PD. These requirements

include the following:

1. Must interpret type 2 hardware classification

2. Must present hardware class 4

3. Must implement DLL negotiation

4. Must behave like a type 1 PD during inrush and startup

5. Must not draw more than 13W for 80ms after PSE applies operating voltage (power-up)

6. Must not draw more than 13W if it has not received a type 2 hardware classification or received permission

through DLL

7. Must meet various operating and transient templates

8. Optionally monitor for the presence or absence of an adapter (assume high power).

As a result of these requirements, the PD must be able to dynamically control its loading, and monitor T2P for

changes. In cases where the design needs to know specifically if an adapter is plugged in and operational, the

adapter should be individually monitored, typically with an optocoupler.

Threshold Voltages

The TPS23754 has a number of internal comparators with hysteresis for stable switching between the various

states. Figure 22 relates the parameters in the Electrical Characteristics section to the PoE states. The mode

labeled idle between classification and operation implies that the DEN, CLS, and RTN pins are all high

impedance. The state labeled Mark, which is drawn in dashed lines, is part of the new type 2 hardware class

state machine.

PD Powered

Idle

Classification

Mark

Detection

V_DD-V_SS

V_{CU_H}

V_{CU_OFF}

V_{CL_H}

V_{CL_ON}

V_{UVLO_H}

V_MSR

V_{UVLO_R}

Note: Variable names refer to Electrical Characteristic

Table parameters

Figure 22. Threshold Voltages

PoE Startup Sequence

The waveforms of Figure 23 demonstrate detection, classification, and startup from a PSE with type 2 hardware

classification. The key waveforms shown are V_VDD-V_VSS, V_RTN-V_VSS, and I_PI. IEEE 802.3at requires a minimum of

two detection levels, two class and mark cycles, and startup from the second mark event. V_RTNto V_SSfalls as the

TPS23754 charges C_INfollowing application of full voltage. Subsequently, the converter starts up, drawing

current as seen in the I_PIwaveform.

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Cvtr. Starts

Inrush

I

PI

Class

V

VDD-VSS

Mark

Detect

V

RTN-VSS

t - Time - 25 ms/div

Figure 23. Startup

Detection

The TPS23754 drives DEN to V_SSwhenever V_VDD-V_VSSis below the lower classification threshold. When the

input voltage rises above V_CL-ON, the DEN pin goes to an open-drain condition to conserve power. While in

detection, RTN is high impedance, and almost all the internal circuits are disabled. An R_DENof 24.9 kΩ (1%),

presents the correct signature. It may be a small, low-power resistor since it only sees a stress of about 5 mW. A

valid PD detection signature is an incremental resistance ( ΔV / ΔI ) between 23.75 kΩ and 26.25 kΩ at the PI.

The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with the

parallel combination of R_DENand internal V_DDloading. The input diode bridge’s incremental resistance may be

hundreds of ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge resistance is

partially cancelled by the TPS23754's effective resistance during detection.

The type 2 hardware classification protocol of IEEE 802.3at specifies that a type 2 PSE drops its output voltage

into the detection range during the classification sequence. The PD is required to have an incorrect detection

signature in this condition, which is referred to as the mark event (see Figure 23). After the first mark event, the

TPS23754 will present a signature less than 12 kΩ until it has experienced a V_VDD-V_VSSvoltage below the mark

reset (V_MSR). This is explained more fully under Hardware Classification.

Hardware Classification

Hardware classification allows a PSE to determine a PD’s power requirements before powering, and helps with

power management once power is applied. Type 2 hardware classification permits high power PSEs and PDs to

determine whether the connected device can support high-power operation. A type 2 PD presents class 4 in

hardware to indicate it is a high-power device. A type 1 PSE will treat a class 4 device like a class 0 device,

allotting 12.95 W if it chooses to power the PD. A PD that receives a 2 event class understands that it is powered

from a high-power PSE and it may draw up to 25.5 W immediately after the 80 ms startup period completes. A

type 2 PD that does not receive a 2-event hardware classification may choose to not start, or must start in a 13

W condition and request more power through the DLL after startup. The standard requires a type 2 PD to

indicate that it is underpowered if this occurs. Startup of a high-power PD under 13 W implicitly requires some

form of powering down sections of the application circuits.

The maximum power entries in Table 1 determine the class the PD must advertise. The PSE may disconnect a

PD if it draws more than its stated Class power, which may be the hardware class or a lower DLL-derived power

level. The standard permits the PD to draw limited current peaks that increase the instantaneous power above

the Table 1 limit, however the average power requirement always applies.

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The TPS23754 implements two-event classification. Selecting an R_CLSof 63.4 Ω provides a valid type 2

signature. TPS23754 may be used as a compatible type 1 device simply by programming class 0–3 per Table 1.

DLL communication is implemented by the ethernet communication system in the PD and is not implemented by

the TPS23754.

The TPS23754 disables classification above V_{CU_OFF}to avoid excessive power dissipation. CLS voltage is turned

off during PD thermal limit or when APD or DEN are active. The CLS output is inherently current limited, but

should not be shorted to V_SSfor long periods of time.

Figure 24 shows how classification works for the TPS23754. Transition from state-to-state occurs when

comparator thresholds are crossed (see Figure 21 and Figure 22). These comparators have hysteresis, which

adds inherent memory to the machine. Operation begins at idle (unpowered by PSE) and proceeds with

increasing voltage from left to right. A 2-event classification follows the (heavy lined) path towards the bottom,

ending up with a latched type 2 decode along the lower branch that is highlighted. This state results in a low T2P

during normal operation. Once the valid path to type 2 PSE detection is broken, the input voltage must transition

below the mark reset threshold to start anew.

Mark

Reset

UVLO

Falling

Mark

Class

Operating

T2P

open-drain

Between

Ranges

UVLO

Rising

Idle

Detect

TYPE 1 PSE

Hardware Class

Mark

Reset

Between

Ranges

Mark

Between

Ranges

UVLO

Rising

Operating

T2P low

TYPE 2 PSE

Hardware Class

UVLO

Falling

Figure 24. Two-Event Class Internal States

Inrush and Startup

802.3at has a startup current and time limitation, providing type 2 PSE compatibility for type 1 PDs. A type 2 PSE

limits output current to between 400 mA and 450 mA for up to 75 ms after power-up (applying “48 V” to the PI) in

order to mirror type 1 PSE functionality. The type 2 PSE will support higher output current after 75 ms. The

TPS23754 implements a 140 mA inrush current, which is compatible with all PSE types. A high-power PD must

control its converter startup peak and operational currents drawn to below 400 mA for 80 ms. The TPS23754’s

internal softstart permits control of the converter startup, however the application circuits must assure that their

power draw does not cause the PD to exceed the current/time limitation. This requirement implicitly requires

some form of powering down sections of the application circuits. T2P becomes valid within t_T2Pafter switching

starts, or if an adapter is plugged in while the PD is operating from a PSE.

Maintain Power Signature

The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating

voltage is applied. A valid MPS consists of a minimum dc current of 10 mA (or a 10 mA pulsed current for at

least 75 ms every 225 ms) and an ac impedance lower than 26.25 kΩ in parallel with 0.05 µF. The ac impedance

is usually accomplished by the minimum operating C_INrequirement of 5 µF. When either APD or DEN is used to

force the hotswap switch off, the dc MPS will not be met. A PSE that monitors the dc MPS will remove power

from the PD when this occurs. A PSE that monitors only the ac MPS may remove power from the PD.

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Startup and Converter Operation

The internal PoE UVLO (Under Voltage Lock Out) circuit holds the hotswap switch off before the PSE provides

full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and

classification. The converter circuits will discharge C_IN, C_VC, and C_VBwhile the PD is unpowered. Thus V_VDD-V_RTN

will be a small voltage just after full voltage is applied to the PD, as seen in Figure 23. The PSE drives the PI

voltage to the operating range once it has decided to power up the PD. When V_VDDrises above the UVLO

turn-on threshold (V_UVLO-R, ~35 V) with RTN high, the TPS23754 enables the hotswap MOSFET with a ~140 mA

(inrush) current limit as seen in Figure 25. Converter switching is disabled while C_INcharges and V_RTNfalls from

V_VDDto nearly V_VSS, however the converter startup circuit is allowed to charge C_VC(the bootstrap startup

capacitor). Converter switching is allowed if the PD is not in inrush, OTSD is not active, and the V_CUVLO

permits it. Once the inrush current falls about 10% below the inrush current limit, the PD current limit switches to

the operational level (~970 mA). Continuing the startup sequence shown in Figure 25, V_VCcontinues to rise until

the startup threshold (V_CUV, ~15 V or ~9 V) is exceeded, turning the startup source off and enabling switching.

The V_Bregulator is always active, powering the internal converter circuits as V_VCrises. There is a slight delay

between the removal of charge current and the start of switching as the softstart ramp sweeps above the V_ZDC

threshold. V_VCfalls as it powers both the internal circuits and the switching MOSFET gates. If the converter

control bias output rises to support V_VCbefore it falls to V_CUV– V_CUVH(~8.5 V or ~5.5 V), a successful startup

occurs. T2P in Figure 23 (Figure 1, V_T2P-OUT) becomes active within t_T2Pfrom the start of switching, indicating

that a type 2 PSE or an adapter is plugged in.

10

5 V/div

9

T2P @ output

9

Inrush

8

200 mA/div

I

PI

7

PI Powered

6

V

-RTN

C

10 V/div

5

Switching starts

4

2 V/div

3

V

OUT

2

1

50 V/div

V

-RTN

DD

0

t - Time - 10 ms/div

Figure 25. Power Up and Start

If V_VDD- V_VSSdrops below the lower PoE UVLO (V_UVLO-R- V_UVLO-H, ~30.5 V), the hotswap MOSFET is turned off,

but the converter will still run. The converter will stop if V_VCfalls below the converter UVLO (V_CUV– V_CUVH, ~8.5 V

or ~5.5 V), the hotswap is in inrush current limit, 0% duty cycle is demanded by V_CTL(V_CTL< V_ZDC, ~1.5 V), or

the converter is in thermal shutdown.

PD Hotswap Operation

IEEE 802.3at has taken a new approach to PSE output limiting. A type 2 PSE must meet an output current vs.

time template with specified minimum and maximum sourcing boundaries. The peak output current may be as

high as 50 A for 10 µs or 1.75 A for 75 ms. This makes robust protection of the PD device even more important

than it was in IEEE 802.3-2005.

The internal hotswap MOSFET is protected against output faults and input voltage steps with a current limit and

deglitched (time-delay filtered) foldback. An overload on the pass MOSFET engages the current limit, with

V_RTN-V_VSSrising as a result. If V_RTNrises above ~12 V for longer than ~400 µs, the current limit reverts to the

inrush value, and turns the converter off. The 400 µs deglitch feature prevents momentary transients from

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causing a PD reset, provided that recovery lies within the bounds of the hotswap and PSE protection. Figure 26

shows an example of recovery from a 16 V PSE rising voltage step. The hotswap MOSFET goes into current

limit, overshooting to a relatively low current, recovers to ~950 mA full current limit, and charges the input

capacitor while the converter continues to run. The MOSFET did not go into foldback because V_RTN-V_VSSwas

below 12 V after the 400 µs deglitch.

I

PI

C

completes charge

IN

while converter operates

V

RTN-VSS

V

< 12 V @ 400 ms

16 V Input step

RTN

V

VDD-VSS

Recovery from PI dropout

t - Time - 200 ms/div

Figure 26. Response to PSE Step Voltage

The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like startup or

operation into a V_DDto RTN short cause high power dissipation in the MOSFET. An over-temperature shutdown

(OTSD) turns off the hotswap MOSFET and class regulator, which are restarted after the device cools. The

hotswap MOSFET will be re-enabled with the inrush current limit when exiting from an over-temperature event.

Pulling DEN to V_SSduring powered operation causes the internal hotswap MOSFET to turn off. This feature

allows a PD with Option three ORing per Figure 27 to achieve adapter priority. Care must be taken with

synchronous converter topologies that can deliver power in both directions.

The hotswap switch will be forced off under the following conditions:

1. V_APDabove V_APDEN(~1.5 V)

2. V_DEN< V_PD-DISwhen V_VDD– V_VSSis in the operational range

3. PD over-temperature

4. (V_VDD– V_VSS) < PoE UVLO (~30.5 V).

Converter Controller Features

The TPS23754 dc/dc controller implements a typical current-mode control as shown in the Functional Block

Diagram. Features include oscillator, over-current and PWM comparators, current-sense blanker, dead-time

control, softstart, and gate driver. In addition, an internal slope-compensation ramp generator, frequency

synchronization logic, thermal shutdown, and startup current source with control are provided.

The TPS23754 is optimized for isolated converters, and does not provide an internal error amplifier. Instead, the

optocoupler feedback is directly fed to the CTL pin which serves as a current-demand control for the PWM.

There is an offset of V_ZDC(~1.5 V) and 2:1 resistor divider between the CTL pin and the PWM. A V_CTLbelow

V_ZDCwill stop converter switching, while voltages above (V_ZDC+ (2 × V_CSMAX)) will not increase the requested

peak current in the switching MOSFET. Optocoupler biasing design is eased by this limited control range.

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Bootstrap Topology

The internal startup current source and control logic implement a bootstrap-type startup as discussed in “Startup

and Converter Operation.” The startup current source charges C_VCfrom V_DD1when the converter is disabled

(either by the PD control or the V_Ccontrol) to store enough energy to start the converter. Steady-state operating

power must come from a converter (bias winding) output or other source. Loading on V_Cand V_Bmust be minimal

while C_VCcharges, otherwise the converter may never start. The optocoupler will not load V_Bwhen the converter

is off for most situations, however care should be taken in ORing topologies where the output is powered when

PoE is off.

The converter will shut off when V_Cfalls below its lower UVLO. This can happen when power is removed from

the PD, or during a fault on a converter output rail. When one output is shorted, all the output voltages fall

including the one that powers V_C. The control circuit discharges V_Cuntil it hits the lower UVLO and turns off. A

restart will initiate as described in Startup and Converter Operation if the converter turns off and there is sufficient

V_DD1voltage. This type of operation is sometimes referred to as hiccup mode which provides robust output short

protection by providing time-average heating reduction of the output rectifier.

The bootstrap control logic disables most of the converter controller circuits except the V_Bregulator and internal

reference. Both GATE and GAT2 (assuming GAT2 is enabled) will be low when the converter is disabled. FRS,

BLNK, and DT will be at ARTN while the V_CUVLO disables the converter. While the converter runs, FRS, BLNK,

and DT will be about 1.25 V.

The startup current source transitions to a resistance as (V_VDD1– V_VC) falls below 7 V, but will start the converter

from adapters within t_ST. The lower test voltage for t_STwas chosen based on an assumed adapter tolerance, but

is not meant to imply a hard cutoff exists. Startup takes longer and eventually will not occur as V_DD1decreases

below the test voltage. The bootstrap source provides reliable startup from widely varying input voltages, and

eliminates the continual power loss of external resistors. The startup current source will not charge above the

maximum recommended V_VCif the converter is disabled and there is sufficient V_DD1to charge higher.

Current Slope Compensation and Current Limit

Current-mode control requires addition of a compensation ramp to the sensed inductive (transformer or inductor)

current for stability at duty cycles near and over 50%. The TPS23754 has a maximum duty cycle limit of 78%,

permitting the design of wide input-range flyback and active clamp converters with a lower voltage stress on the

output rectifiers. While the maximum duty cycle is 78%, converters may be designed that run at duty cycles well

below this for a narrower, 36 V to 57 V PI range. The TPS23754 provides a fixed internal compensation ramp

that suffices for most applications.

The TPS23754 provides internal, frequency independent, slope compensation (150 mV, V_SLOPE) to the PWM

comparator input for current-mode control-loop stability. This voltage is not applied to the current-limit comparator

whose threshold is 0.55 V (V_CSMAX). If the provided slope is not sufficient, the effective slope may be increased

by addition of R_Sper Figure 31. The additional slope voltage is provided by (I_SL-EX× R_S). There is also a small dc

offset caused by the ~2.5 µA pin current. The peak current limit does not have duty cycle dependency unless R_S

is used. This makes it easier to design the current limit to a fixed value. See Current Slope Compensation for

more information.

The internal comparators monitoring CS are isolated from the IC pin by the blanking circuits while GATE is low,

and for a short time (blanking period) just after GATE switches high. A 440 Ω (max) equivalent pull down on CS

is applied while GATE is low.

Blanking - R_BLNK

The TPS23754 provides a choice between internal fixed and programmable blanking periods. The blanking

period is specified as an increase in the minimum GATE on time over the inherent gate driver and comparator

delays. The default period (see the Electrical Characteristics table) is selected by connecting BLNK to RTN, and

the programmable period is set with R_BLNK

.

The TPS23754 blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This

avoids current-sense waveform distortion, which tends to get worse at light output loads. There may be some

situations or designers that prefer an R-C approach. The TPS23754 provides a pull-down on CS during the

GATE off time to improve sensing when an R-C filter must be used. The CS input signal should be protected

from nearby noisy signals like GATE drive and the switching MOSFET drain.

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Dead Time

The TPS23754 features two switching MOSFET gate drivers to ease implementation of high-efficiency

topologies. Specifically, these include active (primary) clamp topologies and those with synchronous drivers that

are hard-driven by the control circuit. In all cases, there is a need to assure that both driven MOSFETs are not

on at the same time. The DT pin programs a fixed time period delay between the turn-off of one gate driver until

the turn-on of the next. This feature is an improvement over the repeatability and accuracy of discrete solutions

while eliminating a number of discrete parts on the board. Converter efficiency is easily tuned with this one

repeatable adjustment. The programmed dead time is the same for both GATE-to-GAT2 and GAT2-to-GATE

transitions. The dead time is triggered from internal signals that are several stages back in the driver to eliminate

the effects of gate loading on the period, however the observed and actual dead-time will be somewhat

dependent on the gate loading. The turnoff of GAT2 coincides with the start of the internal clock period.

DT may be used to disable GAT2, which goes to a high-impedance state.

GATE’s phase turns the main switch on when it transitions high, and off when it transitions low. GAT2’s phase

turns the second switch off when it transitions high, and on when it transitions low. Both switches should be off

when GAT2 is high and GATE is low. The signal phasing is shown in Figure 2. Many topologies that use

secondary-side synchronous rectifiers also use N-Channel MOSFETs driven through a gate-drive transformer.

The proper signal phase for these rectifiers may be achieved by inverting the phasing of the secondary winding

(swapping the leads). Use of the two gate drives is shown in Figure 1 and Figure 28.

FRS and Synchronization

The FRS pin programs the (free-running) oscillator frequency, and may also be used to synchronize the

TPS23754 converter to a higher frequency. The internal oscillator sets the maximum duty cycle at 78% and

controls the slope-compensation ramp circuit. Synchronization may be accomplished by applying a short pulse

(T_SYNC) of magnitude V_SYNCto FRS as shown in Figure 30. The synchronization pulse terminates the potential

on-time period, and the off-time period does not begin until the pulse terminates.

T2P, Startup and Power Management

T2P (type 2 PSE) is an active-low multifunction pin that indicates if

[(PSE = Type_2) + (1.5 V < V_APD) + (1.55 V < V_PPD< 8.3 V)] × (V_CTL< 4 V) × (pd current limit ≠ Inrush).

The term with V_CTLprevents an optocoupler connected to the secondary-side from loading V_Cbefore the

converter is started. The APD and PPD terms allow the PD to operate from an adapter at high-power if a type 2

PSE is not present, assuming the adapter has sufficient capacity. Applications must monitor the state of T2P to

detect power source transitions. Transitions could occur when a local power supply is added or dropped or when

a PSE is enabled on the far end. The PD may be required to adjust the load appropriately. The usage of T2P is

demonstrated in Figure 1.

In order for a type 2 PD to operate at less than 13 W the first 80 ms after power application, the various delays

must be estimated and used by the application controller to meet the requirement. The bootup time of many

applications processors may be long enough to eliminate the need to do any timing.

Thermal Shutdown

The dc/dc controller has an OTSD that can be triggered by heat sources including the V_Bregulator, GATE driver,

bootstrap current source, and bias currents. The controller OTSD turns off V_B, the GATE driver, and forces the

V_Ccontrol into an under-voltage state.

Adapter ORing

Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local power

solution adds cost and complexity, but allows a product to be used if PoE is not available in a particular

installation. While most applications only require that the PD operate when both sources are present, the

TPS23754 supports forced operation from either of the power sources. Figure 27 illustrates three options for

diode ORing external power into a PD. Only one option would be used in any particular design. Option 1 applies

power to the TPS23754 PoE input, option 2 applies power between the TPS23754 PoE section and the power

circuit, and option 3 applies power to the output side of the converter. Each of these options has advantages and

disadvantages. Many of the basic ORing configurations and discussion contained in application note Advanced

Adapter ORing Solutions using the TPS23753 (literature number SLVA306A), apply to the TPS23754.

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Optional for PoE Priority

Low Voltage

Output

DEN

CLS

Power

Circuit

V_SS

RTN

Adapter

Option 2

Adapter

Option 3

Adapter

Option 1

Figure 27. ORing Configurations

The IEEE standards require that the Ethernet cable be isolated from ground and all other system potentials. The

adapter must meet a minimum 1500 Vac dielectric withstand test between the output and all other connections

for ORing options 1 and 2. The adapter only needs this isolation for option 3 if it is not provided by the converter.

Adapter ORing diodes are shown for all the options to protect against a reverse voltage adapter, a short on the

adapter input pins, and damage to a low-voltage adapter. ORing is sometimes accomplished with a MOSFET in

option 3.

PPD ORing Features

The TPS23754 provides several additional features to ease ORing based on the multifunction PPD pin (not

available on TPS23754-1). These include T2P signaling of an option 1 adapter, use of a 24 V adapter (reduced

output power) for option 1, and use of PoE as a power backup in conjunction with option 2. See the Advanced

ORing Techniques section.

ORing Challenges

Preference of one power source presents a number of challenges. Combinations of adapter output voltage

(nominal and tolerance), power insertion point, and which source is preferred determine solution complexity.

Several factors adding to the complexity are the natural high-voltage selection of diode ORing (the simplest

method of combining sources), the current limit implicit in the PSE, and PD inrush and protection circuits

(necessary for operation and reliability). Creating simple and seamless solutions is difficult if not impossible for

many of the combinations. However the TPS23754 offers several built-in features that simplify some

combinations.

Several examples will demonstrate the limitations inherent in ORing solutions. Diode ORing a 48 V adapter with

PoE (option 1) presents the problem that either source might be higher. A blocking switch would be required to

assure which source was active. A second example is combining a 12 V adapter with PoE using option 2. The

converter will draw approximately four times the current at 12 V from the adapter than it does from PoE at 48 V.

Transition from adapter power to PoE may demand more current than can be supplied by the PSE. The

converter must be turned off while C_INcapacitance charges, with a subsequent converter restart at the higher

voltage and lower input current. A third example is use of a 12 V adapter with ORing option 1. The PD hotswap

would have to handle four times the current, and have 1/16 the resistance (be 16 times larger) to dissipate equal

power. A fourth example is that MPS is lost when running from the adapter, causing the PSE to remove power

from the PD. If ac power is then lost, the PD will stop operating until the PSE detects and powers the PD.

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APPLICATION INFORMATION

The TPS23754 will support many power supply topologies that require a single PWM gate drive or two

complementary gate drives and will operate with current-mode control. Figure 1 provides an example of an active

clamp forward converter that uses the second gate driver to control M2, the active element in the clamp. GAT2

may also be used to drive a synchronous rectifier as demonstrated in Figure 28. The TPS23754 may be used in

topologies that do not require GAT2, which may be disabled to reduce its idling loss.

Selecting a converter topology along with a design procedure is beyond the scope of this applications section.

Examples to help in programming the TPS23754 are shown below. Additional special topics are included to

explain the ORing capabilities, frequency dithering, and other design considerations.

For more specific converter design examples refer to the following application notes:

•

Designing with the TPS23753 Powered Device and Power Supply Controller, SLVA305

Designing for High Efficiency with the Active Clamp UCC2891 PWM Controller, SLUA303

Advanced Adapter ORing Solutions using the TPS23753, SLVA306A

TPS23754EVM-420 EVM: Evaluation Module for TPS23754, SLVU301

TPS23754EVM-383 EVM: Evaluation Module for TPS23754, SLVU304

T1

C_IN

V_OUT

L_OUT

R_{T2P_OUT}

V_{T2P_OUT}

T2P

DEN

R_T2P

D_VC1

V_C

PPD

CLS

V_B

M1

PAD

V_SS

M2

V_B

GATE

CS

APD

CTL

FRS

R_OB

C_IZ

D_A

GAT2

T2

R_APD1

TLV431

C_IO

Figure 28. Driven Synchronous Flyback

Input Bridges and Schottky Diodes

Using Schottky diodes instead of PN junction diodes for the PoE input bridges and D_VDDwill reduce the loss of

this function by about 30%. There are however some things to consider when using them.

The IEEE standard specifies a maximum backfeed voltage of 2.8 V. A 100 kΩ resistor is placed between the

unpowered pairs and the voltage is measured across the resistor. Schottky diodes often have a higher reverse

leakage current than PN diodes, making this a harder requirement to meet. Use conservative design for diode

operating temperature, select lower-leakage devices where possible, and match leakage and temperatures by

using packaged bridges to help with this.

Schottky diode leakage current and lower dynamic resistance can impact the detection signature. Setting

reasonable expectations for the temperature range over which the detection signature is accurate is the simplest

solution. Increasing R_DENslightly may also help meet the requirement.

Schottky diodes have proven less robust to the stresses of ESD transients, failing as a short or becoming leaky.

Care must be taken to provide adequate protection in line with the exposure levels. This protection may be as

simple as ferrite beads and capacitors.

A general recommendation for the input rectifiers are 1 A or 2 A, 100 V rated discrete or bridge diodes.

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Protection, D1

A TVS, D₁, across the rectified PoE voltage per Figure 29 must be used. An SMAJ58A, or a part with equal to or

better performance, is recommended for general indoor applications. If an adapter is connected from V_DD1to

RTN, as in ORing option 2 above, voltage transients caused by the input cable inductance ringing with the

internal PD capacitance can occur. Adequate capacitive filtering or a TVS must limit this voltage to be within the

absolute maximum ratings. Outdoor transient levels or special applications require additional protection.

Use of diode D_VDDfor PoE priority may dictate the use of additional protection around the TPS23754. ESD

events between the PD power inputs, or the inputs and converter output, cause large stresses in the hotswap

MOSFET if D_VDDbecomes reverse biased and transient current around the TPS23754 is blocked. The use of

C_VDDand D_RTNin Figure 29 provides additional protection should over-stress of the TPS23754 be an issue. An

SMAJ58A would be a good initial selection for D_RTN. Individual designs may have to tune the value of C_VDD

.

C_VDD

0.01mF

D_VDD

PPD

DEN

CLS

V_SS

Figure 29. Example of Added ESD Protection for PoE Priority

Capacitor, C₁

The IEEE 802.3-2005 standard specifies an input bypass capacitor (from V_DDto V_SS) of 0.05 µF to 0.12 µF.

Typically a 0.1 µF, 100 V, 10% ceramic capacitor is used.

Detection Resistor, R_DEN

The IEEE 802.3-2005 standard specifies a detection signature resistance, R_DENbetween 23.75 kΩ and 26.25 kΩ,

or 25 kΩ ± 5%. Choose an R_DENof 24.9 kΩ.

Classification Resistor, R_CLS

Connect a resistor from CLS to V_SSto program the classification current according to the IEEE 802.3-2005

standard. The class power assigned should correspond to the maximum average power drawn by the PD during

operation. Select R_CLSaccording to Table 1.

For a high power design, choose class 4 and R_CLS= 63.4 Ω.

APD Pin Divider Network, R_APD1, R_APD2

The APD pin can be used to disable the TPS23754 internal hotswap MOSFET giving the adapter source priority

over the PoE source. An example calculation is provided, see literature number SLVA306A.

PPD Pin Divider Network, R_PPD1, R_PPD2

The PPD pin can be used to override the internal hotswap MOSFET UVLO (V_{UVLO_R}and V_{UVLO_H}) when using

low voltage adapters connected between V_DDand V_SS. The PPD pin has an internal 5 µA pulldown current

source. As an example, consider the choice of R_PPD1and R_PPD2, for a 24 V adapter.

1. Select the startup voltage, V_ADPTR-ONapproximately 75% of nominal for a 24 V adapter. Assuming that the

adapter output is 24 V ± 10%, this provides 15% margin below the minimum adapter operating voltage.

26

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2. Choose V_ADPTR-ON= 24 V × 0.75 = 18 V

3. Choose R_PPD2= 3.01 kΩ

4. Calculate R_PPD1

æ

ç

è

ö

÷

ø

æ

ç

ö

V_{ADPTR_ON}- V_PPDEN

÷

18 V - 1.55 V

1.55 V

R_PPD1

=

=ç

÷ = 32.26 kW

÷

ø

V_PPDEN

- I_PPD

R_PPD2

ç

è

- 5 mA

3.01 kW

a.

b. Choose R_PPD1= 32.4 kΩ

5. Check PPD turn on and PPD turn off voltages

é

ù

ú

û

æ

ç

è

ö

÷

ø

V

PPDEN

V

= V

+

R

´

- I

= 18.07 V

ê

ADPTR_ON

PPDEN

PPD1

PPD

R

ê

PPD2

ë

a.

é

ù

ö

æ

V

(

- V

)

- I

PPDEN

PPDH

V

=

V

(

- V

+êR

´ ç

÷ú = 14.54 V

)

ADPTR_OFF

PPDEN

PPDH

PPD1

PPD

ç

è

÷

ú

R

ê

ë

PPD2

ø

û

b.

c. Voltages look acceptable.

6. Check PPD resistor power consumption.

24 V ´ 1.1 ²

2

(

)

3.01 kW + 32.4 kW

(V_DD- V_SS

)

P_RPPD

=

= 19.6 mW

R_PPD1+ R_PPD2

a.

b. Power is acceptable, but resistor values could be increased to reduce the power loss.

Setting Frequency (R_FRS) and Synchronization

The converter switching frequency is set by connecting R_FRSfrom the FRS pin to ARTN. The frequency may be

set as high as 1 MHz with some loss in programming accuracy as well as converter efficiency. Synchronization

at high duty cycles may become more difficult above 500 kHz due to the internal oscillator delays reducing the

available on-time. As an example:

1. Assume a desired switching frequency (f_SW) of 250 kHz.

2. Compute R_FRS

:

17250

(kHz)

17250

250

R

(kW) =

=

= 69

FRS

f

SW

a.

b. Select 69.8 kΩ.

The TPS23754 may be synchronized to an external clock to eliminate beat frequencies from a sampled system,

or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished by

applying a short pulse (T_SYNC) of magnitude V_SYNCto FRS as shown in Figure 30. R_FRSshould be chosen so that

the maximum free-running frequency is just below the desired synchronization frequency. The synchronization

pulse terminates the potential on-time period, and the off-time period does not begin until the pulse terminates.

The pulse at the FRS pin should reach between 2.5 V and V_B, with a minimum width of 22 ns (above 2.5 V) and

rise/fall times less than 10 ns. The FRS node should be protected from noise because it is high-impedance. An

R_Ton the order of 100 Ω in the isolated example reduces noise sensitivity and jitter.

Synchronization

Pulse

FRS

47pF

1000pF

T_SYNC

V_SYNC

T_SYNC

1:1

V_SYNC

Figure 30. Synchronization

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Current Slope Compensation

The TPS23754 provides a fixed internal compensation ramp that suffices for most applications. R_S(see

Figure 31) may be used if the internally provided slope compensation is not enough.

Most current-mode control papers and application notes define the slope values in terms of V_PP/T_S(peak ramp

voltage / switching period), however the electrical characteristics table specifies the slope peak (V_SLOPE) based

on the maximum (78%) duty cycle. Assuming that the desired slope, V_SLOPE-D(in mV/period), is based on the full

period, compute R_Sper the following equation where V_SLOPE, D_MAX, and I_SL-EXare from the electrical

characteristics table with voltages in mV, current in µA, and the duty cycle is unitless (e.g., D_MAX= 0.78).

é

ê

ë

ù

ö

æ

ç

è

V_SLOPE(mV)

D_MAX

V_{SLOPE_D}(mV) -

÷ú

ú

û

ø

R_S(W) =

´ 1000

I_{SL_EX}(mA)

GATE

CS

R_S

R_CS

C_S

Figure 31. Additional Slope Compensation

C_Smay be required if the presence of R_Scauses increased noise, due to adjacent signals like the gate drive, to

appear at the C_Spin.

Blanking Period, R_BLNK

Selection of the blanking period is often empirical because it is affected by parasitics and thermal effects of every

device between the gate-driver and output capacitors. The minimum blanking period prevents the current limit

and PWM comparators from being falsely triggered by the inherent current spike that occurs when the switching

MOSFET turns on. The maximum blanking period is bounded by the output rectifier's ability to withstand the

currents experienced during a converter output short.

If blanking beyond the internal default is desired choose R_BLNKusing R_BLNK(kΩ) = t_BLNK(ns).

1. For a 100 ns blanking interval

a. R_BLNK(kΩ) = 100

b. Choose R_BLNK= 100 kΩ.

The blanking interval can also be chosen as a percentage of the switching period.

1. Compute R_BLNKas follows for 2% blanking interval in a switcher running at 250 kHz.

BIanking_Interval(%)

2

4

R

(kW) =

´ 10

=

´ 10 = 80

BLNK

f

(kHz)

250

SW

a.

b. Select R_BLNK= 80.6 kΩ.

Dead Time Resistor, R_DT

The required dead time period depends on the specific topology and parasitics. The easiest technique to obtain

the optimum timing resistor is to build the supply and tune the dead time to achieve the best efficiency after

considering all corners of operation (load, input voltage, and temperature). A good initial value is 100 ns.

Program the dead time with a resistor connected from DT to ARTN per Equation 3.

1. Choose R_DTas follows assuming a t_DTof 100 ns:

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t

(ns)

100

2

DT

R

(kW) =

=

= 50

DT

2

a.

b. Choose R_DT= 49.9 kΩ

Estimating Bias Supply Requirements and C_VC

The bias supply (V_C) power requirements determine the C_VCsizing and frequency of hiccup during a fault. The

first step is to determine the power/current requirements of the power supply control, then use this to select C_VC

.

The control current draw will be assumed constant with voltage to simplify the estimate, resulting in an

approximate value.

First determine the switching MOSFET gate drive power.

1. Let V_QGbe the gate voltage swing that the MOSFET Q_Gis rated to (often 10 V).

æ

ö

æ

ö

V_C

P_GATE= V_C´ f_SW

´

Q

´

P_GAT2= V_C´ f_SW´ Q

´

ç

÷

ç

÷

GATE

GATE2

ç

÷

ç

è

÷

V_QG

è

ø

a.

b. Compute gate drive power if V_Cis 12 V, Q_GATEis 17 nC, and Q_GAT2is 8 nC.

12

P_GATE= 12 V ´ 250 kHz ´17 nC ´

= 61.2 mW

10

12

10

P_GAT2= 12 V ´ 250 kHz ´ 8 nC ´

= 28.8 mW

c.

P_DRIVE= 61.2 mW + 28.8 mW = 90 mW

d. This illustrates why MOSFET Q_Gshould be an important consideration in selecting the switching

MOSFETs.

2. Estimate the required bias current at some intermediate voltage during the C_VCdischarge. For the

TPS23754, 12 V provides a reasonable estimate. Add the operating bias current to the gate drive current.

P

90 mW

DRIVE

I

=

= 7.5 mA

DRIVE

V

12 V

C

a.

b. I_TOTAL= I_DRIVE+ I_OPERATING= 7.5 mA + 0.92 mA = 8.42 mA

3. Compute the required C_VCbased on startup within the typical softstart period of 4 ms.

T_STARTUP´ I_TOTAL

4 ms ´ 8.42 mA

C_VC1+ C_VC2

=

= 5.18 mF

V_CUVH

6.5 V

a.

b. For this case, a standard 10 µF electrolytic plus a 0.47 µF should be sufficient.

4. Compute the initial time to start the converter when operating from PoE.

a. Using a typical bootstrap current of 4 mA, compute the time to startup.

C

´ V

10.47 mF ´ 15 V

VC1

CUV

T

=

= 39 ms

ST

I

4 mA

VC

b.

5. Compute the fault duty cycle and hiccup frequency

(C

+ C

) ´ V

VC2 CUVH

(10 mF + 0.47 mF) ´ 6.5 V

VC1

T

=

= 17 ms

RECHARGE

I

4 mA

VC

a.

b.

(C

+ C

I

) ´ V

VC2 CUVH

(10 mF + 0.47 mF) ´ 6.5V

8.42 mA

VC1

T

=

= 8.08 ms

DISCHARGE

TOTAL

a. Note that the optocoupler current is 0 mA because the output is in current limit.

b. Also, it is assumed I_T2Pis 0 mA.

T

8.08 ms

DISCHARGE

Duty Cycle: D =

=

= 32%

T

+ T

8.08 ms + 17 ms

DISCHARGE

RECHARGE

c.

d.

1

8.08 ms + 17 ms

Hiccup Frequency: F =

=

= 39.9 Hz

T

+ T

DISCHARGE

RECHARGE

6. With the TPS23754, the voltage rating of C_VC1and C_VC2should be 25 V minimum while with the TPS23756

the rating can be 16 V.

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Switching Transformer Considerations and R_VC

Care in design of the transformer and V_Cbias circuit is required to obtain hiccup overload protection.

Leading-edge voltage overshoot on the bias winding may cause V_Cto peak-charge, preventing the expected

tracking with output voltage. Some method of controlling this is usually required. This may be as simple as a

series resistor, or an R-C filter in front of D_VC1. Good transformer bias-to-output-winding coupling results in

reduced overshoot and better voltage tracking.

R_VCas shown in Figure 32 helps to reduce peak charging from the bias winding. This becomes especially

important when tuning hiccup mode operation during output overload. Typical values for R_VCwill be between 10

Ω and 100 Ω.

D_VC1

R_VC

V_C

T1

Bias Winding

ARTN

Figure 32. R_VCUsage

T2P Pin Interface

The T2P pin is an active low, open-drain output indicating a high power source is available. An optocoupler is

typically used to interface with the T2P pin to signal equipment on the secondary side of the converter of T2P

status. Optocoupler current-gain is referred to as CTR (current transfer ratio), which is the ratio of transistor

collector current to LED current. To preserve efficiency, a high-gain optocoupler ( 250% ≤ CTR ≤ 500%, or 300%

≤ CTR ≤ 600% ) along with a high-impedance (e.g., CMOS) receiver are recommended. Design of the T2P

optocoupler interface can be accomplished as follows:

V_OUT

R_{T2P_OUT}

Type 2 PSE

V_C

R_T2P

Indicator

Low = T2

T2P From

TPS23754

Figure 33. T2P Interface

1. T2P ON characteristic: I_T2P= 2 mA minimum, V_T2P= 1 V

2. Let V_C= 12 V, V_OUT= 5 V, R_T2P-OUT= 10 kΩ, V_T2P-OUT(low) = 400 mV max

V

- V

(low)

5 - 0.4

OUT

T2P-OUT

I

=

= 0.46 mA

RT2P-OUT

R

10000

T2P-OUT

a.

3. The optocoupler CTR will be needed to determine R_T2P. A device with a minimum CTR of 300% at 5 mA

LED bias current is selected. CTR will also vary with temperature and LED bias current. The strong variation

of CTR with diode current makes this a problem that requires some iteration using the CTR versus I_DIODE

curve on the optocoupler data sheet.

a. Using the (normalized) curves, a current of 0.4 mA to 0.5 mA is required to support the output current at

the minimum CTR at 25°C.

a. Pick an I_DIODE. For example one around the desired load current.

b. Use the optocoupler datasheet curve to determine the effective CTR at this operating current. It is

usually necessary to apply the normalized curve value to the minimum specified CTR. It might be

necessary to ratio or offset the curve readings to obtain a value that is relative to the current that the

CTR is specified at.

c. If I_DIODE× CTR_{I_DIODE}is substantially different from I_{RT2P_OUT}, choose another I_DIODEand repeat.

b. This manufacturer’s curves also indicate a –20% variation of CTR with temperature. The approximate

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forward voltage of the optocoupler diode is 1.1 V from the data sheet.

100

I

@ I

´

= 0.5 mA ´

= 0.625 mA

RT2P

MIN

100 - DCTR

100 - 20

TEMP

c.

V

_FLED≈ 1.1 V

V

- V

FLED

12 - 1 - 1.1

C

T2P

R

=

= 15.48 kW

T2P

I

0.625 mA

RT2P

d. Select a 15.4 kΩ resistor. Even though the minimum CTR and temperature variation were considered,

the designer might choose a smaller resistor for a little more margin.

Advanced ORing Techniques

See Advanced Adapter ORing Solutions using the TSP23753, TI document number SLVA306A for ORing

applications that also work with the TPS23754. The material in sections Adapter ORing and Protection, D1 are

important to consider as well. The following applications are unique to the TPS23754 with the introduction of

PPD.

Option 2 ORing with PoE acting as a hot backup is eased by connecting PPD to V_DDper Figure 34. This PPD

connection enables the class regulator even when APD is high. The R-Zener network (1.8 kΩ – 24 V) is the

simplest circuit that will satisfy MPS requirements, keeping the PSE online. This network may be switched out

when the APD is not powered with an optocoupler. This works best with a 48-V adapter and the

APD-programmed threshold as high as possible. An example of an adapter priority application with smooth

switchover between a 48 V adapter and PoE is shown on the right side of Figure 34. D_APDis used to reduce the

effective APD hysteresis, allowing the PSE to power the load before V_VDD1-V_RTNfalls too low and causes a

hotswap foldback.

C_VDD

10nF

D_VDD

For 48V

Adapter

PPD

DEN

CLS

PPD

DEN

CLS

D_A

C_IN

V_SS

D_A

R_APD1

APD

Adapter

Figure 34. Option 2 PoE Backup ORing

Option 1 ORing of a low voltage adapter (e.g., 24 V) is possible by connecting a resistor divider to PPD as in

Figure 35. When 1.55 V ≤ V_PPD≤ 8.3 V, the hotswap MOSFET is enabled, T2P is activated, and the class

feature is disabled. The hotswap current limit is unaffected, limiting the available power. For example, the

maximum input power from a 24 V adapter would be 19.3 W [(24 V – 0.6 V) × 0.825 A].

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DEN

PPD

CLS

V_SS

D_A

APD

R_PPD1

Adapter

Figure 35. Low-Voltage Option 1 ORing

Softstart

Converters require a softstart on the voltage error amplifier to prevent output overshoot on startup. Figure 36

shows a common implementation of a secondary-side softstart that works with the typical TL431 error amplifier.

The softstart components consist of D_SS, R_SS, and C_SS. They serve to control the output rate-of-rise by pulling

V_CTLdown as C_SScharges through R_OB, the optocoupler, and D_SS. This has the added advantage that the TL431

output and C_IZare preset to the proper value as the output voltage reaches the regulated value, preventing

voltage overshoot due to the error amplifier recovery. The secondary-side error amplifier will not become active

until there is sufficient voltage on the secondary. The TPS23754 provides a primary-side softstart which persists

long enough (~4 ms) for secondary side voltage-loop softstart to take over. The primary-side current-loop

softstart controls the switching MOSFET peak current by applying a slowly rising ramp voltage to a second PWM

control input. The PWM is controlled by the lower of the softstart ramp or the CTL-derived current demand. The

actual output voltage rise time is usually much shorter than the internal softstart period. Initially the internal

softstart ramp limits the maximum current demand as a function of time. Either the current limit, secondary-side

softstart, or output regulation assume control of the PWM before the internal softstart period is over. Figure 25

shows a smooth handoff between the primary and secondary-side softstart with minimal output voltage

overshoot.

From Regulated

Output Voltage

R_OB

C_IZ

R_SS

R_FBU

D_SS

C_SS

R_FBL

TLV431

Figure 36. Error Amplifier Soft Start

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Special Switching MOSFET Considerations

Special care must be used in selecting the converter switching MOSFET. The TPS23756 minimum switching

MOSFET V_GATEis ~5.5 V, which is due to the V_Clower threshold. This will occur during an output overload, or

towards the end of a (failed) bootstrap startup. The MOSFET must be able to carry the anticipated peak fault

current at this gate voltage.

Thermal Considerations and OTSD

Sources of nearby local PCB heating should be considered during the thermal design. Typical calculations

assume that the TPS23754 is the only heat source contributing to the PCB temperature rise. It is possible for a

normally operating TPS23754 device to experience an OTSD event if it is excessively heated by a nearby

device.

Frequency Dithering for Conducted Emissions Control

The international standard CISPR 22 (and adopted versions) is often used as a requirement for conducted

emissions. Ethernet cables are covered as a telecommunication port under section 5.2 for conducted emissions.

Meeting EMI requirements is often a challenge, with the lower limits of Class B being especially hard. Circuit

board layout, filtering, and snubbing various nodes in the power circuit are the first layer of control techniques. A

more detailed discussion of EMI control is presented in Practical Guidelines to Designing an EMI Compliant PoE

Powered Device With Isolated Flyback, TI literature number SLUA469. Additionally, IEEE802.3-2005 sections

33.3 and 33.4 have requirements for noise injected onto the Ethernet cable based on compatibility with data

transmission.

Occasionally, a technique referred to as frequency dithering is utilized to provide additional EMI measurement

reduction. The switching frequency is modulated to spread the narrowband individual harmonics across a wider

bandwidth, thus lowering peak measurements. The circuit of Figure 37 modulates the switching frequency by

feeding a small ac signal into the FRS pin. These values may be adapted to suit individual needs.

V_B

6.04kW

+

-

TL331IDBV

10kW

To

301kW

FRS

1mF

ARTN

Figure 37. Frequency Dithering

ESD

The TPS23754 has been tested to EN61000-4-2 using a power supply based on Figure 1. The levels used were

8 kV contact discharge and 15 kV air discharge. Surges were applied between the PoE input and the dc output,

between the adapter input and the dc output, between the adapter and the PoE inputs, and to the dc output with

respect to earth. Tests were done both powered and unpowered. No TPS23754 failures were observed and

operation was continuous. See Figure 29 for additional protection for some test configurations.

ESD requirements for a unit that incorporates the TPS23754 have a much broader scope and operational

implications than are used in TI’s testing. Unit-level requirements should not be confused with reference design

testing that only validates the ruggedness of the TPS23754.

Layout

Printed circuit board layout recommendations are provided in the evaluation module (EVM) documentation

available for these devices.

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Changes from Revision A (April 2009) to Revision B .................................................................................................... Page

•

Deleted The TPS23756 is at PREVIEW status. .................................................................................................................... 1

Changed Preview................................................................................................................................................................... 2

Changed minimum limit ........................................................................................................................................................ 3

Changed limits ....................................................................................................................................................................... 3

Added graph for 756 ............................................................................................................................................................ 12

Added graph for '756 ........................................................................................................................................................... 13

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PACKAGE OPTION ADDENDUM

www.ti.com

9-Jun-2009

PACKAGING INFORMATION

Orderable Device

TPS23754PWP

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

HTSSOP

PWP

20

70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS23754PWP-1

TPS23754PWPR

TPS23754PWPR-1

TPS23756PWP

HTSSOP

PWP

70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS23756PWPR

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jun-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

TPS23754PWPR

TPS23754PWPR-1

TPS23756PWPR

HTSSOP PWP

20

2000

330.0

16.4

6.95

7.1

1.6

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jun-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS23754PWPR

TPS23754PWPR-1

TPS23756PWPR

HTSSOP

PWP

20

2000

346.0

33.0

Pack Materials-Page 2

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logic.ti.com

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