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SLVS312A – JULY 2000 – REVISED DECEMBER 2002

D OR P PACKAGE

(TOP VIEW)

Overvoltage Protection and Lockout for

12 V, 5 V, 3.3 V

Undervoltage Protection and Lockout for

5 V and 3.3 V

PGI

GND

PGO

Fault Protection Output With Open-Drain

Output Stage

FPO

VS5

PSON

VS33

Open-Drain Power Good Output Signal for

Power Good Input, 3.3 V and 5 V

Power Good Delay; 300-ms TPS3510,

150-ms TPS3511

75-ms Delay for 5-V and 3.3-V Power

Supply Short-Circuit Turnon Protection

2.3-ms PSON Control to FPO Turnoff Delay

38-ms PSON Control Debounce

73-µs Width Noise Deglitches

Wide Supply Voltage Range From 4 V

to 15 V

description

The TPS3510/1 is designed to minimize external components of personal-computer switching power supply

systems. It provides protection circuits, power good indicator, fault protection output (FPO) and PSON control.

Overvoltage protection (OVP) monitors 3.3 V, 5 V, and 12 V (12-V signal detects via V

pin). Undervoltage

protection (UVP) monitors 3.3 V and 5 V. When an OV or UV condition is detected, the power good output (PGO)

is set to low and FPO is latched high. PSON from low to high resets the protection latch. UVP function is enabled

75 ms after PSON is set low and debounced. Furthermore, there is a 2.3-ms delay (and an additional 38-ms

debounce) at turnoff. There is no delay during turnon.

Power good feature monitors PGI, 3.3 V and 5 V and issues a power good signal when the output is ready.

The TPS3510/1 is characterized for operation from –40°C to 85°C.

typical application

5 V

PGI

PGO

12 V

0.5 V

Drop

PGI

PGO

GND

FPO

VS5

5 V

PSON VS33

PSON

(From Motherboard)

3.3 V

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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SLVS312A – JULY 2000 – REVISED DECEMBER 2002

FUNCTION TABLE

UV CONDITION

(3.3 V OR 5 V)

OV CONDITION

(3.3 V, 5 V, OR 12 V)

PGI

PGO

PSON

FPO

<0.95 V

yes

<0.95 V

0.95 V<PGI<1.15 V

PGI > 1.15 V

x = don’t care

FPO = L means: fault IS NOT latched

FPO = H means: fault IS latched

PGO = L means: fault

PGO = H means: NO fault

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SLVS312A – JULY 2000 – REVISED DECEMBER 2002

functional block diagram

12 V OV

POR

VS5

5 V OV

FPO

73-µs

Debounce

VS33

2.3-ms

Delay

73-µs

Debounce

3.3 V OV

38-ms

PSON

Debounce

3.3 V UV

75-ms

Delay

5 V UV

PGI1

PGO

150-µs

Debounce

†

Delay

Band-Gap

Reference

1.15 V

PGI2

150-µs Debounce

and

4.8-ms Delay

PGI

Band-Gap

Reference

0.95 V

†

300 ms for TPS3510 and 150 ms for TPS3511

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SLVS312A – JULY 2000 – REVISED DECEMBER 2002

timing diagram

PSON

FPO

PGI

3.3 V, 5 V

12 V

PGO

PG OFF

Delay

Protect

Occur

PSON

AC Off

PSON

PSON Off

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

FPO

GND

PGI

Inverted fault protection output, open drain output stage

Ground

Power good input

PGO

PSON

Power good output, open drain output stage

ON/OFF control

Supply voltage/12 V overvoltage protection input pin

3.3 V over/undervoltage protection

5 V over/undervoltage protection

VS33

VS5

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SLVS312A – JULY 2000 – REVISED DECEMBER 2002

detailed description

power good and power good delay

A PC power supply is commonly designed to provide a power-good signal, which is defined by the computer

manufacturers. PGO is a power-good signal and should be asserted high by the PC power supply to indicate

that the 5-V and 3.3-V outputs are above the under-voltage threshold limit. At this time the converter should be

able to provide enough power to ensure continuous operation within the specification. Conversely, when either

the 5-V or the 3.3-V output voltages fall below the under-voltage threshold, or when ac power has been removed

for a time sufficiently long so that power supply operation is no longer ensured, PGO should be de-asserted to

a low state.

Figure 1 represents the timing characteristics of the power good (PGO), dc enable (PSON), and the 5 V/3.3 V

supply rails.

PSON

Off

75%

10%

5-V/3.3-V

Output

PGO

Figure 1. Timing of PSON and PGO

Although there is no requirement to meet specific timing parameters, the following signal timings are

recommended:

2 ms ≤ t2 ≤ 20 ms, 100 ms < t3 < 2000 ms, t4 > 1 ms, t5 ≤ 10 ms

Furthermore motherboards should be designed to comply with the previously recommended timing. If timings

other than these are implemented or required, this information should be clearly specified.

The TPS3510/1 family of power-supply supervisors provides a power-good output (PGO) for the 3.3-V and 5-V

supply voltage rails and a separate power-good input (PGI). An internal timer is used to generate a power-good

delay. If the voltage signals at PGI, VS33, and VS5 rise above the under-voltage threshold, the open-drain

power-good output (PGO) goes high after a delay of 150 ms or 300 ms. When the PGI voltage or either the 3.3-V

and 5-V power rails drops below the under-voltage threshold, PGO is disabled immediately (after 150-µs

debounce).

power supply remote on/off (PSON) and fault protect output (FPO)

Since the latest personal computer generation focuses on easy turnon and power saving functions, the PC

power supply requires two characteristics. One is a dc power supply remote on/off function, the other is standby

voltage to achieve very low power consumption of the PC system. Thus the main power needs to be shut down.

The power supply remote on/off (PSON) is an active low signal that turns on all of the main power rails including

3.3 V, 5 V, –5 V, 12 V, and –12 V power rails. When this signal is held high by the PC motherboard or left open

circuited, the signal of the fault protect output (FPO) also goes high. Thus, the main power rails should not deliver

current and should be held at 0 V.

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SLVS312A – JULY 2000 – REVISED DECEMBER 2002

power supply remote on/off (PSON) and fault protect output (FPO)(continued)

When the FPO signal is held high due to an occurring fault condition, the fault status is latched and the outputs

of the main power rails should not deliver current but are held at 0 V. Toggling the power supply remote on/off

(PSON) from low to high resets the fault-protection latch. During this fault condition only the standby power is

not affected.

When PSON goes from high to low or low to high, the 38-ms debounce block is active to avoid a glitch on the

input that disables/enables the FPO output. During this period the under-voltage function is disabled for 75 ms

to prevent turnon failure. At turnoff, there is an additional delay of 2.3 ms from PSON to FPO.

Power should be delivered to the rails only if the PSON signal is held at ground potential, thus FPO is active-low.

The FPO pin can be connected to 5 V (or up to 15 V) through a pullup resistor.

undervoltage protection

The TPS3510/1 provides under-voltage protection (UVP) for the 3.3-V and 5-V rails. When an undervoltage

condition appears at either one of the 3.3-V (VS33) or 5-V (VS5) input pins for more than 146 µs, the FPO output

goes high and PGO goes low. Also, this fault condition is latched until PSON is toggled from low to high or V

is removed.

The need for undervoltage protection is often overlooked in off-line switching power supply system design. But

it is very important in battery-powered or hand-held equipment since the TTL or CMOS logic often results in

malfunction.

In flyback or forward-type off-line switching power supplies, usually designed for low power, the overload

protection design is very simple. Most of these types of power supplies are only sensing the input current for

an overload condition. The trigger point needs to be set much higher than the maximum load in order to prevent

false turnon.

However, this causes one critical problem. If the connected load is larger than the maximum allowable load but

smaller than the trigger point, the system always becomes overheated with failure and damage occurring.

overvoltage protection

The overvoltage protection (OVP) of TPS3510/1 monitors 3.3 V, 5 V, and 12 V (12 V is sensed via the V

When an overvoltage condition appears at one of the 3.3-V, 5-V, or 12-V input pins for more than 73 µs, the FPO

pin).

output goes high and PGO goes low. Also, this fault condition is latched until PSON is toggled from low to high

or V

is removed. During fault conditions, most power supplies have the potential to deliver higher output

voltages than those normally specified or required. In unprotected equipment, it is possible for output voltages

to be high enough to cause internal or external damage of the system. To protect the system under these

abnormal conditions, it is common practice to provide overvoltage protection within the power supply.

Because TTL and CMOS circuits are very vulnerable to overvoltages, it is becoming industry standard to provide

overvoltage protection on all 3.3-V and 5-V outputs. However, not only the 3.3-V and 5-V rails for the logic circuits

on the motherboard need to be protected, but also the 12-V peripheral devices such as the hard disk, floppy

disk, and CD-ROM players etc., need to be protected.

short-circuit power supply turnon

During safety testing the power supply might have tied the output voltage direct to ground. If this happens during

the normal operating, this is called a short-circuit or over-current condition. When it happens before the power

supply turns on, this is called a short-circuit power supply turnon. It can happen during the design period, in the

production line, at quality control inspection or at the end user. The TPS3510/1 provides an undervoltage

protection function with a 75-ms delay after PSON is set low.

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SLVS312A – JULY 2000 – REVISED DECEMBER 2002

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage, V

(see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V

Output voltage V : FPO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V

PGO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V

All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16 V

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to GND.

DISSIPATION RATING TABLE

DERATING FACTOR

≤ 25°C

= 70°C

T = 85°C

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING POWER RATING

1092 mW

8.74 mW/°C

5.84 mW/°C

699 mW

467 mW

568 mW

379 mW

730 mW

recommended operating conditions at specified temperature range

MIN NOM

MAX

UNIT

Supply voltage, V

PSON, VS5, VS33

PGI

Input voltage, V

+ 0.3 V

(max = 7 V)

FPO

Output voltage, V

PGO

FPO

Output sink current, I

O,sink

PGO

Supply voltage rising time, t

See Note 2

Operating free-air temperature range, T

–40

°C

NOTE 2:

rising and falling slew rate must be less than 14 V/ms.

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SLVS312A – JULY 2000 – REVISED DECEMBER 2002

electrical characteristics over recommended operating conditions (unless otherwise noted)

overvoltage protection

PARAMETER

TEST CONDITIONS

MIN

3.7

TYP

3.9

MAX

4.1

6.5

14.4

UNIT

VS33

VS5

5.7

6.1

Overvoltage threshold

13.2

13.8

Leakage current (FPO)

V(FPO) = 5 V

µA

LKG

Low-level output voltage (FPO)

Noise deglitch time OVP

= 5 V,

= 5 V

I = 20 mA

sink

0.7

110

µs

PGI and PGO

PARAMETER

TEST CONDITIONS

MIN

1.1

0.9

TYP

1.15

0.95

2.2

MAX

1.2

UNIT

PGI1

PGI2

VS33

VS5

Input threshold voltage (PGI)

PGI

2.4

3.7

Undervoltage threshold

3.3

3.5

Leakage current (PGO)

PGO = 5 V

µA

LKG

Low-level output voltage (PGO)

Short-circuit protection delay

= 4 V,

= 5 V

I = 10 mA

sink

0.4

114

450

225

7.2

225

445

220

3.3 V, 5 V

200

100

3.2

300

150

4.8

TP3510

TP3511

PGI to PGO

Delay time

PGI to FPO

PGI to PGO

PGI to FPO

UVP to FPO

150

296

146

180

Noise deglitch time

µs

PSON control

PARAMETER

TEST CONDITIONS

PSON = 0 V

MIN

TYP

MAX

UNIT

µA

Input pullup current

120

High-level input voltage

Low-level input voltage

Debounce time (PSON)

Delay time (PSON to FPO)

2.4

1.2

= 5 V

t +1.1 t +2.3

t +4

total device

PARAMETER

TEST CONDITIONS

PSON = 5 V

MIN

TYP

MAX

UNIT

Supply current

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SLVS312A – JULY 2000 – REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

SUPPLY VOLTAGE

INPUT CURRENT (PSON)

INPUT VOLTAGE (PSON)

400

300

= 4 V

= –40°C

–20

–40

–60

–80

= 85°C

200

100

= 25°C

= 0°C

= –40°C

= 0°C

= 25°C

= 85°C

–100

–120

–200

–300

PGI = 1.4 V

PSON = 5 V

–140

2.5

7.5

12.5

– Supply Voltage – V

V – Input Voltage – V

Figure 2

Figure 3

LOW-LEVEL OUTPUT VOLTAGE (FPO)

LOW-LEVEL OUTPUT CURRENT (FPO)

LOW-LEVEL OUTPUT VOLTAGE (FPO)

LOW-LEVEL OUTPUT CURRENT (FPO)

800

700

= 4 V

PSON = GND

= 4 V

PSON = GND

Exploded View

600

500

= 85°C

400

300

= 25°C

T = –40°C

= –40°C

= 25°C

200

100

= 0°C

120

100

– Low-Level Output Current – mA

Figure 4

Figure 5

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SLVS312A – JULY 2000 – REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

LOW-LEVEL OUTPUT VOLTAGE (PGO)

LOW-LEVEL OUTPUT CURRENT (PGO)

600

500

= 4 V

PSON = GND

Exploded View

= 85°C

400

300

= 85°C

= –40°C

= 25°C

200

100

= –40°C

= 0°C

100

150

125

– Low-Level Output Current – mA

Figure 6

Figure 7

NORMALIZED SENSE THRESHOLD VOLTAGE

FREE-AIR TEMPERATURE AT V

1.001

= 4 V

PSON = GND

0.999

0.998

0.997

0.996

0.995

0.994

–40

–15

– Free-Air Temperature – °C

Figure 8

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SLVS312A – JULY 2000 – REVISED DECEMBER 2002

MECHANICAL DATA

D (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0.050 (1,27)

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

0.008 (0,20) NOM

0.244 (6,20)

0.228 (5,80)

0.157 (4,00)

0.150 (3,81)

Gage Plane

0.010 (0,25)

0°–ā8°

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.004 (0,10)

0.010 (0,25)

0.004 (0,10)

0.069 (1,75) MAX

PINS **

DIM

0.197

(5,00)

0.344

(8,75)

0.394

(10,00)

A MAX

0.189

(4,80)

0.337

(8,55)

0.386

(9,80)

A MIN

4040047/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-012

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢀ ꢁꢂꢃ ꢄꢅꢅ

ꢁ ꢈ ꢁꢉꢊ ꢋꢌ ꢂꢍ ꢁ ꢁꢎꢏ ꢂ ꢍꢁ ꢋꢌꢐ ꢑ ꢂꢉ ꢌꢂ

SLVS312A – JULY 2000 – REVISED DECEMBER 2002

MECHANICAL DATA

P (R-PDIP-T8)

PLASTIC DUAL-IN-LINE

0.400 (10,60)

0.355 (9,02)

0.260 (6,60)

0.240 (6,10)

0.070 (1,78) MAX

0.325 (8,26)

0.300 (7,62)

0.020 (0,51) MIN

0.015 (0,38)

Gage Plane

0.200 (5,08) MAX

Seating Plane

0.010 (0,25) NOM

0.125 (3,18) MIN

0.100 (2,54)

0.021 (0,53)

0.430 (10,92)

MAX

0.010 (0,25)

0.015 (0,38)

4040082/D 05/98

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

in which TI products or services are used. Information published by TI regarding third–party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

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Post Office Box 655303

Dallas, Texas 75265

TPS3510相关文章

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TPS3510D产品参数

型号:	TPS3510D
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25
针数：	8
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	0.71
可调阈值：	NO
模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e4
长度：	4.9 mm
湿度敏感等级：	1
信道数量：	3
功能数量：	1
端子数量：	8
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
电源：	4/15 V
认证状态：	Not Qualified
座面最大高度：	1.58 mm
子类别：	Power Management Circuits
最大供电电流 (Isup)：	1 mA
最大供电电压 (Vsup)：	15 V
最小供电电压 (Vsup)：	4 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	1.27 mm
端子位置：	DUAL
阈值电压标称：	2.2
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.91 mm
Base Number Matches：	1

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