TPS5102IDB原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

TPS5102

DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER

SLVS239 - SEPTEMBER 1999

DBT PACKAGE

(TOP VIEW)

Dual, Step-Down for Notebook System

Power

4.5 V to 25 V Input Voltage Range

Adjustable Output Voltage

95% Efficiency Achievable

INV1

FB1

LH1

1

30

29

28

27

26

25

24

23

22

21

20

OUT1_u

LL1

2

SOFTSTART1

PWM_SKIP

3

OUT1_d

OUTGND1

TRIP1

4

PWM/Skip Mode Control Maintains High

Efficiency Under Light Load Conditions

C

5

T

R

T

GND

REF

6

Fixed-Frequency Operation

Resistorless Current Protection

Fixed High-Side Driver Voltage

VCC_CNTP

TRIP2

7

8

STBY1

STBY2

VREF5

9

Low Quiescent Current (0.6 mA, <1 µA for

Standby)

REG5V_IN

OUTGND2

10

11

V

CC

COMP 12

SOFTSTART2 13

FB2 14

19 OUT2_d

18 LL2

Small 30-Pin TSSOP

EVM Available (TPS5102EVM-135)

17 OUT2_u

15

16

INV2

LH2

description

TheTPS5102isadual, highefficiencycontrollerdesignedfornotebooksystempowerrequirements. Underlight

load conditions, high efficiency is maintained as the controller switches from the PWM mode to the lower

frequency Skip mode.

These two operating modes, along with the synchronous-rectifier drivers, dead-time, and very low quiescent

current, allow power to be conserved and the battery life extended, under all load conditions.

The resistor-less current protection and fixed high-side driver voltage simplify the system design and reduce

the external parts count. The wide input voltage range and adjustable output voltages allow flexibility for using

the TPS5102 in notebook power supply applications.

5 V

R3

+

C1

Q1

Q2

R7

GND

L1

R5

C7

C3

U1

R8

D1

Vo1

TPS5102DBT

+

C10

C12

C4

C8

R2

R9

R10

C2

C5

C13

+

C11

Q3

Q4

C6

R4

Vo2

R11

D2

L2

C9

R1

R6

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

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TPS5102

DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER

SLVS239 - SEPTEMBER 1999

functional block diagram

V

CC

To Channel 2

STNBY2

STNBY1

VREF5

REF

REG5V_IN

1.185 V

REF

_

+

UVLO

+

_

To

Channel 2

4.5 V

RT

CT

OSC

3.8 V

To Channel 2

LH

To

Channel 2

COMP

+

_

To

OUT_U

LL

1.1 V

1 Shot

PWM/SKIP

OUT_D

SOFTSTART

OUTGND

_

+

Sync.

Signal

Skip Comp

To

Channel 2

VCC_CNTP

TRIP

_

+

_

+

PWM Comp

+

INV

FB

+

Error Amp

1.185 V

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5102

DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER

SLVS239 - SEPTEMBER 1999

AVAILABLE OPTIONS

T

PACKAGE

TSSOP(DBT)

TPS5102IDBT

TPS5102IDBTR

EVM

A

–40°C to 85°C

TPS5102EVM-135

Terminal Functions

TERMINAL

NAME

COMP

I/O

DESCRIPTION

NO.

12

5

I/O

O

Voltage monitor comparator input

C

External capacitor connection for switching frequency adjustment

CH1 error amp output

T

FB1

FB2

GND

INV1

INV2

LH1

LH2

LL1

2

14

7

O

CH2 error amp output

Control GND

1

I

CH1 inverting input

15

30

16

28

18

27

19

29

17

26

20

4

I

CH2 inverting input

I/O

O

CH1 boost capacitor connection

CH2 boost capacitor connection

CH1 boost circuit connection

CH2 boost circuit connection

CH1 low-side gate-drive output

CH2 low-side gate-drive output

CH1 high-side drive output

CH2 high-side drive output

Output GND 1

LL2

OUT1_d

OUT2_d

OUT1_u

O

OUT2_u

O

OUTGND1

OUTGND2

PWM_SKIP

Output GND 2

I

PWM/SKIP mode select

L:PWM mode

H:SKIP mode

REF

8

O

1.185-V reference voltage output

REG5V_IN

21

6

I

External 5-V input

R

T

I/O

External resistor connection for switching frequency adjustment

External capacitor connection for CH1soft start timing.

External capacitor connection for CH2 soft start timing.

CH1 stand-by control

SOFTSTART1

SOFTSTART2

STBY1

3

I/O

13

9

I/O

I

STBY2

10

23

25

11

22

24

CH2 stand-by control

TRIP2

External resistor connection for CH2 over current protection.

External resistor connection for CH1 over current protection.

Supply voltage input

TRIP1

V

CC

V 5

ref

O

I

5-V internal regulator output

VCC_CNTP

Supply voltage sense input

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5102

DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER

SLVS239 - SEPTEMBER 1999

detailed description

Vref (1.185 V)

The reference voltage is used to set the output voltage and the overvoltage protection (COMP).

Vref5 (5 V)

The internal linear voltage regulator is used for the high-side driver bootstrap voltage. Since the input voltage

range is from 4.5 V to 25 V, this feature offers a fixed voltage for the bootstrap voltage greatly simplifying the

drive design. It is also used for powering the low side driver. The tolerance is 6%.

5-V Switch

If the internal 5 V switch senses a 5-V input from REG5V_IN pin, the internal 5-V linear regulator will be

disconnected from the MOSFET drivers. The external 5 V will be used for both the low-side driver and the high

side bootstrap, thus increasing the efficiency.

PWM/SKIP

This pin is used to change between PWM and Skip mode. If the pin is lower than 0.5-V, the IC is in regular PWM

mode; if a minimum 2-V is applied to this pin, the IC works in Skip mode. In light load condition (<0.2 A), the

skip mode gives a short pulse to the low-side FET instead of a full pulse. By this control, switching frequency

is lowered, reducing switching loss; also the output capacitor energy discharging through the output inductor

and the low-side FET is prevented. Therefore, the IC can achieve high efficiency at light load conditions

(< 0.2 A).

err-amp

Each channel has its own error amplifier to regulate the output voltage of the synchronous-buck converter. It

is used in the PWM mode for the high output current condition (>0.2A). Voltage mode control is applied.

skip comparator

In Skip mode, each channel has its own hysteretic comparator to regulate the output voltage of the

synchronous-buck converter. The hysteresis is set internally and typically at 8.5 mV. The delay from the

comparator input to the driver output is typically 1.2 µs.

low-side driver

The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The maximum drive voltage is 5 V

from Vref5. The current rating of the driver is typically 1 A, source and sink.

high-side driver

The high side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is

1 A, source and sink. When configured as a floating driver, the bias voltage to the driver is developed from Vref5,

limiting the maximum drive voltage between OUT_u and LL to 5 V. The maximum voltage that can be applied

between LHx and OUTGND is 30 V.

deadtime control

Deadtime prevents shoot–through current from flowing through the main power FETs during switching

transitions by actively controlling the turn-on time of the MOSFETs drivers. The typical deadtime from

low-side-driver-off to high-side-driver-on is 70 ns, and 85 ns from high-side-driver-off to low-side-driver-on.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5102

DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER

SLVS239 - SEPTEMBER 1999

detailed description (continued)

current protection

Current protection is achieved by sensing the high-side power MOSFET drain-to-source voltage drop during

on-time at VCC_CNTP and LL. An external resistor between Vin and TRIP pin in serial with the internal current

source adjusts the current limit. When the voltage drop during the on-time is high enough, the current

comparator triggers the current protection and the circuit is reset. The reset repeats until the over-current

condition is removed.

COMP

COMP is an internal comparator used for any voltage protection such as the output under-voltage protection

for notebook power applications. If the core voltage is lower than the setpoint, the comparator turns off both

channels to prevent the notebook from damage.

SOFT1, SOFT2

Separate softstart terminals make it possible to set the start-up time of each output for any possibility.

STBY1, STBY2

Both channels can be switched into standby mode separately by grounding the STBY pin. The standby current

is as low as 1 µA.

ULVO

When the input voltage goes up to about 4 V, the IC is turned on, ready to function. When the input voltage is

lower than the turn-on value, the IC is turned off. The typical hysteresis is 40 mV.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5102

DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER

SLVS239 - SEPTEMBER 1999

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage, Vcc (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 27 V

Input voltage, INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V

SOFTSTART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V

COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V

REG5_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V

STBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 15 V

Driver current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A

TRIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 27 V

C

R

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V

T

LL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 27 V

LH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 32 V

OUT_u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 32 V

OUT_d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V

PWM/SKIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V

VCC_Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 27V

Power dissipation (T = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874 mW

A

Operating temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C

A

Operating temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 125°C

J

Storage temperature (T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 150°C

STG)

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to the network ground terminal.

2. This rating is specified at duty ≤ 10% on output rise and fall each pulse. Each pulse width (rise and fall) for the peak current should

not exceed 2 µs.

3. See Dissipation Rating Table for free-air temperature range above 25°C.

DISSIPATION RATING TABLE

T

≤ 25°C

DERATING FACTOR

T = 85°C

A

PACKAGE

DBT

POWER RATING

ABOVE T = 25°C

POWER RATING

A

874 mW

6.993 mW/°C

454 mW

recommended operating conditions

PARAMETERS

MIN NOM

MAX

25

UNIT

Supply voltage, Vcc

4.5

-0.1

V

INV1/2 C R ,

PWM/SKIP, SOFTSTART

VCC_SENSE

6

T

5 V_IN

5.5

12

Input voltage, V

V

I

STBY1, STBY2

TRIP1/2

25

C

R

100

82

pF

kΩ

T

Oscillator frequency

T

f

PWM

200

KHz

°C

osc

Operation temperature range, T

-40

85

A

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5102

DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER

SLVS239 - SEPTEMBER 1999

electrical characteristics over recommended operating free-air temperature range, V

(unless otherwise noted)

= 7 V

CC

reference voltage

PARAMETER

TEST CONDITIONS

= 25°C, = 50 µA

MIN

TYP

MAX

UNIT

T

I

vref

1.167 1.185 1.203

A

Vref

Reference voltage

V

I

= 50 µA

1.155

1.215

12

vref

Regin Line regulation

Regl Load regulation

Vcc = 4.5, 25V,

I = 50 µA

0.2

0.5

mV

I = 0.1 µA to 1 mA

10

quiescent current

PARAMETER

TEST CONDITIONS

Both STBY > 2.5 V,

No switching, Vin = 4.5 – 25 V

MIN

TYP

0.6

1

MAX

1.5

UNIT

mA

Icc

Operating current without switching

Stand-by current

Iccs

Both STBY < 0.5 V, Vin = 4.5 – 25 V

1000

nA

oscillator

PARAMETER

Frequency

Timing resistor

TEST CONDITIONS

MIN

TYP

MAX

UNIT

kHz

kΩ

fosc

PWM operation

500

R

T

56

fdv

fdt

Vcc = 4.5 V to 25 V

= -40°C to 85°C

0.1%

2%

fosc change

T

A

DC, includes internal comparator error

1

1.1

1.2

0.6

V

H-level output voltage

L-level output voltage

V

oscH

Fosc = 200 kHz, Includes internal comparator error

Includes internal comparator error

1.17

0.5

0.4

V

oscL

Fosc = 200 kHz, Includes internal comparator error

0.43

error amp

PARAMETER

TEST CONDITIONS

MIN

50

TYP

MAX

UNIT

mV

dB

Vio

Av

Input offset voltage

Open-loop voltage gain

T

A

= 25°C

±2

±10

GB

Isnk

Isrc

Unity-gain bandwidth

Output sink current

Output source current

0.8

45

MHz

µA

Vo = 0.4 V

Vo = 1 V

30

300

µA

skip comparator

PARAMETER

Hysteresis window

Offset voltage

TEST CONDITIONS

MIN

TYP

9.5

2

MAX

UNIT

mV

pA

†

Vhys

6

13

Vhoff

Ihbias

Bias current

10

‡

T

Propagation delay from INV to OUTxU

TTL input signal

10 mV overdrive on hysteresis band signal

0.7

1.2

µs

LHT

µs

LH

†

‡

Vhys is assured by design.

The total delay in the table includes the driver delay.

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5102

DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER

SLVS239 - SEPTEMBER 1999

electrical characteristics over recommended operating free-air temperature range, V

(unless otherwise noted) (continued)

= 7 V

CC

driver deadtime

PARAMETER

Low side to high side

High side to low side

TEST CONDITIONS

MIN

TYP

70

MAX

UNIT

nS

T

DRVLH

85

nS

DRVHL

standby

PARAMETER

H-level input voltage

L-level input voltage

Propagation delay

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

2.5

IH

STBY1, STBY2

V

0.5

IL

T

1.5

1.8

turnon

STBY to driver output

µs

Propagation delay

turnoff

5V regulator

PARAMETER

Output voltage

TEST CONDITIONS

MIN

TYP

MAX

5.3

20

UNIT

V

I = 10 mA

4.7

O

Regin

Regl

Ios

Line regulation

Vcc = 5.5 V, 25 V,

I = 1 V, 10 mA,

Vref = 0 V

I = 10 mA

mV

mA

Load regulation

Vcc = 5.5 V

40

Short-circuit output current

80

5-V internal switch

PARAMETER

TEST CONDITIONS

MIN

4.2

4.1

30

TYP

MAX

4.8

UNIT

V

TLH

THL

hys

Threshold voltage

Hysteresis

4.7

V

150

mV

UVLO

PARAMETER

MIN

3.7

3.6

10

TYP

MAX

4.2

UNIT

V

TLH

V

THL

V

hys

Threshold voltage

Hysteresis

4.1

V

40

150

mV

current limit

PARAMETER

MIN

10

3

TYP

15

MAX

20

UNIT

µA

PWM mode

Skip mode

Internal current source

Input offset voltage

5

7

2.5

mV

driver output

PARAMETER

OUT_u sink current

MIN

0.5

–1

TYP

1.2

MAX

UNIT

Vo = 3 V

A

OUT_d sink current

OUT_u source current

OUT_d source current

1.2

–1.7

–1.5

A

–1

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5102

DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER

SLVS239 - SEPTEMBER 1999

electrical characteristics over recommended operating free-air temperature range, V

(unless otherwise noted) (continued)

= 7 V

CC

softstart

PARAMETER

Soft-start current

TEST CONDITIONS

MIN

TYP

2.5

MAX

UNIT

µA

I

1.8

3

CTRL

Maximum discharge current

0.92

3.9

mA

V

3.4

1.8

4.7

3.4

TLH

Threshold voltage (skip mode)

V

2.6

THL

output voltage protection (COMP)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Threshold voltage

0.9

1.1

1.3

V

†

Progagation delay , 50% duty cycle,

No capacitor on COMP or OUT_u pin,

Frequency = 200 kHz

Turnon

Turnoff (with channel on)

900

400

ns

†

The delay time in the table includes the driver delay.

PWM/SKIP

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

High to low

Low to high

High to low

Low to high

0.5

Threshold

V

2

550

400

Delay

ns

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5102

DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER

SLVS239 - SEPTEMBER 1999

TYPICAL CHARACTERISTICS

QUIESCENT CURRENT (BOTH CHANNELS ON)

QUIESCENT CURRENT (BOTH CHANNELS STANDBY)

vs

INPUT VOLTAGE

800

700

600

500

400

160

140

120

100

T

= 125°C

J

T

J

= -40°C

T

J

= 25°C

T

J

= 125°C

80

60

40

300

200

T

J

= -40°C

100

0

T

= 25°C

20

0

J

0

10

20

30

4.5

7

10

15

20

25

V

CC

- Supply Voltage - V

V

CC

- Supply Voltage - V

Figure 1

Figure 2

DRIVE CURRENT (SOURCE)

DRIVE CURRENT (SINK)

vs

DRIVE VOLTAGE

6

5

4

3.5

3

T

= -40°C

J

2.5

2

T

J

= 125°C

T

J

= 25°C

T

J

= 125°C

3

2

T

J

= 25°C

1.5

1

T

J

= -40°C

1

0

0.5

0

0.1

0.5

1

0.1

0.5

1

I

- Driver Source Current - A

I

- Driver Sink Current - A

(src)

(snk)

Figure 3

Figure 4

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5102

DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER

SLVS239 - SEPTEMBER 1999

TYPICAL CHARACTERISTICS

CURRENT PROTECTION SOURCE CURRENT

(SKIP MODE)

vs

(PWM MODE)

vs

INPUT VOLTAGE

14

13.8

13.6

13.4

13.2

13

5.2

5.1

5

T

= 125°C

= 25°C

J

T

= 125°C

J

4.9

4.8

4.7

4.6

T

J

T

J

= -40°C

T

J

= 25°C

4.5

4.4

T

= -40°C

J

12.8

12.6

4.3

4.2

4.5

7

10

15

20

25

0

10

20

30

V

CC

- Supply Voltage - V

V

CC

- Supply Voltage - V

Figure 6

Figure 5

PWM/SKIP THRESHOLD VOLTAGE

V

VOLTAGE

vs

CURRENT

ref5

vs

INPUT VOLTAGE

1

5.1

5

T

J

= -40°C

0.9

0.8

0.7

0.6

0.5

T

J

= 125°C

T

J

= 125°C

T

J

= 25°C

4.9

4.8

4.7

4.6

4.5

T

J

= 25°C

T

J

= -40°C

0.4

0.3

0.2

0.1

0

10

20

30

0

–10

–20

–30

–40

–50

V - Supply Voltage - V

I

I - Current - mA

r

Figure 7

Figure 8

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TYPICAL CHARACTERISTICS

SOFT START CHARGE CURRENT

MAXIMUM OUTPUT VOLTAGE

vs

SWITCHING FREQUENCY

vs

JUNCTION TEMPERATURE

–3

2.5

–2.5

2

–2

1.5

–1.5

–1

1

0.5

0

–0.5

0

–40 –20

0

25

50

70

95

125

1

10

100

1000

T

J

- Junction Temperature - °C

Switching Frequency – kHz

Figure 9

Figure 10

SWITCHING FREQUENCY

vs

TIMING RESISTOR

1000

C = 47 pF

t

100

C = 100 pF

t

C = 150 pF

t

C = 220 pF

t

C = 330 pF

t

10

100

1000

Timing Resistor - kΩ

Figure 11

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TYPICAL CHARACTERISTICS

timing diagram

1.17 V Typ.

Err. Amplifier Output

Oscillator Output

OUTx_u

0.43 V Typ.

High

Delay

Low

(100 nS Typ.)

Delay

Duty

High

Low

OUTx_d

(100 nS Typ.)

Detected Over Current

High

Low

Over-Current

Protection

Current Limit

Inductor Current

I

= 0

L

TRIPx Voltage

LLx Voltage

GND

-Vf

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TPS5102

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APPLICATION INFORMATION

The design shown in this application report is a reference design for notebook applications. An evaluation

module (EVM), TPS5102EVM-135 (SLVP135), is available for customer testing and evaluation. The intent is

to allow a customer to fully evaluate the given design using the plug-in EVM supply shown here. For subsequent

customer board revisions, the EVM design can be copied onto the users’ PCB to shorten design cycle.

The following key design procedures will aid in the design of the notebook power supply using the TPS5102:

SLVP135 EVM

TP27

C6

R3

R5

Q1

Q2

TP26

R17

C2

R4

L1

R6

C7

R1

C8

J1

J2

D3

RS1

TP24

TP23

TP1

TP2

+

Vo1

J3

D1

C17

C4

C22

+

Vo1

TP3

R8

J4

C9

C10

Vo1GND

Vin

TP22

TP21

TP4

J5

C18

R18

TP5

J6

JP1

R9

TP6

J7

Vin

TP7

C1

J8

J15

GND

Input GND

Vo2GND

Vo2

R19

C19

C11

TP20

TP19

TP8

R10

J9

J16

TP9

GND

J10

J11

J12

J13

J14

R11

R21

TP10

TP11

TP12

TP13

TP14

TP15

JP2

R12

C12

C13

TP18

C23

Vo2

C5

+

D2

RS2

C21

D4

+

Q4

C15

TP17

TP16

R2

L2

R20

C14

R13

R14

R15

R16

C20

C3

TP25

Q3

TP28

C16

Vin

Iin

Vo1

3.3 V

Io1

Vo2

5 V

Io2

6 V to 15 V

6 A

4 A

16 V to 25 V

2.5 A

output voltage setpoint calculation

The output voltage is set by the reference voltage and the voltage divider. In the TPS5102, the reference voltage

is 1.185-V, and the divider is composed of two resistors in the EVM design that are R4 and R5, or R14 and R15.

The equation for the setpoint is:

R1

Vo–Vr

Vr

R2

Where R1 is the top resistor (kΩ) ( R4 or R15); R2 is the bottom resistor (kΩ) ( R5 or R14); Vo is the required

output voltage (V); Vr is the reference voltage (1.185 V in TPS5102).

Example: R1 = 1 kΩ; Vr = 1.185 V; Vo = 3.3 V, then R2 = 560 Ω.

Some of the most popular output voltage setpoints are calculated in the table below:

V

1.3 V

1 V

1.5 V

1 V

1.8 V

1 V

2.5 V

1 V

3.3 V

1 V

5 V

1 V

O

R1 (top) (kΩ)

R2 (bottom) (kΩ)

10 V

3.7 V

1.9 V

0.9 V

0.56 V

0.31 V

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APPLICATION INFORMATION

output voltage setpoint calculation (continued)

If a higher precision resistor is used, the voltage setup can be more accurate.

In some applications, the output voltage is required to be lower than the reference voltage. With a few extra

components, the lower voltage can be easily achieved. The drawing below shows the method.

V

CC

V

O

R

(top)

z1

INV

R

z2

TPS5102

R

Zener

(bottom)

In the schematic, the Rz1, the Rz2, and the zener are the extra components. Rz1 is used to give the zener

enough current to build up the zener voltage. The zener voltage is added to INV through Rz2. Therefore, the

voltage on the INV is still equal to the IC internal voltage (1.185 V) even if the output voltage is regulated at a

lower setpoint. The equation for setting up the output voltage is shown below:

( Vz –Vr )

Rz 2 =

(Vr–Vo)

Rtop

Vr

Rbtm

+

When Rz2 is the adjusting resistor for low output voltage; Vz is the zener voltage; Vr is the internal reference

voltage; Rtop is the resistor of the voltage sensing network; Rbtm is the bottom resistor of the sensing

network;V is the required output voltage setpoint.

O

Example: Assuming the required output voltage setpoint is V = 0.8 V, V = 5 V; Rtop = 1 kΩ; Rbottom = 1 kΩ,

O

Z

Then the Rz2 = 2.43 kΩ.

output inductor ripple current

The output inductor current ripple can affect not only the efficiency, but also the output voltage ripple. The

equation is exhibited below:

Vin Vout Iout (Rdson R_L)

Iripple

D

Ts

Lout

Where Iripple is the peak-to-peak ripple current (A) through the inductor; Vin is the input voltage (V); Vout is the

outputvoltage(V);Ioutistheoutputcurrent; Rdsonistheon-timeresistanceofMOSFET(Ω);Disthedutycycle;

and Ts is the switching cycle (S). From the equation, it can be seen that the current ripple can be adjusted by

changing the output inductor value.

Example: Vin = 5 V; Vout = 1.8 V; Iout = 5 A; Rdson = 10 mΩ; RL = 5 mΩ; D = 0.36; Ts = 10 µS; Lout = 6 µH

Then, the ripple Iripple = 2 A.

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APPLICATION INFORMATION

output capacitor RMS current

Assuming the inductor ripple current totally goes through the output capacitor to ground, the RMS current in the

output capacitor can be calculated as:

I

Iorms

12

Where Io(rms) is the maximum RMS current in the output capacitor (A); ∆I is the peak-to-peak inductor ripple

current (A).

Example: ∆I = 2 A, so Io(rms) = 0.58 A

input capacitor RMS current

Assuming the input ripple current totally goes into the input capacitor to the power ground, the RMS current in

the input capacitor can be calculated as:

1

12

Iirms

Io²

D

(1–D)

D

Iripple²

Where Ii(rms) is the input RMS current in the input capacitor (A); Io is the output current (A); Iripple is the

peak-to-peak output inductor ripple current; D is the duty cycle. From the equation, it can be seen that the

highest input RMS current usually occurs at the lowest input voltage, so it is the worst case design for input

capacitor ripple current.

Example: Io = 5 A; D = 0.36; Iripple = 2 A,

Then, Ii(rms) = 2.42 A

soft-start

The soft-start timing can be adjusted by selecting the soft-start capacitor value. The equation is

C

2

T

soft

Where C

is the soft-start capacitance (µF) (C9 or C13 in EVM design); T

is the start-up time (S).

soft

Example: Tsoft = 5 mS, so Csoft = 0.01 µF.

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APPLICATION INFORMATION

current protection

The current limit in TPS5102 on each channel is set using an internal current source and an external resistor

(R18 or R19). The sensed high side MOSFET drain-to-source voltage drop is compared to the set point, if the

voltage drop exceeds the limit, the internal oscillator is activated, and it continuously reset the current limit until

the over-current condition is removed. The equation below should be used for calculating the external resistor

value for current protection setpoint:

Rds(on)

(Itrip Iind(p-p) 2)

0.000015

Rcl

In skip mode,

Rds(on)

(Itrip Iind(p-p) 2)

0.000005

Rcl

Where Rcl is the external current limit resistor (R10 or R11); Rds(on) is the high side MOSFET (Q1 or Q3)

on-time resistance. Itrip is the required current limit; Iind(p-p) is the peak-to-peak output inductor current.

Example for voltage mode: Rds(on) = 10 mΩ, Itrip = 5 A, Iind = 2 A, so Rcl = 4 kΩ.

loop-gain compensation

Voltage mode control is used in this controller for the output voltage regulation. To achieve fast, stabilized

control, two parts are discussed in this section: the power stage small signal modeling and the compensation

circuit design.

For the buck converter, the small signal modeling circuit is shown below:

Z

L

V

ap

d

L

D

R

a

c

L

+

-

V

O

i

a

i

c

D

1

+

C

R

V

I

c

d

Z

RC

R

C

p

From this equivalent circuit, several control transfer functions can be derived: input-to-output, output

impedance, and control-to-output. Typically the control-to-output transfer function is used for the feedback

control design.

Assuming Rc and RL are much smaller than R, the simplified small signal control-to-output transfer function is:

(1 sCRc)

Vo

d

Vod

L

R

1

s C

Rc

R

s²LC

L

Where C is the output capacitance; Rc is the equivalent serial resistance (ESR) in the output capacitor; L is the

output inductor; RL is the equivalent serial resistance (DCR) in the output inductor; R is the load resistance.

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APPLICATION INFORMATION

loop-gain compensation (continued)

To achieve fast transient response and the better output voltage regulation, a compensation circuit is added to

improve the feedback control. The whole system is shown:

Power

Stage

PWM

V

ref

Compensation

The typical compensation circuit used as an option in the EVM design is a part of the output feedback circuit.

The circuitry is displayed below:

C3

R1

C1

R2

R4

C2

_

To PWM

+

V

ref

R3

This circuit is composed of one integrator, two poles, and two zeros:

Assuming R1 << R2 and C2 << C3, the equation is:

(

)

(

) (

)

sC2R2

)

sC1R1

1

sC3R4

(

1

Comp

sC3R2 1 sC2R4

1

Therefore,

Pole1

1

Zero1

Zero2

2 C1R1

2 C2R2

1

Pole2

Integrator

2 C2R4

2 C3R4

2 C3R2

A simplified version used in the EVM design is exhibited below:

18

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APPLICATION INFORMATION

loop-gain compensation (continued)

V

O

C3

R2

R4

C2

_

To PWM

+

V

ref

R3

Assuming C2 << C3, the equation is:

(

)

sC3R4

1

Comp

(

)

sC3R2 1 sC2R4

There is one pole, one zero and one integrator:

1

Zero

Integrator

Pole

2 C3R4

2 fC3R2

2 C2R4

The loop-gain concept is used to design a stable and fast feedback control. The loop-gain equation is derived

by the control-to-output transfer function times the compensation:

Loop–gain

Vod

Comp

The amplitude and the phase of this equation can be drawn with software such as MathCad. In turn, the stability

can be easily designed by adjusting the compensation parameters. The sample bode plot is shown below to

explain the phase margin, gain margin, and the crossover frequency.

The gain is drawn as 20 log (loop-gain), and the phase is in degrees. To explain them clearer, 180 degrees is

added to the phase, so that the gain and phase share the same zero.

The crossover frequency is the point at which the gain curve touches zero. The higher this frequency, the faster

the transient response, since the transient recovery time is 1/(crossover frequency). The phase is the phase

margin. The phase margin should be at least 60 degrees to cover all changes such as temperature. The gain

margin is the gap between the gain curve and the zero when the phase curve touches zero. This margin should

be at least 20 dB to guarantee stability over all conditions.

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APPLICATION INFORMATION

180

166

152

Phase

138

124

110

96

82

68

54

40

Phase

Margin

20 Log (Loop-Gain)

180 + Phase

26

12

–2

–16

–30

–44

–58

–72

Gain

Margin

Crossover

–86

–100

3

10

4

10

5

10

6

10

100

f – Frequency – Hz

synchronization

Some applications require switching clock synchronization. There are two methods that can be used for

synchronization: the triangle wave synchronization and the square wave synchronization.

The triangle wave synchronization is displayed below:

TPS5102

740 mV

Ct

Rt

740 mV

It can be seen that both Rt and Ct are removed from the circuit. Therefore, two components are saved. This

method is good for the synchronization between two controllers. If the controller needs to be synchronized with

a digital circuit such as DSP, the square-type clock signal is usually used. The configuration exhibited below is

for this type of application:

20

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APPLICATION INFORMATION

synchronization (continued)

TPS5102

Ct

Rt

An external resistor is added into the circuit, but Rt is still removed. Ct is kept to be a part of RC circuit generating

triangle waveform for the controller. Assuming the peak value of the square is known, the resistor and the

capacitor can be adjusted to achieve the correct peak-to-peak value and the offset value.

layout guidelines

Goodpowersupplyresultswillonlyoccurwhencareisgiventoproperdesignandlayout. Layoutwillaffectnoise

pickup and generation and can cause a good design to perform with less than expected results. With a range

of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult

than most general PCB designs. The general design should proceed from the switching node to the output,

then back to the driver section and, finally, parallel the low-level components. Below are several specific points

to consider before the layout of a TPS5102 design begins.

All sensitive analog components should be referenced to ANAGND. These include components connected

to Vref5, Vref, INV, LH, and COMP.

Analogground and drive ground should be isolated as much as possible. Ideally, analog ground will connect

to the ground side of the bulk storage capacitors on V , and drive ground will connect to the main ground

O

plane close to the source of the low-side FET.

Connections from the drivers to the gate of the power FETs should be as short and wide as possible to

reduce stray inductance. This becomes more critical if external gate resistors are not being used.

The bypass capacitor for V

should be placed close to the TPS5102.

CC

When configuring the high-side driver as a floating driver, the connection from LL to the power FETs should

be as short and as wide as possible.

When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from LH to

LL) should be placed close to the TPS5102.

When configuring the high-side driver as a ground-referenced driver, LL should be connected to DRVGND.

The bulk storage capacitors across V should be placed close to the power FETS. High-frequency bypass

In

capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the

high-side FET and to the source of the low-side FET.

High-frequency bypass capacitors should be placed across the bulk storage capacitors on V .

O

LH and LL should be connected very close to the drain and source, respectively, of the high-side FET. LH

and LL should be routed very close to each other to minimize differential-mode noise coupling to these

traces.

The output voltage sensing trace should be isolated by either ground trace or Vcc trace.

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APPLICATION INFORMATION

PWM AND SKIP MODE EFFICIENCY

COMPARISON

95

90

85

80

75

70

100

95

90

85

80

75

70

Output = 3.3 V

PWM Mode

Output = 5 V

Skip Mode

PWM Mode

Skip Mode

65

60

65

60

0

0.2

0.4

0.6

0.8

1

1.2

0

0.2

0.4

0.6

0.8

1

1.2

I

O

- Output Current - A

I

O

- Output Current - A

Figure 12

Figure 13

EFFICIENCY

vs

EFFICIENCY

vs

OUTPUT CURRENT

100

95

90

85

80

75

70

100

95

90

85

80

75

70

Output = 5 V

Output = 3.3 V

PWM Mode

Skip Mode

65

60

65

60

0

1

2

3

4

5

0

1

2

3

4

5

I

O

- Output Current - A

I

O

- Output Current - A

Figure 14

Figure 15

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APPLICATION INFORMATION

EFFICIENCY

vs

OUTPUT LOAD REGULATION

OUTPUT CURRENT

100

95

90

85

80

75

70

3.4

3.38

3.36

3.34

3.32

3.3

Output Load = 3.3 V

Dual Output Efficiency

3.28

3.26

3.24

65

60

3.22

3.2

0

20

40

60

80

100

0

1

2

3

4

5

I

O

- Output Current - A

Output Current – %

Figure 16

Figure 17

OUTPUT LOAD REGULATION

OUTPUT LINE REGULATION

5.1

5.08

5.06

5.04

5.02

5

3.4

3.38

3.36

3.34

3.32

3.3

Output Load = 5 V

Output Line = 3.3 V

4.98

4.96

4.94

3.28

3.26

3.24

4.92

4.9

3.22

3.2

0

1

2

3

4

5

0

10

20

30

I

O

- Output Current - A

V - Input Voltage - V

I

Figure 18

Figure 19

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APPLICATION INFORMATION

OUTPUT LINE REGULATION

DIODE VERSION EFFICIENCY

5.1

5.09

5.08

5.07

5.06

5.05

5.04

5.03

5.02

95

90

85

80

75

70

Output Line = 5 V

Output Diode Version = 3.3 V

65

60

5.01

5

10

15

20

25

30

0

1

2

3

4

5

V - Input Voltage - V

I

O

- Output Current - A

Figure 20

Figure 21

5–V OUTPUT VOLTAGE RIPPLE

3.3–V OUTPUT VOLTAGE RIPPLE

Figure 22

Figure 23

24

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APPLICATION INFORMATION

Table 1. Bill of Materials

REF.

PN

RV-35V221MH10-R

10TPB220M

GMK325F106ZH

4TPB470M

10TPB220M

6TPB330M

Standard

DESCRIPTION

Capacitor, electrolytic, 220 µF, 35 V

Capacitor, POSCAP, 220 µF, 10 V

Capacitor, ceramic, 10 µF, 35 V

Capacitor, POSCAP, 470 µF, 4 V

Capacitor, POSCAP, 220 µF, 10 V

Capacitor, POSCAP, 330 µF, 6.3 V

Open, capacitor, ceramic, 0.22 µF, 16 V

Capacitor, ceramic, 0,01 µF, 16 V

Capacitor, ceramic, 220 pF, 16 V

Capacitor, ceramic, 0.01 µF, 16 V

Capacitor, ceramic, 100 pF, 16 V

Capacitor, ceramic, 1 µF, 16 V

Capacitor, ceramic, 2.2 µF, 35 V

Capacitor, ceramic, 0.01 µF, 16 V

Capacitor, ceramic, 220 pF, 16 V

Capacitor, ceramic, 0.1 µF, 16 V

Open, capacitor, ceramic, 0.1 µF, 16 V

Capacitor, ceramic, 2.2 µF, 35 V

Open

MANUFACTURER

ELNA

SIZE

10x10mm

C1

†

C1 opt

C2

Sanyo

7.3x4.3mm

1210

Taiyo Yuden

Sanyo

C3

1210

C4

7.3x4.3mm

805

C5

Sanyo

†

C5 opt

Sanyo

†

C6

C7

C8

C9

Standard

805

Standard

805

Standard

805

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

D1

Standard

805

Standard

muRata

805

GMK316F225ZG

Standard

Taiyo Yuden

1206

805

Standard

805

Standard

805

†

Standard

805

GMK316F225ZG

Standard

Taiyo Yuden

1206

805

Standard

Open

805

GMK325F106ZH

GMK316F225ZG

Capacitor, ceramic, 10 µF, 35 V

Capacitor, ceramic, 2.2 µF, 35 V

Taiyo Yuden

1210

1206

†

7.3x4.3mm

SMC

MBRS340T3

Diode, Schottky, 40 V, 3 A

Diode, Schottky, 40 V, 200 mA

Inductor, 6.8 µH, 4.4 A

Motorola

Digikey

D2

MBRS340T3

SMC

D3

SD103-AWDICT-ND

DO3316P-682

3.5x1.5mm

0.5x0.37in

0.040in

D4

Digikey

L1

Coilcraft

NAS Interplex

L2

DO3316P-682

Inductor, 6.8 µH, 4.4 A

J1-J16

CA26DA-D36W-OFC

Edge connector, surface mount, 0.040” board, 0.090”

standoff

JP1

S1132-2-ND

Header, straight, 2-pin, 0.1 ctrs, 0.3” pins

Shunt, jumper, 0.1”

Sullins

DigiKey # 1132-2-ND

JP1 shunt

S1132-14-ND

DigiKey #

929950-00-ND

JP2

R1

S1132-14-ND

Standard

Header, straight, 2-pin, 0.1 ctrs, 0.3” pins

Resistor, 5.1 Ω, 5%

Open

Sullins

DigiKey # 1132-2-ND

805

R2

†

R3

R4

R5

R6

R8

Resistor, 1.21 kΩ, 1%

Resistor, 680 Ω, 1%

Resistor, 5.1 kΩ, 5%

Resistor, 1 kΩ, 5%

†

Option table

25

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APPLICATION INFORMATION

Table 1. Bill of Materials (continued)

REF.

PN

Standard

DESCRIPTION

Resistor, 82 kΩ, 5%

MANUFACTURER

SIZE

R9

805

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

Q1

Standard

Si4410DY

TPS5102

Resistor, 1 kΩ, 5%

805

Resistor, 0 Ω, 5%

805

Resistor, 1 kΩ, 5%

805

Reistor, 1 kΩ, 5%

805

Resistor, 310 kΩ, 1%

805

Resistor, 1 kΩ, 1%

805

†

Open resistor, 5.1 Ω, 5%

Resister, 15 Ω, 5%

805

Resistor, 7.5 kΩ, 5%

805

Resistor, 7.5 kΩ, 5%

805

Resistor, 15 Ω, 5%

805

Open

805

Transistor, MOSFET, n-ch, 30 V, 10 A, 13 mΩ,

IC, Dual Controller

Siliconix

TI

SO-8

TSSOP

Q2

Q3

Q4

U1

†

Option table

ThisEVMisdesignedtocoverasmanyapplicationsaspossible. Forsomemorespecificapplications, thecircuit

can be simpler. The table below gives some recommendations.

Table 2. EVM Application Recommendations

5V INPUT VOLTAGE

<3–A OUTPUT CURRENT

DIODE VERSION

Change C1 to low profile capacitor

Sanyo 10TPB220M (220 µF, 10 V)

Or 6TPB330M (330 µF, 6.3 V)

Change Q1/Q2 and Q3/Q4 to dual pack MOS- Remove Q2 and Q4 to reduce the cost.

FET, IRF7311 to reduce the cost.

Remove R12

Table 3. Vendor and Source Information

MATERIAL

MOSFETS (Q1–Q4)

SOURCE

In EVM Design

PART NUMBER

Si4410DY (SILICONIX)

DISTRIBUTORS

Local Distributor

Second Source

In EVM Design

IRF7811 (International Rectifier)

RV–35V221MH10–R (ELNA)

INPUT CAPACITORS (C1)

Bell Microproducts

972–783–4191

Second Source

35CV330AX/GX (Sanyo)

UUR1V221MNR1GS (Nichicon)

MBRS340T3 (Motorola)

U3FWJ44N (Toshiba)

870–633–5030

Future Electronics (Local Office)

Local Distributors

MAIN DIODES (D1 – D2)

INDUCTORS (L1 – L2)

In EVM Design

Second Source

In EVM Design

Second Source

Local Distributors

DO3316P–682 (Coilcraft)

CTDO3316P–682 (Inductor Warehouse) 800–533–8295

972–248-3575

CERAMIC CAPACITORS

(C2, C3) (C12, C17, C21)

IN EVM Design

GMK325F106ZH

GMK316F225ZG

(Taiyo Yuden)

SMEC

512–331–1877

Taiyo Yuden, Representative

e–mail: mike@millsales.com

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5102

DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER

SLVS239 - SEPTEMBER 1999

APPLICATION INFORMATION

Top Layer

Bottom Layer (Top View)

Top Assembly

27

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5102

DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER

SLVS239 - SEPTEMBER 1999

APPLICATION INFORMATION

+

Load

0 – 4 A

–

0 – 4 A

Power Supply

5–V, 5–A Supply

–

+

Test Setup

NOTE: All wire pairs should be twisted.

28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5102

DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER

SLVS239 - SEPTEMBER 1999

APPLICATION INFORMATION

High current applications are described in table . The values are recommendations based on actual test circuits.

Many variations are possible based on the requirements of the user. Performance of teh circuit is dependent

upon the layout rather than the on specific components, if the device parameters are not exceeded. The power

stage, having the highest current levels and greatest dv/dt rates, should be given the most attention, as both

the supply and load can be severly affected by the power levels and edge rates.

Table 4. High Current Applications

REFERENCE

DESIGNATIONS

FUNCTION

8-A OUTPUT

12-A OUTPUT

16-A OUTPUT

4x ELNA

2x ELNA

3x ELNA

C1

Input Bulk Capacitor

RV-35V221MH10-R

220 µF, 35 V

2x Taiyo Yuden

GMK325F106ZH

10 µF, 35 V

3x Taiyo Yuden

GMK325F106ZH

10 µF, 35 V

4x Taiyo Yuden

GMK325F106ZH

10 µF, 35 V

C2 (C3)

L1 (L2)

Input Bypass Capacitor

Output Filter Indicator

Coiltronics UP4B-1R5

1.5 µH, 13.4 A

MicorMetals T68-8/90

Core w/7T, #16

1.0 µH, 25 A

Coiltronics UP3B-2R2

2.2 µH, 9.2 A

2x Sanyo 4TPB470M

470 µF, 4 V

3x Sanyo 4TPB470M

470 µF, 4 V

4x Sanyo 4TPB470M

470 µF, 4 V

C4 (C22)

C5 (C23)

Q1 (Q3)

Q2 (Q4)

Output Filter Capacitor

Power Switch

2x Sanyo 6TPB330M

330 µF, 6.3 V

3x Sanyo 6TPB330M

330 µF, 6.3 V

4x Sanyo 6TPB330M

330 µF, 6.3 V

2x Siliconix Si4410DY

30 V, 10 A, 13 mΩ

3x Siliconix Si4410DY

30 V, 10 A, 13 mΩ

4x Siliconix Si4410DY

30 V, 10 A, 13 mΩ

2x Siliconix Si4410DY

30 V, 10 A, 13 mΩ

3x Siliconix Si4410DY

30 V, 10 A, 13 mΩ

4x Siliconix Si4410DY

30 V, 10 A, 13 mΩ

Power Switch

R17 (R20)

Gate Drive Resistor

7 Ω

5 Ω

4 Ω

R18 (R19)

Current Limit Resistor

10 kΩ

200 kHz

15 kΩ

150 kHz

20 kΩ

100 kHz

Switching Frequency

29

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS5102

DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER

SLVS239 - SEPTEMBER 1999

DBT (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

30 PINS SHOWN

0,27

0,17

M

0,50

30

0,08

16

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

15

0°-8°

0,75

0,50

A

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

28

30

38

44

50

DIM

7,90

7,70

7,90

7,70

9,80

9,60

11,10

12,60

12,40

A MAX

10,90

A MIN

4073252/D 09/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. Falls within JEDEC MO-153

30

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

型号:	TPS5102IDBR
生命周期：	Obsolete
包装说明：	,
Reach Compliance Code：	unknown
风险等级：	5.84
Base Number Matches：	1

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