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TPS51116

www.ti.com

SLUS609A–MAY 2004–REVISED JUNE 2004

COMPLETE DDR AND DDR2 MEMORY POWER SOLUTION

SYNCHRONOUS BUCK CONTROLLER, 3-A LDO, BUFFERED REFERENCE

FEATURES

DESCRIPTION

•

Synchronous Buck Controller (VDDQ)

The TPS51116 provides a complete power supply for

both DDR/SSTL-2 and DDR2/SSTL-18 memory sys-

tems. It integrates a synchronous buck controller with

a 3-A sink/source tracking linear regulator and

buffered low noise reference. The TPS51116 offers

the lowest total solution cost in systems where space

is at a premium. The TPS51116 synchronous control-

ler runs fixed 400kHz pseudo-constant frequency

PWM with an adaptive on-time control that can be

configured in D-CAP™ Mode for ease of use and

fastest transient response or in current mode to

support ceramic output capacitors. The 3-A

sink/source LDO maintains fast transient response

only requiring 20-µF (2 × 10 µF) of ceramic output

capacitance. In addition, the LDO supply input is

available externally to significantly reduce the total

power losses. The TPS51116 supports all of the

sleep state controls placing VTT at high-Z in S3

(suspend to RAM) and discharging VDDQ, VTT and

VTTREF (soft-off) in S4/S5 (suspend to disk). The

TPS51116 has all of the protection features including

thermal shutdown and is in a 20-pin HTSSOP

PowerPAD™ package.

– Wide-Input Voltage Range: 3.0-V to 28-V

– D–CAP™ Mode with 100-ns Load Step Re-

sponse

– Current Mode Option Supports Ceramic

Output Capacitors

– Supports Soft-Off in S4/S5 States

– Current Sensing from R_DS(on)or Resistor

– 2.5-V (DDR), 1.8-V (DDR2) or Adjustable

Output (1.5-V to 3.0-V)

– Equipped with Powergood, Overvoltage Pro-

tection and Undervoltage Protection

•

3-A LDO (VTT), Buffered Reference (VREF)

– Capable to Sink and Source 3 A

– LDO Input Available to Optimize Power

Losses

– Requires only 20-µF Ceramic Output Ca-

pacitor

– Buffered Low Noise 10-mA Output

– Accuracy ±20 mV for both VREF and VTT

– Supports High-Z in S3 and Soft-Off in S4/S5

– Thermal Shutdown

APPLICATIONS

•

DDR/DDR2 Memory Power Supplies

•

SSTL-2 SSTL-18 and HSTL Termination

TYPICAL APPLICATION

(DDR2)

C1

Ceramic

V

IN

TPS51116PWP

C5

Ceramic

2 × 10 µF

1

2

3

VLDOIN VBST 20

L1

1 µH

VTT

0.9 V

2 A

0.1 µF

VTT

DRVH 19

VDDQ

1.8 V

10 A

VTTGND

LL 18

GND

C8

SP−CAP

2 × 150 µF

4

5

6

7

8

9

VTTSNS DRVL 17

C3

Ceramic

GND

PGND 16

CS 15

2 × 10 µF

R1

C4

MODE

VTTREF

Ceramic

0.033 µF

V5IN 14

VREF

5V_IN

0.9 V

R2

10 mA

COMP PGOOD 13

VDDQSNS S5 12

C2

PGOOD

S5

Ceramic

4.7 µF

GND

10 VDDQSET S3 11

S3

UDG−04058

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS51116

www.ti.com

SLUS609A–MAY 2004–REVISED JUNE 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device

placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

T_A

PLASTIC HTTSOP PowerPAD (PWP)⁽¹⁾

-40°C to 85°C

TPS51116PWP

(1) The PWP package is also available taped and reeled. Add an R

suffix to the device type (TPS51116PWPR)

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range unless otherwise noted

TPS51116

-0.3 to 36

-0.3 to 6

UNITS

VBST

VBST wrt LL

V_IN

Input voltage range

V

CS, MODE, S3, S5, VTTSNS, VDDQSNS, V5IN, VLDOIN, VDDQSET

-0.3 to 6

PGND, VTTGND

DRVH

-0.3 to 0.3

-1.0 to 36

-1.0 to 30

-0.3 to 6

V_OUTOutput voltage range LL

COMP, DRVL, PGOOD, VTT, VTTREF

Operating ambient temperature range

Storage temperature

V

T_A

-40 to 85

-55 to 150

°C

T_stg

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage

values are with respect to the network ground terminal unless otherwise noted.

DISSIPATION RATINGS

T_A< 25°C POWER

DERATING FACTOR

ABOVE T_A= 25°C

PACKAGE

T_A= 85°C POWER RATING

RATING

20-pin PWP

2.53 W

25.3 mW/°C

1.01 W

RECOMMENDED OPERATING CONDITIONS

MIN

4.75

-0.1

-0.6

-0.1

MAX

5.25

34

UNIT

Supply voltage, V5IN

V

VBST, DRVH

LL

28

VLDOIN, VTT, VTTSNS, VDDQSNS

VTTREF

3.6

1.8

0.1

Voltage range

V

PGND, VTTGND

S3, S5, MODE, VDDQSET, CS, COMP, PGOOD,

DRVL

-0.1

-40

5.25

85

Operating free-air temperature, T_A

°C

2

TPS51116

www.ti.com

SLUS609A–MAY 2004–REVISED JUNE 2004

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, V_V5IN= 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)

PARAMETER

SUPPLY CURRENT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

T_A= 25°C, No load, V_S3= V_S5= 5 V,

COMP connected to capacitor

I_V5IN1

I_V5IN2

I_V5IN3

Supply current 1, V5IN

Supply current 2, V5IN

Supply current 3, V5IN

0.8

300

240

2

600

500

mA

T_A= 25°C, No load, V_S3= 0 V, V_S5= 5 V,

COMP connected to capacitor

T_A= 25°C, No load, V_S3= 0 V, V_S5= 5 V,

V_COMP= 5 V

µA

I_V5INSDN

I_VLDOIN1

I_VLDOIN2

I_VLDOINSDN

Shutdown current, V5IN

Supply current 1, VLDOIN

Supply current 2, VLDOIN

Standby current, VLDOIN

T_A= 25°C, No load, V_S3= V_S5= 0 V

T_A= 25°C, No load, V_S3= V_S5= 5 V

T_A= 25°C, No load, V_S3= 5 V, V_S5= 0 V,

T_A= 25°C, No load, V_S3= V_S5= 0 V

0.1

1

1.0

10

0.1

10

1.0

VTTREF OUTPUT

V_VTTREF

Output voltage, VTTREF

V_VDDQSNS/2

V

-10 mA < I_VTTREF< 10 mA, V_VDDQSNS= 2.5 V,

Tolerance to V_VDDQSNS/2

-20

-18

20

18

V_VTTREFTOL

Output voltage tolerance

mV

-10 mA < I_VTTREF< 10 mA, V_VDDQSNS= 1.8 V,

Tolerance to V_VDDQSNS/2

V_VTTREFSRC

V_VTTREFSNK

VTT OUTPUT

Source current

Sink current

V_VDDQSNS= 2.5 V, V_VTTREF= 0 V

V_VDDQSNS= 2.5 V, V_VTTREF= 2.5 V

-20

20

-40

40

-80

80

mA

V

V_S3= V_S5= 5 V, V_VLDOIN= V_VDDQSNS= 2.5 V

V_S3= V_S5= 5 V, V_VLDOIN= V_VDDQSNS= 1.8 V

V_S3= V_S5= 5 V, I_VTT= 0 A

1.25

0.9

V_VTTSNS

Output voltage, VTT

-20

-30

-40

-20

-30

-40

20

30

40

20

30

40

VTT output voltage tolerance

to VTTREF

V_VTTTOL25

V_S3= V_S5= 5 V, |I_VTT| = 0 A < 1.5 A

V_S3= V_S5= 5 V, |I_VTT| = 0 A < 3 A

V_S3= V_S5= 5 V, I_VTT= 0 A

mV

VTT output voltage tolerance

to VTTREF

V_VTTTOL18

V_S3= V_S5= 5 V, |I_VTT| = 0 A < 1 A

V_S3= V_S5= 5 V, |I_VTT| = 0 A < 2 A

V_VLDOIN= V_VDDQSNS= 2.5 V, V_VTT= V_VTTSNS

1.19 V, PGOOD = HI

=

3.0

1.5

3.0

3.8

2.2

3.6

2.2

6.0

3.0

6.0

I_VTTTOCLSRC

Source current limit, VTT

Sink current limit, VTT

V_VLDOIN= V_VDDQSNS= 2.5 V, V_VTT= 0 V

A

V_VLDOIN= V_VDDQSNS= 2.5 V, V_VTT= V_VTTSNS

1.31 V, PGOOD = HI

=

I_VTTTOCLSNK

V_VLDOIN= V_VDDQSNS= 2.5 V, V_VTT= V_VDDQ

V_S3= 0 V, V_S5= 5 V, V_VTT= V_VDDQSNS/2

V_S3= 5 V, V_VTTSNS= V_VDDQSNS/2

1.5

-10

-1

3.0

10

1

I_VTTLK

Leakage current, VTT

I_VTTBIAS

I_VTTSNSLK

Input bias current, VTTSNS

Leakage current, VTTSNS

-0.1

17

µA

V_S3= 0 V, V_S5= 5 V, V_VTT= V_VDDQSNS/2

-1

1

T_A= 25°C, V_S3= V_S5= V_VDDQSNS= 0 V,

V_VTT= 0.5 V

I_VTTDisch

Discharge current, VTT

10

mA

VDDQ OUTPUT

T_A= 25°C, V_VDDQSET= 0 V, No load

0°C ≤ T_A≤ 85°C, V_VDDQSET= 0 V, No load⁽¹⁾

2.465

2.457

2.440

1.776

1.769

1.764

1.5

2.500

1.800

2.535

2.543

2.550

1.824

1.831

1.836

3.0

(1)

-40°C ≤ T_A≤ 85°C, V_VDDQSET= 0 V, No load

T_A= 25°C, V_VDDQSET= 5 V, No load⁽¹⁾

0°C ≤ T_A≤ 85°C, V_VDDQSET= 5V, No load⁽¹⁾

-40°C ≤ T_A≤ 85°C, V_VDDQSET= 5V, No load⁽¹⁾

-40°C ≤ T_A≤ 85°C, Adjustable mode, No load⁽¹⁾

V_VDDQ

Output voltage, VDDQ

V

(1) Ensured by design. Not production tested.

3

TPS51116

www.ti.com

SLUS609A–MAY 2004–REVISED JUNE 2004

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, V_V5IN= 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A= 25°C, Adjustable mode

MIN

742.5

740.2

738.0

TYP

750.0

215

MAX

757.5

759.8

762.0

UNIT

V_VDDQSET

VDDQSET regulation voltage 0°C ≤ T_A≤ 85°C, Adjustable mode

-40°C ≤ T_A≤ 85°C, Adjustable mode

V_VDDQSET= 0 V

mV

R_VDDQSNS

Input impedance, VDDQSNS V_VDDQSET= 5 V

Adjustable mode

180

kΩ

460

V_VDDQSET= 0.78 V, COMP = Open

Input current, VDDQSET

-0.04

-0.06

I_VDDQSET

µA

V_VDDQSET= 0.78 V, COMP = 5 V

V_S3= V_S5= 0 V, V_VDDQSNS= 0.5 V,

I_VDDQDisch

Discharge current, VDDQ

V_MODE= 0 V

10

40

mA

V_S3= V_S5= 0 V, V_VDDQSNS= 0.5 V,

Discharge current, VLDOIN

I_VDDOINDisch

700

V_MODE= 0.5 V

TRANSCONDUCTANCE AMPLIFIER

gm

Gain

T_A= 25°C

240

300

13

360

µS

µA

COMP maximum sink cur-

rent

V_S3= 0 V, V_S5= 5 V, V_VDDQSET= 0 V,

V_VDDQSNS= 2.7 V, V_COMP= 1.28 V

I_COMPSNK

COMP maximum source cur- V_S3= 0 V, V_S5= 5 V, V_VDDQSET= 0 V,

rent

I_COMPSRC

V_COMPHI

V_COMPLO

-13

1.34

1.21

V_VDDQSNS= 2.3 V, V_COMP= 1.28 V

V_S3= 0 V, V_S5= 5 V, V_VDDQSET= 0 V,

V_VDDQSNS= 2.3 V, V_CS= 0 V

COMP high clamp voltage

1.31

1.18

1.37

1.24

V

V_S3= 0 V, V_S5= 5 V, V_VDDQSET= 0 V,

V_VDDQSNS= 2.7 V, V_CS= 0 V

COMP low clamp voltage

DUTY CONTROL

T_ON

Operating on-time

V_IN= 12 V, V_VDDQSET= 0 V

V_IN= 12 V, V_VDDQSNS= 0 V

520

125

100

350

T_ON0

Startup on-time

Minimum on-time

Minimum off-time

ns

(2)

T_ON(min)

T_OFF(min)

T_A= 25°C

T_A= 25°C⁽²⁾

OUTPUT DRIVERS

Source, I_DRVH= -100 mA

Sink, I_DRVH= 100 mA

Source, I_DRVL= -100 mA

Sink, I_DRVL= 100 mA

3

0.9

3

6

3

6

3

R_DRVH

R_DRVL

T_D

DRVH resistance

Ω

DRVL resistance

Dead time

0.9

10

20

(2)

LL-low to DRVL-on

ns

DRVL-off to DRVH-on⁽²⁾

INTERNAL BST DIODE

V_FBST

Forward voltage

V_V5IN-VBST, I_F= 10 mA, T_A= 25°C

0.7

0.8

0.1

0.9

1.0

V

V_VBST= 34 V, V_LL= 28 V, V_VDDQ= 2.6 V,

T_A= 25°C

I_VBSTLK

VBST leakage current

µA

(2) Ensured by design. Not production tested.

4

TPS51116

www.ti.com

SLUS609A–MAY 2004–REVISED JUNE 2004

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, V_V5IN= 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)

PARAMETER

PROTECTIONS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_PGND-CS, PGOOD = HI, V_CS< 0.5 V

V_PGND-CS, PGOOD = LO, V_CS< 0.5 V

T_A= 25°C, V_CS> 4.5 V, PGOOD = HI

T_A= 25°C, V_CS> 4.5 V, PGOOD = LO

50

20

9

60

30

10

5

70

40

11

6

V_OCL

Current limit threshold

mV

I_TRIP

Current sense sink current

µA

4

TRIP current temperature co- R_DS(on)sense scheme, On the basis

TC_ITRIP

V_OCL(off)

V_R(trip)

4500

0

ppm/°C

(3)

efficient

of T_A= 25°C

Overcurrent protection

COMP offset

(V_V5IN-CS- V_PGND-LL), V_V5IN-CS= 60 mV,

V_CS> 4.5 V

-5

5

mV

Current limit threshold setting

range

(3)

V_V5IN-CS

30

150

POWERGOOD COMPARATOR

PG in from lower

93%

95%

105%

5%

97%

V_TVDDQPG

VDDQ powergood threshold PG in from higher

103%

107%

PG hysteresis

I_PG(max)

T_PG(del)

PGOOD sink current

PGOOD delay time

V_VTT= 0 V, V_PGOOD= 0.5 V

Delay for PG in

2.5

80

7.5

mA

µs

130

200

UNDERVOLTAGE LOCKOUT/LOGIC THRESHOLD

Wake up

3.7

0.2

4.7

4.0

0.3

4.3

0.4

V5IN UVLO threshold volt-

age

V_UVV5IN

Hysteresis

No discharge

Non-tracking discharge

2.5 V output

1.8 V output

S3, S5

V_THMODE

MODE threshold

0.1

0.25

4.5

0.08

3.5

0.15

4.0

V

V_THVDDQSET

VDDQSET threshold voltage

V_IH

High-level input voltage

Low-level input voltage

Hysteresis voltage

2.2

V_IL

S3, S5

0.3

V_IHYST

V_INLEAK

V_INVDDQSET

S3, S5

0.2

Logic input leakage current

Input leakage/ bias current

S3, S5, MODE

VDDQSET

-1

1

µA

µs

UNDERVOLTAGE AND OVERVOLTAGE PROTECTION

OVP detect

Hysteresis

110%

115%

5%

120%

VDDQ OVP trip threshold

voltage

V_OVP

VDDQ OVP propagation de-

lay

T_OVPDEL

V_UVP

T_UVPDEL

T_UVPEN

1.5

(3)

UVP detect

Hysteresis

70%

10%

Output UVP trip threshold

Output UVP propagation de-

lay⁽³⁾

Output UVP enable delay⁽³⁾

32

cycle

1007

THERMAL SHUTDOWN

Shutdown temperature

Hysteresis

160

10

(3)

T_SDNThermal SDN threshold

°C

(3) Ensured by design. Not production tested.

5

TPS51116

www.ti.com

SLUS609A–MAY 2004–REVISED JUNE 2004

DEVICE INFORMATION

PWP PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

VLDOIN

VTT

VTTGND

VTTSNS

GND

MODE

VTTREF

COMP

VBST

DRVH

LL

DRVL

PGND

CS

V5IN

PGOOD

S5

VDDQSNS

VDDQSET

S3

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Output of the transconductance amplifier for phase compensation. Connect to V5IN to disable

gm amplifier and use D-CAP™ mode.

COMP

8

I/O

Current sense comparator input (-) for resistor current sense scheme. Or over current trip voltage

setting input for R_DS(on)current sense scheme if connected to V5IN through the voltage setting

resistor.

CS

15

DRVH

DRVL

GND

19

17

5

O

-

Switching (top) MOSFET gate drive output.

Rectifying (bottom) MOSFET gate drive output.

Signal ground. Connect to minus terminal of the VTT LDO output capacitor.

Switching (top) MOSFET gate driver return. Current sense comparator input (-) for R_DS(on)current

sense.

LL

18

I/O

MODE

PGND

6

I

Discharge mode setting pin. See VDDQ and VTT Discharge Control section.

16

-

Ground for rectifying (bottom) MOSFET gate driver. Also current sense comparator input (+).

Powergood signal open drain output, In HIGH state when VDDQ output voltage is within the

target range.

PGOOD

13

O

S3

11

12

14

20

10

I

S3 signal input.

S5

I

S5 signal input.

V5IN

VBST

VDDQSET

I

I/O

I

5-V power supply input for internal circuits.

Switching (top) MOSFET driver bootstrap voltage input.

VDDQ output voltage setting pin. See VDDQ Output Voltage Selection section.

VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge current

sinking terminal for VDDQ Non-tracking discharge. Output voltage feedback input for VDDQ

output if VDDQSET pin is connected to V5IN or GND.

VDDQSNS

9

I/O

VLDOIN

VTT

1

2

3

7

4

I

O

-

Power supply for the VTT LDO.

Power output for the VTT LDO.

VTTGND

VTTREF

VTTSNS

Power ground output for the VTT LDO.

O

I

VTTREF buffered reference output.

Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output capacitor.

6

TPS51116

www.ti.com

SLUS609A–MAY 2004–REVISED JUNE 2004

FUNCTIONAL BLOCK DIAGRAM

7

TPS51116

www.ti.com

SLUS609A–MAY 2004–REVISED JUNE 2004

DETAILED DESCRIPTION

The TPS51116 is an integrated power management solution which combines a synchronous buck controller, a

10-mA buffered reference and a high-current sink/source low-dropout linear regulator (LDO) in a small 20-pin

HTSSOP package. Each of these rails generates VDDQ, VTTREF and VTT that required with DDR/DDR2

memory systems. The switch mode power supply (SMPS) portion employs external N-channel MOSFETs to

support high current for DDR/DDR2 memory’s VDD/VDDQ. The output voltage is preset and selectable from 2.5

V or 1.8 V. User defined output voltage is also possible and can be adjustable from 1.5 V to 3 V. Input voltage

range of the SMPS is 3 V to 28 V. The SMPS runs an adaptive on-time PWM operation at high-load condition

and automatically reduces frequency to keep excellent efficiency down to several mA. Current sensing scheme

uses either R_DS(on)of the external rectifying MOSFET for a low-cost, loss-less solution, or an optional sense

resistor placed in series to the rectifying MOSFET for more accurate current limit. The output of the switcher is

sensed by VDDQSNS pin to generate one-half VDDQ for the 10-mA buffered reference (VTTREF) and the VTT

active termination supply. The VTT LDO can source and sink up to 3-A peak current with only 20-µF (two 10 µF

in parallel) ceramic output capacitors. VTTREF tracks VDDQ/2 within ±20 mV. VTT output tracks VTTREF within

±20 mV at no load condition while ±40 mV at full load. The LDO input can be separated from VDDQ and

optionally connected to a lower voltage by using VLDOIN pin. This helps reducing power dissipation in sourcing

phase. TheTPS51116 is fully compatible to JEDEC DDR/DDR2 specifications at S3/S5 sleep state (see Table 2).

The part has two options of output discharge function when both VTT and VDDQ are disabled. The tracking

discharge mode discharges VDDQ and VTT outputs through the internal LDO transistors and then VTT output

tracks half of VDDQ voltage during discharge. The non-tracking discharge mode discharges outputs using

internal discharge MOSFETs which are connected to VDDQSNS and VTT. The current capability of these

discharge FETs are limited and discharge occurs more slowly than the tracking discharge. These discharge

functions can be disabled by selecting non-discharge mode.

VDDQ SMPS, Dual PWM Operation Modes

The main control loop of the SMPS is designed as an adaptive on-time pulse width modulation (PWM) controller.

It supports two control schemes which are a current mode and a proprietary D-CAP™ mode. D-CAP™ mode

uses internal compensation circuit and is suitable for low external component count configuration with an

appropriate amount of ESR at the output capacitor(s). Current mode control has more flexibility, using external

compensation network, and can be used to achieve stable operation with very low ESR capacitor(s) such as

ceramic or specialty polymer capacitors.

These control modes are selected by the COMP terminal connection. If the COMP pin is connected to V5IN,

TPS51116 works in the D-CAP™ mode, otherwise it works in the current mode. VDDQ output voltage is

monitored at a feedback point voltage. If VDDQSET is connected to V5IN or GND, this feedback point is the

output of the internal resistor divider inside VDDQSNS pin. If an external resistor divider is connected to

VDDQSET pin, VDDQSET pin itself becomes the feedback point (see VDDQ Output Voltage Selection section).

At the beginning of each cycle, the synchronous top MOSFET is turned on, or becomes ON state. This MOSFET

is turned off, or becomes OFF state, after internal one shot timer expires. This one shot is determined by V_INand

V_OUTto keep frequency fairly constant over input voltage range, hence it is called adaptive on-time control (see

PWM Frequency and Adaptive On-Time Control section). The MOSFET is turned on again when feedback

information indicates insufficient output voltage and inductor current information indicates below the over current

limit. Repeating operation in this manner, the controller regulates the output voltage. The synchronous bottom or

the rectifying MOSFET is turned on each OFF state to keep the conduction loss minimum. The rectifying

MOSFET is turned off when inductor current information detects zero level. This enables seamless transition to

the reduced frequency operation at light load condition so that high efficiency is kept over broad range of load

current.

In the current mode control scheme, the transconductance amplifier generates a target current level

corresponding to the voltage difference between the feedback point and the internal 750 mV reference. During

the OFF state, the PWM comparator monitors the inductor current signal as well as this target current level, and

when the inductor current signal comes lower than the target current level, the comparator provides SET signal

to initiate the next ON state. The voltage feedback gain is adjustable outside the controller device to support

various types of output MOSFETs and capacitors. In the D-CAP™ mode, the transconductance amplifier is

disabled and the PWM comparator compares the feedback point voltage and the internal 750 mV reference

during the OFF state. When the feedback point comes lower than the reference voltage, the comparator provides

SET signal to initiate the next ON state.

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DETAILED DESCRIPTION (continued)

VDDQ SMPS, Light Load Condition

TPS51116 automatically reduces switching frequency at light load condition to maintain high efficiency. This

reduction of frequency is achieved smoothly and without increase of V_OUTripple or load regulation. Detail

operation is described as follows. As the output current decreases from heavy load condition, the inductor current

is also reduced and eventually comes to the point that its valley touches zero current, which is the boundary

between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when

this zero inductor current is detected. As the load current further decreased, the converter runs in discontinuous

conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires next

ON cycle. The ON-time is kept the same as that in the heavy load condition. In reverse, when the output current

increase from light load to heavy load, switching frequency increases to the constant 400 kHz as the inductor

current reaches to the continuous conduction. The transition load point to the light load operation I_OUT(LL)(i.e. the

threshold between continuous and discontinuous conduction mode) can be calculated in Equation 1:

(V

V

)

V

IN

OUT

1

I

+

OUT(LL)

2 L f

V

IN

(1)

where

•

f is the PWM switching frequency (400 kHz)

Switching frequency versus output current in the light load condition is a function of L, f, V_INand V_OUT, but it

decreases almost proportional to the output current from the I_OUT(LL)given above. For example, it is 40 kHz at

I_OUT(LL)/10 and 4 kHz at I_OUT(LL)/100.

Low-Side Driver

The low-side driver is designed to drive high-current, low-R_DS(on), N-channel MOSFET(s). The drive capability is

represented by its internal resistance, which are 3 Ω for V5IN to DRVL and 0.9 Ω for DRVL to PGND. A

dead-time to prevent shoot through is internally generated between top MOSFET off to bottom MOSFET on, and

bottom MOSFET off to top MOSFET on. 5-V bias voltage is delivered from V5IN supply. The instantaneous drive

current is supplied by an input capacitor connected between V5IN and GND. The average drive current is equal

to the gate charge at V_GS= 5 V times switching frequency. This gate drive current as well as the high-side gate

drive current times 5 V makes the driving power which needs to be dissipated from TPS51116 package.

High-Side Driver

The high-side driver is designed to drive high-current, low-R_DS(on)N-channel MOSFET(s). When configured as a

floating driver, 5-V bias voltage is delivered from V5IN supply. The average drive current is also calculated by the

gate charge at V_GS= 5V times switching frequency. The instantaneous drive current is supplied by the flying

capacitor between VBST and LL pins. The drive capability is represented by its internal resistance, which are 3 Ω

for VBST to DRVH and 0.9 Ω for DRVH to LL.

Current Sensing Scheme

In order to provide both good accuracy and cost effective solution, TPS51116 supports both of external resistor

sensing and MOSFET R_DS(on)sensing. For resistor sensing scheme, an appropriate current sensing resistor

should be connected between the source terminal of the bottom MOSFET and PGND. CS pin is connected to the

MOSFET source terminal node. The inductor current is monitored by the voltage between PGND pin and CS pin.

For R_DS(on)sensing scheme, CS pin should be connected to V5IN through the trip voltage setting resistor, R_TRIP

.

In this scheme, CS terminal sinks 10-µA I_TRIPcurrent and the trip level is set to the voltage across the R_TRIP. The

inductor current is monitored by the voltage between PGND pin and LL pin so that LL pin should be connected to

the drain terminal of the bottom MOSFET. I_TRIPhas 4500ppm/°C temperature slope to compensate the

temperature dependency of the R_DS(on). In either scheme, PGND is used as the positive current sensing node so

that PGND should be connected to the proper current sensing device, i.e. the sense resistor or the source

terminal of the bottom MOSFET.

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TPS51116

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DETAILED DESCRIPTION (continued)

PWM Frequency and Adaptive On-Time Control

TPS51116 employs adaptive on-time control scheme and does not have a dedicated oscillator on board.

However, the device runs with fixed 400-kHz pseudo-constant frequency by feed-forwarding the input and output

voltage into the on-time one-shot timer. The on-time is controlled inverse proportional to the input voltage and

proportional to the output voltage so that the duty ratio is kept as V_OUT/V_INtechnically with the same cycle time.

Although the TPS51116 does not have a pin connected to VIN, the input voltage is monitored at LL pin during

the ON state. This helps pin count reduction to make the part compact without sacrificing its performance. In

order to secure minimum ON-time during startup, feed-forward from the output voltage is enabled after the output

becomes 750 mV or larger.

VDDQ Output Voltage Selection

TPS51116 can be used for both of DDR (V_VDDQ= 2.5 V) and DDR2 (V_VDDQ= 1.8 V) power supply and adjustable

output voltage (1.5 V < V_VDDQ< 3 V) by connecting VDDQSET pin as shown in Table 1.

Table 1. VDDQSET and Output Voltages

VDDQSET

GND

VDDQ (V)

2.5

VTTREF and VTT

V_VDDQSNS/2

NOTE

DDR

V5IN

1.8

V_VDDQSNS/2

DDR2

FB Resistors

Adjustable

V_VDDQSNS/2

1.5 V < V_VDDQ< 3 V

VTT Linear Regulator and VTTREF

TPS51116 integrates high performance low-dropout linear regulator that is capable of sourcing and sinking

current up to 3 A. This VTT linear regulator employs ultimate fast response feedback loop so that small ceramic

capacitors are enough to keep tracking the VTTREF within ±40 mV at all conditions including fast load transient.

To achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should

be connected to the positive node of VTT output capacitor(s) as a separate trace from VTT pin. For stable

operation, total capacitance of the VTT output terminal can be equal to or greater than 20 µF. It is recommended

to attach two 10-µF ceramic capacitors in parallel to minimize the effect of ESR and ESL. If ESR of the output

capacitor is greater than 2 mΩ, insert an RC filter between the output and the VTTSNS input to achieve loop

stability. The RC filter time constant should be almost the same or slightly lower than the time constant made by

the output capacitor and its ESR. VTTREF block consists of on-chip 1/2 divider, LPF and buffer. This regulator

also has sink and source capability up to 10 mA. Bypass VTTREF to GND by a 0.033-µF ceramic capacitor for

stable operation.

Outputs Management by S3, S5 Control

In the DDR/DDR2 memory applications, it is important to keep VDDQ always higher than VTT/VTTREF including

both start-up and shutdown. TPS51116 provides this management by simply connecting both S3 and S5

terminals to the sleep-mode signals such as SLP_S3 and SLP_S5 in the notebook PC system. All of VDDQ,

VTTREF and VTT are turned on at S0 state (S3 = S5 = high). In S3 state (S3 = low, S5 = high), VDDQ and

VTTREF voltages are kept on while VTT is turned off and left at high impedance (high-Z) state. The VTT output

is floated and does not sink or source current in this state. In S4/S5 states (S3 = S5 = low), all of the three

outputs are disabled. Outputs are discharged to ground according to the discharge mode selected by MODE pin

(see VDDQ and VTT Discharge Control section). Each state code represents as follow; S0 = full ON, S3 =

suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF. (See Table 2)

Table 2. S3 and S5 Control

STATE

S0

S3

HI

S5

HI

VDDQ

VTTREF

VTT

On

S3

LO

HI

Off (Hi-Z)

Off (Discharge)

S4/S5

LO

Off (Discharge)

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DETAILED DESCRIPTION (continued)

Soft-Start and Powergood

The soft start function of the SMPS is achieved by ramping up reference voltage and two-stage current clamp. At

the starting point, the reference voltage is set to 650 mV (87% of its target value) and the overcurrent threshold

is set half of the nominal value. When UVP comparator detects VDDQ become greater than 80% of the target,

the reference voltage is raised toward 750 mV using internal 4-bit DAC. This takes approximately 85 µs. The

overcurrent threshold is released to nominal value at the end of this period. The powergood signal waits another

45 µs after the reference voltage reaches 750 mV and the VDDQ voltage becomes good (above 95% of the

target voltage), then turns off powergood open-drain MOSFET.

The soft-start function of the VTT LDO is achieved by current clamp. The current limit threshold is also changed

in two stages using an internal powergood signal dedicated for LDO. During VTT is below the powergood

threshold, the current limit level is cut into 60% (2.2 A).This allows the output capacitors to be charged with low

and constant current that gives linear ramp up of the output. When the output comes up to the good state, the

overcurrent limit level is released to normal value (3.8 A). TPS51116 has an independent counter for each

output, but the PGOOD signal indicates only the status of VDDQ and does not indicate VTT powergood

externally. See Figure 1.

100%

87%

80%

V

VDDQ

V

OCL

V

PGOOD

V

S5

85 µs

45 µs

UDG−04066

Figure 1. VDDQ Soft-Start and Powergood Timing

Soft-start duration, T_VDDQSS, T_VTTSSare functions of output capacitances.

2 C

V

0.8

VDDQ

T

+

) 85 ms

VDDQSS

I

VDDQOCP

(2)

(3)

where I_VDDQOCPis the current limit value for VDDQ switcher calculated by Equation 5.

C

V

VTT

T

+

VTTSS

I

VTTOCL

where, I_VTTOCL= 2.2 A (typ). In each of the two previous calculations, no load current during start-up are

assumed. Note that both switchers and the LDO do not start up with full load condition.

VDDQ and VTT Discharge Control

TPS51116 discharges VDDQ, VTTREF and VTT outputs during S3 and S5 are both low. There are two different

discharge modes. The discharge mode can be set by connecting MODE pin as shown in Table 3.

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DETAILED DESCRIPTION (continued)

Table 3. Discharge Selection

MODE

V5IN

DISCHARGE MODE

No discharge

VDDQ

S4/GND

Tracking discharge

Non-tracking discharge

When in tracking-discharge mode, TPS51116 discharges outputs through the internal VTT regulator transistors

and VTT output tracks half of VDDQ voltage during this discharge. Note that VDDQ discharge current flows via

VLDOIN to LDOGND thus VLDOIN must be connected to VDDQ output in this mode. The internal LDO can

handle up to 3 A and discharge quickly. After VDDQ is discharged down to 0.2 V, the internal LDO is turned off

and the operation mode is changed to the non-tracking-discharge mode.

When in non-tracking-discharge mode, TPS51116 discharges outputs using internal MOSFETs which are

connected to VDDQSNS and VTT. The current capability of these MOSFETs are limited to discharge slowly.

Note that VDDQ discharge current flows from VDDQSNS to PGND in this mode. In case of non-tracking mode,

TPS51116 does not discharge output charge at all.

Current Protection for VDDQ

The SMPS has cycle-by-cycle over current limiting control. The inductor current is monitored during the OFF

state and the controller keeps the OFF state during the inductor current is larger than the over current trip level.

The trip level and current sense scheme are determined by CS pin connection (see Current Sensing Scheme

section). For resistor sensing scheme, the trip level, V_TRIP, is fixed value of 60 mV.

For R_DS(on)sensing scheme, CS terminal sinks 10 µA and the trip level is set to the voltage across this R_TRIP

resistor.

V

(mV)

R

(kW) 10 (mA)

TRIP

(4)

As the comparison is done during the OFF state, V_TRIPsets valley level of the inductor current. Thus, the load

current at over current threshold, I_OCP, can be calculated as shown in Equation 5.

ǒ_V

Ǔ

V

* V

V

I

V

TRIP

IN

OUT

TRIP

RIPPLE

2

1

I

+

)

+

)

OCP

R

2 L f

V

DS(on)

IN

(5)

In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output

voltage tends to fall down. If the output voltage becomes less than Powergood level, the V_TRIPis cut into half and

the output voltage tends to be even lower. Eventually, it crosses the undervoltage protection threshold and

shutdown.

Current Protection for VTT

The LDO has an internally fixed constant over current limiting of 3.8 A while operating at normal condition. This

trip point is reduced to 2.2 A before the output voltage comes within ±5% of the target voltage or goes outside of

±10% of the target voltage.

Overvoltage and Undervoltage Protection for VDDQ

TPS51116 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage. If VDDQSET is

connected to V5IN or GND, the feedback voltage is made by an internal resistor divider inside VDDQSNS pin. If

an external resistor divider is connected to VDDQSET pin, the feedback voltage is VDDQSET voltage itself.

When the feedback voltage becomes higher than 115% of the target voltage, the OVP comparator output goes

high and the circuit latches as the top MOSFET driver OFF and the bottom MOSFET driver ON.

Also, TPS51116 monitors VDDQSNS voltage directly and if it becomes greater than 4 V TPS51116 turns off the

top MOSFET driver. When the feedback voltage becomes lower than 70% of the target voltage, the UVP

comparator output goes high and an internal UVP delay counter begins counting. After 32 cycles, TPS51116

latches OFF both top and bottom MOSFETs. This function is enabled after 1007 cycles of SMPS operation to

ensure startup.

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DETAILED DESCRIPTION (continued)

V5IN Undervoltage Lockout (UVLO) Protection

TPS51116 has V5IN undervoltage lock out protection (UVLO). When the V5IN voltage is lower than UVLO

threshold voltage, SMPS, VTTLDO and VTTREF are shut off. This is a non-latch protection.

V5IN Input Capacitor

Add a ceramic capacitor with a value between 1.0 µF and 4.7 µF placed close to the V5IN pin to stabilize 5 V

from any parasitic impedance from the supply.

Thermal Shutdown

TPS51116 monitors the temperature of itself. If the temperature exceeds the threshold value, 160°C (typ),

SMPS, VTTLDO and VTTREF are shut off. This is a non-latch protection and the operation is resumed when the

device is cooled down by about 10°C.

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TPS51116

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APPLICATION INFORMATION

Loop Compensation and External Parts Selection

Current Mode Operation

A buck converter using TPS51116 current mode operation can be partitioned into three portions, a voltage

divider, an error amplifier and a switching modulator. By linearizing the switching modulator, we can derive the

transfer function of the whole system. Since current mode scheme directly controls the inductor current, the

modulator can be linearized as shown in Figure 2.

Figure 2. Linearizing the Modulator

Here, the inductor is located inside the local feedback loop and its inductance does not appear in the small signal

model. As a result, a modulated current source including the power inductor can be modeled as a current source

with its transconductance of 1/R_Sand the output capacitor represent the modulator portion. This simplified model

is applicable in the frequency space up to approximately a half of the switching frequency. One note is, although

the inductance has no influence to small signal model, it has influence to the large signal model as it limits slew

rate of the current source. This means the buck converter’s load transient response, one of the large signal

behaviors, can be improved by using smaller inductance without affecting the loop stability.

Total open loop transfer function of the whole system is given by Equation 6.

H(s)

H (s) H (s) H (s)

1 2 3

(6)

Assuming RL>>ESR, R_O>>R_Cand C_C>>C_C2, each transfer function of the three blocks is shown starting with

Equation 7.

R2

R2 ) R1

H (s) +

1

(

)

(7)

_Oǒ_{1 ) s C R}_CǓ

R

C

H (s) + * gm

2

ǒ_{1 ) s C R}Ǔ ǒ_{1 ) s C}

R

C2

_CǓ

C

O

(8)

(9)

(1 ) s C ESR)

O

RL

H (s) +

3

R

ǒ_{1 ) s C RL}Ǔ

S

O

There are three poles and two zeros in H(s). Each pole and zero is given by the following five equations.

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APPLICATION INFORMATION (continued)

1

w

⁺ǒ_{C R}_OǓ

P1

C

(10)

(11)

(12)

(13)

(14)

1

w

⁺ǒ_{C RL}Ǔ

P2

O

1

R

w

⁺ǒ_C

_CǓ

P3

C2

1

⁺ǒ_{C R}_CǓ

w

Z1

C

1

⁺ǒ_{C ESR}Ǔ

w

Z2

O

Usually, each frequency of those poles and zeros is lower than the 0 dB frequency, f₀. However, the f₀should be

kept under 1/3 of the switching frequency to avoid effect of switching circuit delay. The f₀is given by Equation 15.

R

gm

C

S

0.75

C

S

1

2p

R1

R1 ) R2

1

2p

f +

+

0

C

R

V

C

R

O

OUT

O

(15)

Based on small signal analysis above, the external components can be selected by following manner.

1. Choose the inductor. The inductance value should be determined to give the ripple current of

approximately 1/4 to 1/3 of maximum output current.

ǒ_V

Ǔ

ǒ_V

Ǔ

* V

V

* V

V

IN(max)

OUT

IN(max)

OUT OUT

3

1

L +

+

I

f

V

I

f

V

IND(ripple)

IN(max)

OUT(max)

IN(max)

(16)

The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak

inductor current before saturation. The peak inductor current can be estimated as shown in Equation 17.

ǒ_V

Ǔ

* V

V

OUT

V

IN(max)

OUT

TRIP

1

I

+

)

IND(peak)

R

L f

V

DS(on)

IN(max)

(17)

2. Choose rectifying (bottom) MOSFET. When R_DS(on)sensing scheme is selected, the rectifying MOSFET’s

on-resistance is used as this R_Sso that lower R_DS(on)does not always promise better performance. In order

to clearly detect inductor current, minimum R_Srecommended is to give 15 mV or larger ripple voltage with

the inductor ripple current. This promises smooth transition from CCM to DCM or vice versa. Upper side of

the R_DS(on)is of course restricted by the efficiency requirement, and usually this resistance affects efficiency

more at high-load conditions. When using external resistor current sensing, there is no restriction for low

R_DS(on). However, the current sensing resistance R_Sitself affects the efficiency

3. Choose output capacitor(s). In cases of organic semiconductor capacitors (OS-CON) or specialty polymer

capacitors (SP-CAP), ESR to achieve required ripple value at stable state or transient load conditions

determines the amount of capacitor(s) need, and capacitance is then enough to satisfy stable operation. The

peak-to-peak ripple value can be estimated by ESR times the inductor ripple current for stable state, or ESR

times the load current step for a fast transient load response. In case of ceramic capacitor(s), usually ESR is

small enough to meet ripple requirement. On the other hand, transient undershoot and overshoot driven by

output capacitance becomes the key factor to determine the capacitor(s).

4. Determine f₀and calculate R_Cusing Equation 18. Note that higher R_Cshows faster transient response in

cost of unstableness. If the transient response is not enough even with high R_Cvalue, try increasing the out

put capacitance. Recommended f₀is f_OSC/4. Then R_Ccan be derived by Equation 19.

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APPLICATION INFORMATION (continued)

V

C

gm

OUT

O

R

v 2p f

R

0

C

S

0.75

(18)

(19)

R

2.8

V

C

[mF] R [mW]

C

OUT

O

S

5. Calculate C_C2. Purpose of this capacitance is to cancel zero caused by ESR of the output capacitor. In case

of ceramic capacitor(s) is used, no need for C_C2

.

1

w

+ w

p3

⁺ǒ_C

Ǔ

⁺ǒ_C

_CǓ

R

z2

ESR

O

C2

(20)

ǒ_{C ESR}Ǔ

O

C

+

C2

R

C

(21)

6. Calculate C_C. The purpose of C_Cis to cut DC component to obtain high DC feedback gain. However, as it

causes phase delay, another zero to cancel this effect at f₀frequency is need. This zero, ωz1, is determined

by Cc and Rc. Recommended ωz1 is 10 times lower to the f₀frequency.

f

0

1

f

+

z1

10

2p C R

C

(22)

7. When using adjustable mode, determine the value of R1 and R2. Recommended R2 value is from 100

kΩ to 300 kΩ. Determine R1 using Equation 23.

V

0.75

OUT

R1 +

R2

0.75

(23)

D-CAP™ Mode Operation

A buck converter system using D-CAP™ Mode can be simplified as below.

Figure 3. Linearizing the Modulator

The VDDQSNS voltage is compare with internal reference voltage after divider resistors. The PWM comparator

determines the timing to turn on top MOSFET. The gain and speed of the comparator is high enough to keep the

voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The DC output voltage

may have line regulation due to ripple amplitude that slightly increases as the input voltage increase.

For the loop stability, the 0-dB frequency, f₀, defined below need to be lower than 1/3 of the switching frequency.

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APPLICATION INFORMATION (continued)

f

SW

3

1

f +

v

0

2p ESR C

O

(24)

As f₀is determined solely by the output capacitor’s characteristics, loop stability of D-CAP™ mode is determined

by the capacitor’s chemistry. For example, specialty polymer capacitors (SP-CAP) have C_Oin the order of

several 100 µF and ESR in range of 10 mΩ. These makes f₀in the order of 100 kHz or less and the loop is then

stable. However, ceramic capacitors have f₀at more than 700 kHz, which is not suitable for this operational

mode.

Although D-CAP™ mode provides many advantages such as ease-of-use, minimum external components

configuration and extremely short response time, due to not employing an error amplifier in the loop, sufficient

amount of feedback signal needs to be provided by external circuit to reduce jitter level.

The required signal level is approximately 15 mV at comparing point. This gives V_RIPPLE= (V_OUT/0.75) x 15 (mV)

at the output node. The output capacitor’s ESR should meet this requirement.

The external components selection is much simple in D-CAP™ mode.

1. Choose inductor. This section is the same as the current mode. Please refer to the instructions in the

Current Mode Operation section.

2. Choose output capacitor(s).Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are

recommended. Determine ESR to meet required ripple voltage above. A quick approximation is shown in

Equation 25.

V

0.015

OUT

VOUT

ESR +

[

60 [mW]

I

0.75

I

RIPPLE

OUT(max)

(25)

Thermal Design

Primary power dissipation of TPS51116 is generated from VTT regulator. VTT current flow in both source and

sink directions generate power dissipation from the part. In the source phase, potential difference between

VLDOIN and VTT times VTT current becomes the power dissipation, W_DSRC

.

₊ǒ_V

Ǔ

I

W

* V

DSRC

VLDOIN

VTT

(26)

In this case, if VLDOIN is connected to an alternative power supply lower than VDDQ voltage, power loss can be

decreased.

For the sink phase, VTT voltage is applied across the internal LDO regulator, and the power dissipation, W_DSNK

,

is calculated by Equation 27:

W

V

I

VTT

DSNK

VTT

(27)

Since this device does not sink AND source the current at the same time and I_VTTvaries rapidly with time, actual

power dissipation need to be considered for thermal design is an average of above value. Another power

consumption is the current used for internal control circuitry from V5IN supply and VLDOIN supply. V5IN

supports both the internal circuit and external MOSFETs drive current. The former current is in the VLDOIN

supply can be estimated as 1.5 mA or less at normal operational conditions.

These powers need to be effectively dissipated from the package. Maximum power dissipation allowed to the

package is calculated by Equation 28,

T

A(max)

J(max)

W

+

PKG

q

JA

(28)

where

•

T_J(max)is 125°C

T_A(max)is the maximum ambient temperature in the system

θ_JAis the thermal resistance from the silicon junction to the ambient

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APPLICATION INFORMATION (continued)

This thermal resistance strongly depends on the board layout. TPS51116 is assembled in a thermally enhanced

PowerPAD™ package that has exposed die pad underneath the body. For improved thermal performance, this

die pad needs to be attached to ground trace via thermal land on the PCB. This ground trace acts as a heat

sink/spread. The typical thermal resistance, 39.6°C/W, is achieved based on a 6.5 mm × 3.4 mm thermal land

with eight vias without air flow. It can be improved by using larger thermal land and/or increasing vias number.

Further information about PowerPAD™ and its recommended board layout is described in (SLMA002). This

document is available at <www.ti.com>.

Layout Considerations

Certain points must be considered before designing a layout using the TPS51116.

•

PCB trace defined as LL node, which connects to source of switching MOSFET, drain of rectifying MOSFET

and high-voltage side of the inductor, should be as short and wide as possible.

Consider adding a small snubber circuit, consists of 3 Ω and 1 nF, between LL and PGND in case a

high-frequency surge is observed on the LL voltage waveform.

All sensitive analog traces such as VDDQSNS, VTTSNS and CS should placed away from high-voltage

switching nodes such as LL, DRVL or DRVH nodes to avoid coupling.

VLDOIN should be connected to VDDQ output with short and wide trace. If different power source is used for

VLDOIN, an input bypass capacitor should be placed to the pin as close as possible with short and wide

connection.

•

The output capacitor for VTT should be placed close to the pin with short and wide connection in order to

avoid additional ESR and/or ESL of the trace.

VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the

high current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to

sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point.

Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and

the output capacitor(s).

•

Consider adding LPF at VTTSNS in case ESR of the VTT output capacitor(s) is larger than 2 mΩ.

VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the

reference voltage of VTTREF. Avoid any noise generative lines.

•

Negative node of VTT output capacitor(s) and VTTREF capacitor should be tied together by avoiding

common impedance to the high current path of the VTT source/sink current.

GND (Signal GND) pin node represents the reference potential for VTTREF and VTT outputs. Connect GND

to negative nodes of VTT capacitor(s), VTTREF capacitor and VDDQ capacitor(s) with care to avoid

additional ESR and/or ESL. GND and PGND (power ground) should be connected together at a single point.

•

In order to effectively remove heat from the package, prepare thermal land and solder to the package’s

thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading.

Numerous vias with a 0.33-mm diameter connected from the thermal land to the internal/solder-side ground

plane(s) should be used to help dissipation. Do NOT connect PGND to this thermal land underneath the

package.

18

TPS51116

www.ti.com

SLUS609A–MAY 2004–REVISED JUNE 2004

APPLICATION INFORMATION (continued)

Figure 4. D-CAP™ Mode

Table 4. D-CAP™ Mode Schematic Components

SYMBOL

R1

SPECIFICATION

5.1 kΩ

MANUFACTURER

PART NUMBER

-

R2

100 kΩ

-

R3

(100 ×V_VDDQ- 75) kΩ

75 kΩ

-

R4

-

M1

30 V, 13 mΩ

30 V, 5 mΩ

International Rectifier

IRF7821

IRF7832

M2

19

TPS51116

www.ti.com

SLUS609A–MAY 2004–REVISED JUNE 2004

Figure 5. Current Mode

Table 5. Current Mode

SYMBOL

R0

SPECIFICATION

MANUFACTURER

Vishay

PART NUMBER

6 mΩ, 1%

100 kΩ

WSL-2521 0.006

R2

-

M0

30 V, 13 mΩ

30 V, 5 mΩ

International Rectifier

IRF7821

IRF7832

M1

20

TPS51116

www.ti.com

SLUS609A–MAY 2004–REVISED JUNE 2004

TYPICAL CHARACTERISTICS

V5IN SUPPLY CURRENT

V5IN SHUTDOWN CURRENT

vs

JUNCTION TEMPERATURE

vs

JUNCTION TEMPERATURE

1.0

0.9

0.8

0.7

2.0

1.8

1.6

1.4

0.6

0.5

0.4

1.2

1.0

0.8

0.3

0.2

0.6

0.4

0.1

0

0.2

0

−50

0

50

100

150

0

50

100

150

T − Junction Temperature − °C

J

T − Junction Temperature − °C

J

Figure 6.

Figure 7.

V5IN SUPPLY CURRENT

vs

VLDOIN SUPPLY CURRENT

vs

LOAD CURRENT

TEMPERATURE

10

9

1.0

DDR2

= 0.9 V

V

VTT

0.9

0.8

0.7

8

7

6

0.6

0.5

0.4

5

4

3

2

0.3

0.2

1

0.1

0

−50

−2

−1

0

1

2

0

50

100

150

I

− VTT Current − A

T − Junction Temperature − °C

J

VTT

Figure 8.

Figure 9.

21

TPS51116

www.ti.com

SLUS609A–MAY 2004–REVISED JUNE 2004

TYPICAL CHARACTERISTICS (continued)

CS CURRENT

vs

JUNCTION TEMPERATURE

VDDQ DISCHARGE CURRENT

vs

JUNCTION TEMPERATURE

16

14

80

70

60

50

PGOOD = HI

12

10

8

40

30

6

PGOOD = LO

4

20

10

2

0

−50

0

50

100

150

−50

0

50

100

150

T − Junction Temperature − °C

J

T − Junction Temperature − °C

J

Figure 10.

Figure 11.

VTT DISCHARGE CURRENT

vs

JUNCTION TEMPERATURE

OVERVOLTAGE AND UNDERVOLTAGE THRESHOLD

vs

JUNCTION TEMPERATURE

30

140

120

100

80

25

20

15

10

V

OVP

V

UVP

60

−50

0

50

100

150

0

50

100

150

T − Junction Temperature − °C

J

T − Junction Temperature − °C

J

Figure 12.

Figure 13.

22

TPS51116

www.ti.com

SLUS609A–MAY 2004–REVISED JUNE 2004

TYPICAL CHARACTERISTICS (continued)

SWITCHING FREQUENCY

vs

SWITCHING FREQUENCY

vs

INPUT VOLTAGE

OUTPUT CURRENT

430

450

400

D-CAP Mode

DDR2

I

= 7 A

VDDQ

420

410

350

300

250

DDR

400

390

380

200

150

100

50

DDR2

DDR

D−CAP Mode

V

IN

= 12 V

370

0

4

8

12

16

20

24

28

0

2

4

6

8

10

I

− VDDQ Output Current − A

V

IN

− Input Voltage − V

VDDQ

Figure 14.

Figure 15.

VDDQ OUTPUT VOLTAGE

vs

OUTPUT CURRENT (DDR)

VDDQ OUTPUT VOLTAGE

vs

INPUT VOLTAGE (DDR2)

1.820

1.815

1.810

1.805

1.800

1.795

1.790

1.785

1.780

1.820

1.815

1.810

1.805

1.800

1.795

1.790

1.785

1.780

D−CAP Mode

I

= 0 A

VDDQ

I

= 10 A

VDDQ

D−CAP Mode

V

IN

= 12 V

0

2

4

6

8

10

4

8

12

16

20

24

30

I

− VDDQ Output Current − A

VDDQ

V

IN

− Input Voltage − V

Figure 16.

Figure 17.

23

TPS51116

www.ti.com

SLUS609A–MAY 2004–REVISED JUNE 2004

TYPICAL CHARACTERISTICS (continued)

VTT OUTPUT VOLTAGE

vs

OUTPUT CURRENT (DDR)

VTT OUTPUT VOLTAGE

vs

OUTPUT CURRENT (DDR2)

0.94

0.93

0.92

0.91

0.90

0.89

0.88

0.87

0.86

1.30

1.29

1.28

1.27

1.26

V

= 1.8 V

VLDOIN

V

= 2.5 V

VLDOIN

1.25

1.24

1.23

1.22

V

= 1.5 V

VLDOIN

V

= 1.2 V

VLDOIN

V

= 1.8 V

0

VLDOIN

1.21

1.20

−3

−2

−1

0

1

2

3

−5 −4 −3 −2 −1

1

2

3

4

5

I

− VTT Output Current − A

I

− VTT Output Current − A

VTT

Figure 18.

Figure 19.

VTTREF OUTPUT VOLTAGE

vs

OUTPUT CURRENT (DDR)

VTTREF OUTPUT VOLTAGE

vs

OUTPUT CURRENT (DDR2)

1.252

1.251

1.250

1.249

1.248

0.904

0.903

0.902

0.901

0.900

DDR2

DDR

1.247

1.246

0.899

0.898

1.245

1.244

0.897

0.896

−10

−5

0

5

10

−10

−5

0

5

10

I

− VTTREF Current − A

I

− VTTREF Current − A

VTTREF

Figure 20.

Figure 21.

24

TPS51116

www.ti.com

SLUS609A–MAY 2004–REVISED JUNE 2004

TYPICAL CHARACTERISTICS (continued)

VDDQ EFFICIENCY (DDR)

vs

VDDQ EFFICIENCY (DDR2)

vs

VDDQ CURRENT

100

V

IN

= 8 V

V

IN

= 8 V

V

VDDQ

= 2.5 V

V

VDDQ

= 1.8 V

90

80

90

80

V

IN

= 12 V

V

IN

= 20 V

V

IN

= 12 V

V

IN

= 20 V

70

60

70

60

50

0.001

0.01

0.1

1

10

0.001

0.01

I

0.1

1

10

I

− VDDQ Current − A

VDDQ

Figure 22.

Figure 23.

V

VDDQ

(50 mV/div)

V

VDDQ

(50 mV/div)

I

(2 A/div)

VDDQ

I

(5 A/div)

IND

V

(10 mV/div)

VTTREF

V

VTT

I

(5 A/div)

VDDQ

t − Time − 2 µs/div

t − Time − 20 µs/div

Figure 25. VDDQ Load Transient Response

Figure 24. Ripple Waveforms - Heavy Load Condition

25

TPS51116

www.ti.com

SLUS609A–MAY 2004–REVISED JUNE 2004

TYPICAL CHARACTERISTICS (continued)

V

VDDQ

(50 mV/div)

V

VTT

(20 mV/div)

S5

VDDQ

V

VTTREF

(20 mV/div)

VTTREF

PGOOD

I

VTT

(2 A/div)

I

= I

VTTREF

= 0 A

VDDQ

t − Time − 100 µs/div

Figure 27. VDDQ, VTT, and VTTREF Start-Up Waveforms

t − Time − 20 µs/div

Figure 26. VTT Load Transient Response

VDDQ

VTTREF

VTT

S5

VTT

S5

I

= I

VTT

= I

VTTREF

= 0 A

VDDQ

I

= I

VTT

= I

VTTREF

= 0 A

VDDQ

t − Time − 1 ms/div

Figure 29. Soft-Stop Waveforms Non-Tracking Discharge

t − Time − 200 µs/div

Figure 28. Soft-Start Waveforms Tracking Discharge

26

TPS51116

www.ti.com

SLUS609A–MAY 2004–REVISED JUNE 2004

TYPICAL CHARACTERISTICS (continued)

VDDQ BODE PLOT (CURRENT MODE)

VTT BODE PLOT, SOURCE (DDR2)

GAIN AND PHASE

vs

GAIN AND PHASE

vs

FREQUENCY

80

60

180

135

90

80

180

135

90

60

Phase

40

45

20

45

20

0

Gain

−45

−90

−135

−180

−20

−40

−60

−80

−20

−45

−90

−135

−180

Gain

−40

−60

I

= −1 A

VTT

I

= 7 A

VDDQ

−80

10 k

1 M

100 k

10 M

1 M

100 k

10 M

f − Frequency − Hz

Figure 30.

Figure 31.

VTT BODE PLOT, SINK (DDR2)

GAIN AND PHASE

vs

FREQUENCY

80

60

180

135

90

40

Phase

Gain

20

45

0

−20

−40

−60

−80

−45

−90

−135

−180

I

= 1 A

VTT

10 k

1 M

100 k

10 M

f − Frequency − Hz

Figure 32.

27

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

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Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

型号:	TPS51116PWP
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	TSSOP
包装说明：	HTSSOP, TSSOP20,.25
针数：	20
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	1 week
风险等级：	0.72
模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	CURRENT-MODE
控制技术：	PULSE WIDTH MODULATION
最大输入电压：	5.25 V
最小输入电压：	4.75 V
标称输入电压：	5 V
JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e4
长度：	6.5 mm
湿度敏感等级：	2
功能数量：	1
端子数量：	20
最高工作温度：	85 °C
最低工作温度：	-40 °C
最大输出电流：	6 A
封装主体材料：	PLASTIC/EPOXY
封装代码：	HTSSOP
封装等效代码：	TSSOP20,.25
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified
座面最大高度：	1 mm
子类别：	Switching Regulator or Controllers
表面贴装：	YES
切换器配置：	PUSH-PULL
最大切换频率：	400 kHz
温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING
端子节距：	0.65 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	4.4 mm
Base Number Matches：	1

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